CMOS circuit having a tensile stress layer overlying an NMOS transistor and overlapping a portion of compressive stress layer | Patent Publication Number 20090008718

US 20090008718 A1
Patent NumberUS 09373548 B2
Application Number12199659
Filled DateAug 27, 2008
Priority DateSep 18, 2006
Publication DateJan 8, 2009
Inventor/ApplicantsGen Pei
Scott D. Luning
Gen PEI
Scott D. LUNING
Johannes van MEER
Johannes van Meer
Patent Prosecution report image

Empower your practice with Patexia Publication Prosecution IP Module.

Get access to our exclusive rankings and unlock powerful data.

Looking for a Publication Attorney?

Get in touch with our team or create your account to start exploring a network of over 120K attorneys.