Systems and methods for hard error reduction in a solid state memory device | Patent Publication Number 20150220388

US 20150220388 A1
Patent NumberUS 09576683 B2
Application Number14178201
Filled DateFeb 11, 2014
Priority DateFeb 6, 2014
Publication DateAug 6, 2015
Inventor/ApplicantsYu Cai
Yunxiang Wu
Erich F. Haratsch
Patent Prosecution report image

Empower your practice with Patexia Publication Prosecution IP Module.

Get access to our exclusive rankings and unlock powerful data.

Looking for a Publication Attorney?

Get in touch with our team or create your account to start exploring a network of over 120K attorneys.