Semiconductor package and method using isolated Vss plane to accommodate high speed circuitry ground isolation | Patent Number 07646091
US 07646091 B2Filled DateApr 6, 2006
Priority DateApr 6, 2006
Publication DateOct 11, 2007
Expiration DateApr 5, 2026
Inventor/ApplicantsChok J. Chia
Maurice O. Othieno
Amar J. Amin
Maurice O. Othieno
Amar J. Amin
ExaminesCRUZ, LESLIE PILAR
Art Unit2826
Technology Center2800
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