Method and system for reducing inter-layer capacitance in integrated circuits | Patent Number 07396760
US 07396760 B2Filled DateNov 17, 2004
Priority DateNov 17, 2004
Publication DateMay 18, 2006
Expiration DateNov 17, 2024
Inventor/ApplicantsPaul G. Filseth
Neal Callan
Kunal N. Taravade
Neal Callan
Kunal N. Taravade
ExaminesPICARDAT, KEVIN M
Art Unit2822
Technology Center2800
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