Memory interface system and method for reducing cycle time of sequential read and write accesses using separate address and data buses | Patent Number 07142477

US 07142477 B1
Application Number10871825
Publication Number-
Pendency2 years, 5 months, 13 days
Filled DateJun 18, 2004
Priority DateJun 18, 2004
Publication Date-
Expiration DateJun 18, 2024
Inventor/ApplicantsJoseph Tzou
Suresh Parameswaran
Thinh Tran
ExaminesNGUYEN, NAM THANH
Art Unit2824
Technology Center2800
Assignments
Infineon Technologies Ag
Current
Cypress SemiconductorInfineon Technologies Ag
Original
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