DETAILED DESCRIPTION OF PRESENTLY PREFERRED EMBODIMENTS
In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail, so as not to obscure the present invention. Further, the presently preferred embodiments disclosed are for exemplary purposes only and other embodiments, such as those disclosed in the concurrently filed non-provisional applications entitled (i) DCDC Converter with Resonant Gate Drive, (ii) DCDC Converter with Current Control, (iii) Synchronous Switched Boost and Buck Converter, and (iv) DCDC Converter with Single Gate Drive, may be employed in lieu of or in combination with of the embodiments disclosed.
1. Exemplary Architecture
FIG. 1 is a schematic diagram of a monolithic battery charger 100. The battery charger 100 may be fabricated as (i) an integral part of a multifunctional integrated circuit, (ii) one or more independent monolithically formed integrated circuits, (iii) a single independent monolithically formed integrated circuit, and/or (iv) any other monolithic or hybrid formation.
FIG. 1 illustrates an external DC input supply 110 coupled to a step-down converter 112 having a given duty ratio. The step-down converter 112, in turn, is coupled to a battery-terminal interface 114, which supplies an output voltage and output current having an output power ranging from approximately 1 watt to approximately 100 watts that may be used to charge a rechargeable battery. The output power, however, may be greater than or less than this exemplary range.
It is contemplated that the step-down converter 112 and other components of the battery charger 100 may be fabricated using Silicon/Gallium Arsenide (Si/GaAs), Silicon/Germanium (SiGe), and/or Silicon/Carbide (SiC) fabricating techniques. Included amongst these techniques are Complementary Metal Oxide Semiconductor (CMOS) fabrication processes, Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) fabrication processes, Heterojunction Bipolar Transistor (HBT) fabrication processes, and/or Metal Semiconductor Field Effect Transistor (MESFET) fabrication processes.
The external DC input supply 110 may be any DC supply capable of supplying between a high side terminal 116 and a low-side or ground terminal 118 an input voltage from the range of approximately 1.5 volts to approximately 20 volts, and a corresponding input current from approximately 1 mA to approximately 10 A. The value of the input voltage and current supplied by the external DC input supply, however, may be higher or lower than these ranges. For instance, the values may be adjusted for dissipation losses caused by the attached circuitry and caused by any terminal interconnections between external DC input supply 110, the step-down converter 112, and battery-terminal interface 114.
In one alternative, the value of input voltage may be selected by starting with the desired output voltage and multiplying it by the inverse of the duty ratio. Similarly, the value of the corresponding input current may be selected by starting with the desired output current and multiplying it by the duty ratio. Other functions may be used for determining the value of the input voltage and corresponding input current, as well.
As noted above, coupled to the DC input supply 110 is the step-down converter 112. The step-down converter 112 includes a monolithically-formed DCDC converter 120 in standard buck-style configuration (hereinafter referred to as a synchronous-buck regulator), which may include several components including at least one (i) monolithically or discretely formed capacitor 122, (ii) monolithically or discretely formed inductor 124, (iii) monolithically-formed controller 126, (iv) monolithically-formed switch 128, and (v) monolithically-formed rectifier 130.
In standard buck-style configuration, the switch 128, when closed, couples the high-side terminal 116 of the DC input supply 110 to a first terminal of the inductor 124 at a first node 132. The rectifier 130 is coupled between the first node 132 and the ground terminal 118 of DC input supply 110, so that when the switch 128 is closed the voltage across the rectifier 130 in an ideal circuit is approximately the input voltage.
In the standard buck-type configuration, one side of the capacitor 122 is coupled to a second side of the inductor 124 at a high-side output node 134. And a second side of the capacitor 122 is coupled to the ground terminal 118 of DC input supply 110 at the low-side output node 136.
As noted above, the battery-terminal interface 114 is coupled to the step-down converter 112. In one embodiment, the battery-terminal interface 114 includes a high-side-input terminal 138 coupled to a high-side-output terminal 140. In another embodiment, the high-side-input terminal 138 and the high-side-output terminal 140 are the same terminal. The battery-terminal interface 114 may also include a low-side-input terminal 142 coupled to a low-side-output terminal 144. Paralleling, the high-side terminal of the battery-terminal interface, the low-side-input terminal 142 and the low-side-output terminal 144 may be the same terminal. To couple the step-down converter 112 to battery-terminal interface 114, the high-side-output node 134 of the step-down converter 112 may be coupled to the high-side-input terminal 138, and the low-side-output node 136 of the step-down converter 112 may be coupled to the low-side-input terminal 142. The output voltage and current that emanates from the battery-terminal interface 114 may be supplied between the high-side-output terminal 140 and the low-side-output terminal 144.
Referring to the components of the monolithically-formed DCDC converter 120, the architecture of switch 128 may include (i) one or more enhancement or depletion mode P-channel metal oxide semiconductor (PMOS) transistors, (ii) one or more enhancement or depletion mode N-channel metal oxide semiconductor (NMOS) transistors, (iii) one or more PMOS switches, (iv) one or more NMOS switches, and/or (v) any other monolithic switch capable of switching at frequencies of at least one MHz. The architecture of rectifier 130 may include (i) one or more diodes; (ii) one or more synchronous rectifiers, which may be constructed from one or more enhancement or depletion mode NMOS or PMOS transistors; and/or (iii) any other monolithic rectifier having the ability to switch from a conducting state to a non-conducting state at a frequency in excess of approximately one MHz.
In one exemplary embodiment, when the architecture of switch 128 and the rectifier 130 are configured as transistors or semiconductor switches, the switch 128 and the rectifier 130 may be both constructed from the same type topology, e.g., the same NMOS or PMOS material. The switch architecture and the rectifier architecture, however, are preferably constructed as transistors or semiconductor switches having opposite type conduction channel materials. For example, when the switch 128 is constructed from PMOS, the rectifier 130 is preferably constructed from NMOS, and vice versa. One advantage of this topology is simplification of the controller 126.
This simplification is realized by the reduction in number of signals, and corresponding circuit traces, to switch 128 and the rectifier 130. Because the switch 128 and the rectifier 130 need to operate out of phase, one signal (from, e.g., a single gate driver) can control both, as opposed to when the switch 128 and the rectifier 130 are constructed with the same topology. In this opposite conduction channel configuration, delay mechanisms might not be necessary to prevent both the switch 128 and the rectifier 130 from turning on at the same time (which could happen if two of the same type conduction channel devices are used.).
In the opposite conduction channel configuration, when the rectifier 130 comprises a NMOS type rectifier, the physical gate length of the PMOS type switch to 128 is generally three to four times the gate length of the NMOS rectifier for the PMOS type switch to achieve same current carrying capacity and similar switch speeds as the NMOS rectifier. Given that the physical size of the PMOS type switch is larger than the NMOS type rectifier, which ultimately effects circuit and die size, NMOS type switches and rectifiers are preferred over PMOS type switches and rectifiers.
In one embodiment, the inductor 124 may be fabricated as a thin-film inductor having a value of approximately 100 millihenry and below. These thin film inductors may be formed atop, but are preferably integrated into, the same package or wafer die as the synchronous buck converter 120. While the inductor 124 may be formed directly atop the synchronous buck converter 120, one or more insulating or facilitative thin-film layers may separate the inductor 124 from the synchronous buck converter 120. These facilitative layers may include one or more sacrificial layers, (i.e., material used during processing to construct the final product, but not present in the final product), and/or one or more beneficial layers (i.e., material used during processing to construct the final product, and present in the final product).
Alternatively, the inductor 124 may be formed as a monolithic or discrete, off-chip, coil or spiral wire-wound inductor in (i) a hermetically-sealed (e.g., ceramic encased) leaded package, (ii) a hermetically-sealed surface mount, and/or (iii) flip chip form. Such inductors may be similar to the types of inductors commonly used in radio frequency (RF) type circuits operating in the range from about two Mhz to about five Mhz. These inductors are available from such suppliers as Murata Electronics North America, Inc., having offices at Corporate Headquarters 2200 Lake Park Drive, Smyrna, Ga. 30080-7604 U.S.A.; Bourns Inc., having offices at 1200 Columbia Avenue, Riverside, Calif. 9250, U.S.A.; CoilCraft having offices at 1102 Silver Lake Road, Cary Ill. 60013, U.S.A.; U.S. Microwaves A Division Of Semiconix Corporation having offices at 2964-2966 Scott Blvd Santa Clara, Calif. 95054, U.S.A.; Toko America, Inc. having offices at 1250 Feehanville Drive Mt. Prospect, Ill. 60056, U.S.A.; Kyocera America, Inc. having offices at 8611 Balboa Ave. San Diego, Calif. 92123-1580, U.S.A. Each of these suppliers can provide high accuracy, high Q inductors for high frequency as well as power applications. Other inductor materials and types, and other manufacturers may be used as well.
In addition to the other monolithic components, the architecture of the capacitor 122 may include a monolithically formed coupling capacitor having a storage capacity of approximately a few nanofarads and below. Similar to the inductor 124, the capacitor may be fabricated as a thin-film capacitor; similar in construction of the types commonly used in radio frequency (RF) type circuits operating in the range from about two Mhz to about five Mhz. These thin film capacitors may be preferably formed atop, but are preferably integrated into, the same package or wafer die as the synchronous buck converter. While the capacitor 122 may be formed directly atop the synchronous buck converter 120, one or more insulating or facilitative thin-film layers may separate the capacitor 124 from the synchronous buck converter 120.
Alternatively, the capacitor 122 may be formed as a monolithic or discrete, off-chip, capacitor in (i) a hermetically-sealed (e.g., ceramic or tantalum encased) leaded package, (ii) a hermetically-sealed surface mount, and/or (iii) flip chip form. These capacitors are available from any of the suppliers listed above. And each of these suppliers can provide capacitors for high frequency applications that exhibit high accuracy, and power low dissipation. Other capacitor materials and types, and other manufacturers may be used as well.
Referring again to the components of the monolithically-formed DCDC converter 120, the controller 126 causes the switch 128 to operate at a frequency in excess of approximately one MHz. In such an embodiment, the controller may include a pulse-width-modulator-feedback circuit 146 that includes a ramp generator operating in excess of approximately one MHz and an output to drive the switch 128 between a substantially conductive state (the ON state) and a substantially non-conductive state (the OFF state).
2. Exemplary Operation
The cyclical operation of an exemplary synchronous-buck regulator 120 to accomplish a voltage step-down from the DC input supply voltage Vin is as follows. Each time the switch 128 is in the ON state, the difference between Vin supplied between the high side terminal 116 and the ground terminal 118 and the output voltage Vout supplied between high-side output node 134 and the low-side output node 136 appears across inductor 124, which causes the current exiting the first node 132 to increase linearly through the inductor.
When the output voltage Vout reaches a desired or predetermined value, the controller 126 senses a change in the output voltage Vout and adjusts the duration of the pulse width modulation of the switch 128, accordingly. This adjustment may cause the switch to change from an ON state to an OFF state. Within a short delay period of approximately 0 to approximately 100, and preferably about 10 nanoseconds, the controller 126 may adjust the duration of the pulse width modulation of the rectifier 130. This may cause the rectifier 130 to switch from an OFF state to and ON state, assuming that the rectifier 130 is a synchronous rectifier. The delay period may be greater than and less than these numbers, and is preferably a sufficient delay to obtain optimal performance and efficiency. Additionally, the delay period may depend on the physical characteristics of the switch 128, the rectifier 130, and the controller 126.
If, on the other hand, the rectifier 130 is a diode (e.g., as a Schottky diode), the switching characteristics of the diode determines the amount of delay after switch 128 is turned to the OFF state. In an exemplary embodiment, the delay period for switching such diode should be comparable to the delay period of the synchronous rectifier.
Immediately after the switch 128 switches to the OFF state, the inductor current freewheels through rectifier 130 and through any load, including the load of any battery being charged, connected across the high-side output node 134 and the low-side output node 136. More specifically, once switch 128 turns off, the voltage across the rectifier 130 becomes negative and when the rectifier 130 reaches the forward bias voltage drop, it is simultaneously switched (or if the rectifier 130 comprises as diode, switches) from an OFF state to an ON state. After the rectifier 130 switches to the ON state, current flows through the forward-biased body diode of rectifier 130 and through the channel of the FET. Thereafter, the energy stored in the inductor 124 begins to decrease as current flows to the capacitor 122 and/or the load. Eventually, depending on the load condition, capacitor 122 will discharge through any connected load until the voltage at the output 134 begins to decrease.
The pulse-width pulse-width-modulator-feedback circuit 146 compares the output voltage Vout with a predetermined reference value to generate an error voltage signal. The controller 126 triggers the switch 128 to switch from the OFF state to the ON state in accordance with a ramp generator signal in conjunction with the error voltage signal, as is known in PWM controllers.
3. Combined Voltage and Current Feedback Control
Referring now to FIG. 2, a schematic diagram of a monolithic battery charger 200 is provided. The battery charger 200 illustrated in FIG. 2 is similar to the battery charger 100 illustrated in FIG. 1 in most respects, except as described herein or otherwise noted.
In the embodiment illustrated in FIG. 2, the controller 126, which operates in excess of one MHz, may include a current-sense feedback circuit 247 in combination with a voltage-controlled-feedback circuit 249 to prevent or limit overregulation caused by abrupt changes in the output voltage Vout sensed by the voltage-controlled-feedback circuit 249. Both the current-sense feedback circuit 247 and the voltage-controlled-feedback circuit 249 feed error signals to a pulse-width-modulator-feedback circuit 246. Based on the error signals, the pulse-width-modulator-feedback circuit 246 may adjust the duration or duty cycle of its outputted pulse-width signal. This adjusted-pulse width signal, which ultimately acts as a single gate driver for the switch 128 and the rectifier 130, in turn drives a buffer driver 251. Using the adjusted-pulse width signal, the buffer driver 251 simultaneously or otherwise synchronously drives the switch 128 and the rectifier 130 between their ON state and the OFF state, so that the state of the switch 128 and the state of the rectifier 130 operate as polar opposites.
Although illustrated with both current-sense feedback circuit 247 and a voltage-controlled-feedback circuit 249, the monolithic battery charger 200 may include only a current-sense feedback circuit. Alternatively, the monolithic battery charger 200 may have only a voltage-controlled-feedback circuit, as described above.
The current-sense-feedback circuit 247 includes a sense resistor 255 coupled between the inductor 124 and the capacitor 122. The sense resistor 255 has a first end coupled at a first-sense node 234(a) and a second end coupled at a second-sense node 234(b). Coupled across the sense resistor 255 are first and second inputs 255(a), 255(b) of a current-sense-feedback amplifier 257, which is preferably a differential amplifier having an output in addition to such first and second inputs. The current-sense-feedback amplifier 257 is operable to provide from its output an output signal, hereinafter referred to as a current-sense-error signal, which is proportional to the voltage detected the across the sense resistor 255. And because of the location of the sense resistor 255, the current-sense-error signal is directly proportional to the current of the inductor 124.
The output of the current-sense-feedback amplifier 257 is coupled to a combined-error amplifier 259 of the pulse-width-modulator-feedback circuit 246. The combined-error amplifier 259 is preferably a differential amplifier having a first input, a second input and an output. The current-sense-error signal is fed to the first input of the combined-error amplifier 259 by the output of the current-sense-feedback amplifier 257.
Coupled to the second input of the combined-error amplifier 259 is an output of the voltage-controlled-feedback circuit 249. The voltage-controlled-feedback circuit 249, which may sense changes in the output voltage Vout, feeds the second input of the combined-error amplifier 259 with an error output signal that is proportional to changes in Vout. This error output signal is hereinafter referred to as a voltage-sense-error signal. To facilitate providing such an output signal, the voltage-controlled-feedback circuit 249 includes a voltage-sense-feedback amplifier 261 (e.g., a differential amplifier) having a first input coupled to high-side output node 134. The voltage-sense-feedback amplifier 261 is operable to detect Vout or some voltage division thereof, and reference voltage Vref that is fed to its second input.
The current-sense-error signal provided to the first input of the combined-error amplifier 259 provides varying reference voltage for comparison with the voltage-sense-error signal provided to the second input of the combined-error amplifier 259. Based upon the current-sense error and voltage-sense error signals, the combined-error amplifier 259 feeds to a first input of a pulse-width-amplifier 263 a combined-error-output signal that may be used to adjust the duration of a pulse-width-modulation signal that is provided to a second input of the pulse-width-amplifier 263. An output of the pulse-width-amplifier 263 provides the adjusted-pulse-width-modulation signal, which acts as a single gate driver for driving the buffer driver 251, and in turn the switch 128 and the rectifier 130.
As noted, the buffer driver 251 simultaneously or otherwise synchronously drives the switch 128 and the rectifier 130 between their respective and polar opposite ON states and the OFF states. The buffer driver 251 may include one or more delay mechanisms to insure that when the switch 128 is in its ON state, the rectifier 130 is in its OFF state, and vice-versa. Referring now to FIG. 4, an exemplary buffer driver 251 is illustrated. The buffer-driver 251 includes an buffer-driver input 265 coupled to the output of the pulse-width-amplifier 263, a first-buffer-driver output 267 coupled to the switch 128, and a second-buffer-driver output 269 coupled to the rectifier 130.
Coupled between the buffer-driver input 265 and the first-buffer-driver output 267 is a first-logic-switch-driver-circuit 271 that includes a NOR gate 273. The NOR gate 273 has an output, a first input directly coupled to the buffer-driver input 265 and a second input coupled to the buffer-driver input 265 via four inverters, namely a first inverter 275, a second inverter 277, a third inverter 279, and a fourth inverter 281. The output of the NOR is coupled to a fifth inverter 283, which in turn is coupled to the first-buffer-driver output 267.
Similarly, coupled between the buffer-driver input 265 and the second-buffer-driver output 269 is a second-logic-switch-driver circuit 285. The second-logic-switch-driver circuit 285 has an input directly coupled to the buffer-driver input 265 and an output directly coupled to the second-buffer-driver output 269. Coupled to the input is a sixth inverter 287 that in turn is coupled to a seventh inverter 289. The seventh inverter 289 in turn is coupled to output of the second-logic-switch-driver circuit 285.
4. Buffer Driver Operation
The buffer driver 251 may operate as follows. When fed into the buffer-driver input 265, the adjusted-pulse-width-modulation signal is fed to both the first and second-logic-switch-driver-circuit 271, 285. Because of the propagation delay of each of the inverters and the NOR gate, the adjusted-pulse-width-modulation signal that is fed to the buffer-driver input 265 insures that when the switch 128 is in its ON state, the state of the rectifier 130 is in its OFF state, and vice-versa.
Starting with a transition from a low state to a high state of the adjusted-pulse-width-modulation signal that is fed directly to its first input, the NOR gate 273 of the first-logic-switch-driver-circuit 271 produces (or otherwise transitions from a high state signal to) a low state signal, regardless of the state of its other input. This low state signal is fed to the fifth inverter 283, which inverts it to a high state signal. The high state signal is then fed to the switch 128. When comprised of an enhancement-mode-p-channel MOSFET, this high state signal causes the switch 128 to enter its ohmic region and switch to its OFF state.
Because the NOR gate 273 and the fifth inverter 283 are in series, the high state signal that is fed to the switch 128 lags behind the high state of the adjusted-pulse-width-modulation signal by the combined propagation delay of the NOR gate 273 and the fifth inverter 283. While the propagation delay of the NOR gate 273 and the fifth inverter 283 may be of the same duration, preferably and in practice, the propagation delay of NOR gate 273 is less than the propagation delay of the fifth inverter 283.
When the transition from the low state to the high state of the adjusted-pulse-width-modulation signal is fed directly to the second-logic-switch-driver-circuit 285, the sixth inverter 287 inverts the high state of adjusted-pulse-width-modulation signal to produce a low state signal. This low state signal is fed to the seventh inverter 289, which inverts its incoming signal to produce a high state signal. The high state signal is then fed to the rectifier 130, which when comprised of a enhancement-mode-n-channel MOSFET, causes the rectifier 130 to enter its active region and switch to its ON state.
Like the NOR gate 273 and the fifth inverter 283, the sixth and seventh inverter 287, 289 are in series. And as such, the high state signal that is fed to the rectifier 130 lags behind the high state of the adjusted-pulse-width-modulation signal by the combined propagation delay of the sixth and seventh inverters 287, 289. The propagation delay of the sixth and seventh inverters 287, 289 may be of the same duration or different duration.
In addition, the individual propagation delay of the sixth and seventh inverters 287, 289 may have the same duration as the NOR gate 273 and the fifth inverter 283. Assuming no propagation delay difference for the pinch-off of a MOSFET constructed switch 128 and rectifier 130, preferably and in practice, the combined propagation delay of the sixth and seventh inverters 287, 289 is longer than the combined propagation delay of the NOR gate 273 and the fifth inverter 283. This insures that when the rectifier 130 switches to its ON state, the switch 128 is already in its OFF state.
Returning to the first-logic-switch-driver circuit 271, when the transition from the low state to the high state of the adjusted-pulse-width-modulation signal is fed to the first inverter 275, it inverts the signal, introduces its propagation delay, and feeds the inverted signal to the second inverter 277, which inverts the inverted signal, introduces its propagation delay, and produces a high state signal. The third and fourth inverters 279, 281, which both introduce their respective propagation delays, invert their incoming signals, and ultimately provide a high state signal provided to the NOR gate 273. Because the first input of the NOR gate 273 is already at a high state, the high state signal received on its second input does not change the low state signal emanating from the output of NOR gate (i.e., a high state signal applied to one or both of the NOR gate's inputs will cause the NOR gate 273 to output a low state signal).
When a transition from the high state to a low state of the adjusted-pulse-width-modulation signal is fed to the second-logic-switch-driver-circuit 285, the sixth inverter 287 inverts the low state of adjusted-pulse-width-modulation signal to produce a high state signal. This high state signal is fed to the seventh inverter 289, which inverts its incoming signal to produce a low state signal. The low state signal is then fed to the rectifier 130. When comprised of an enhancement-mode-n-channel MOSFET, the rectifier 130 enters its ohmic region and switches to its OFF state. Given that the sixth and seventh inverter 287, 289 are in series, the low state signal that is fed to the rectifier 130 lags behind the low state of the adjusted-pulse-width-modulation signal by the combined propagation delay of the sixth and seventh inverters 287, 289.
For at least the combined propagation delay of the first, second, third and fourth inverters 275, 277, 279, 281, the output of the first-logic-switch-driver circuit 271 remains unchanged after being fed the high-to-low state transitioning adjusted-pulse-width-modulation signal. Although the low state of the adjusted-pulse-width-modulation signal is fed directly to the first input of the NOR gate 273, the output of the NOR gate 273 continues to provide a low state signal for a period of time up until the fourth inverter 281 provides a low state signal. This period of time may be at least the combined propagation delay of the first, second, third and fourth inverters 275, 277, 279, 281.
When the fourth inverter eventually provides a low state signal to the second input of the NOR gate 273, the output of the NOR gate 273 produces a high state signal that is fed to the fifth inverter 285. The fifth inverter 285 ultimately supplies a high state signal to the switch 128. When comprised of an enhancement-mode-p-channel MOSFET, the switch enters its active region and switches to its ON state. Note that, after a high to low state transition of adjusted-pulse-width-modulation signal, when of the combined propagation delay of the NOR gate 273 and the first, second, third, fourth, and fifth inverters 275, 277, 279, 281 is greater than the combined propagation delay of the sixth and seventh inverters 287, 289, the rectifier 130 switches to its ON state while the switch 128 is still in its OFF state. This insures that the rectifier 130 and switch 128 operate as polar opposites.
Referring back to FIG. 2, each time switch 128 is in the ON state, the difference between Vin supplied between the high side terminal 116 and the ground terminal 118 and the output voltage Vout supplied between high-side output node 134 and the low-side output node 136 appears across inductor 124, which causes the current exiting the first node 132 to increase linearly through the inductor 124. This, in turn, causes the capacitor 122 to charge and the output voltage Vout to increase towards a desired value. When the output voltage Vout reaches a desired value, the voltage-sense-feedback amplifier 261 of the voltage-controlled-feedback circuit 249 senses the output voltage Vout which is compared to the reference voltage Vref to provide the voltage-sense-error signal to the combined-error amplifier 259.
As the current increases through the inductor 124, the current-sense-feedback circuit 247 via the sense resistor 255 and current-sense-feedback amplifier 257 detects the change in the inductor current and provides the current-sense-error signal to the first input of the combined-error amplifier 259. Since inductor current cannot change instantaneously, the voltage across the current sense resistor 255 likewise cannot change instantaneously. Thus, (i) under steady state conditions, (ii) in response to large transients, and/or (iii) under very low load conditions, this voltage has a small magnitude that varies only incrementally with the rate of change of the current in the inductor 124. As such, the current-sense-error signal provided to the combined-error amplifier 259 by the current-sense-feedback amplifier 257 does not change instantaneously, and provides a smoothing effect to the pulse width regulation.
The output of the combined-error amplifier 259 provides to the pulse-width amplifier 263 a combined-error-output signal that may be used as a varying reference for adjusting the duration or the duty cycle of the pulse-width modulation. This adjustment may cause the buffer driver 251 to drive the switch 128 from an ON state to an OFF state and drive the rectifier 130 from its OFF state to its ON, as described above.
After the switch 128 switches to the OFF state, the inductor current freewheels through rectifier 130 and through any load, including the load of any battery being charged, connected across the high-side output node 134 and the low-side output node 136. After the rectifier </
