Block level design method for heterogeneous PG-structure cells | Patent Application Number 18096906

18096906
Not Appealed
Patent NumberUS 11853678 B2
Publication NumberUS 20230153507 A1
Filled DateJan 13, 2023
Priority DateDec 15, 2016
Inventor/ApplicantsYuan-Te Hou
Yen-Hung Lin
Chung-Hsing Wang
ExaminesGARBOWSKI, LEIGH M
Art Unit2851
Technology Center2800
Assignments
Taiwan Semiconductor Manufacturing Company
Current
Taiwan Semiconductor Manufacturing Company
Original
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