2 but higher than the first reference Vref1, the second sub voltage regulating circuit 120 increases the second LDO current Ilod2 to accommodate the increased load current Ireg. Specifically, the second control signal Va2 provided by the second differential amplifier AMP2 decreases the second pass device MP2's resistance by increasing its gate-to-source voltage, so as to increase the second LDO current Ilod2. No current (i.e., the first LDO current Ildo1) is provided by the first sub voltage regulating circuit regulator 110 in this situation. When the feedback voltage Vfb becomes lower than or equal to the first reference Vref1, the first control signal Va1 generated by the first differential amplifier AMP1 enables providing of the first LDO current Ildo1 from the first input terminal 130 to the output terminal 150 by turning on the first pass device MP1. The first LDO current Ildo1 is provided together with the second LDO current ILDO2 to accommodate the increased load current and to regulate the output voltage Vreg to the first target voltage value V_target1. In an embodiment, the first sub voltage regulating circuit regulator 110 is enabled to provide the first LDO current Ildo1 at a time when the output voltage Vreg has reached a value (hereinafter referred to as an out-regulation value) that causes the second sub voltage regulating circuit 120 to fall out of regulation. Said out-regulation value is determined based on the second input voltage Vin_L, the second reference voltage Vref2, a magnification of the second error amplifier AMP2, and operating parameters (e.g., the minimum drain-to-source resistance (R_DS(on)and a corresponding gate-to-source voltage, ext.) of the second pass device MP2. Therefore, in an embodiment, the first reference voltage Vref1 is equal to said out-regulation value. In another embodiment, the first reference voltage Vref1 is equal to said out-regulation value plus a predetermined threshold value.

FIG. 2a shows a waveform graph illustrating waveforms of the load current Iload, the regulated voltage Vreg, the first LDO current Ildo1 flowing through the first sub voltage regulating circuit 110 (shown as LDO1 in FIG. 2a) and the second LDO current Ildo2 flowing through the second sub voltage regulating circuit 120 (shown as LDO2 in FIG. 2a) when a load transient occurs, in accordance with an embodiment of the present invention. In an embodiment, the load transient may occur, for example, when the dual-input LDO voltage regulating circuit 100's load (such as the other low-voltage circuit elements in the aforementioned step-down power converter) suddenly transits from high-speed operation state to an inactive state or vice versa.

From time t0 to time t1, the dual-input LDO voltage regulating circuit 100 is in a steady state (hereinafter referred to a second steady state). The first sub voltage regulating circuit 110 (or, LDO1) does not provide any current from the first input terminal 130 to the output terminal 150, and the second sub voltage regulating circuit 120 (or, LDO2) is working to provide the second LDO current Ildo2 from the second input terminal 140 to the output terminal 150 and convert the second input voltage Vin_L to the output voltage Vreg. In such second steady state, the load current Iload is at Iload2 which is equal to a value of the second LDO current Ildo2 provided by the second sub voltage regulating circuit 120 (or, LDO2), and the output voltage Vreg is regulated and maintained at the second target value V_target2 by the second sub voltage regulating circuit 120 (or LDO2).

At the time t1, the load current Iload suddenly steps from Iload2 to Iload1, which cause the output voltage Vreg to sag/decrease from V_target2.

From the time t1 to time t2, as shown in FIG. 2a, the resulting change in the output voltage is smaller than a difference between the first target voltage value V_target1 and the second target voltage value V_target2, which causes the feedback voltage Vfb being lower than the second reference voltage Vref2 but higher than the first reference voltage Vref1. Therefore, from the time t1 to the time t2, the first sub voltage regulating circuit 110 (or, LDO1) still does not provide the first LDO current Ildo1, and the second sub voltage regulating circuit 120 (or, LDO2) reacts to increase the second LDO current Ildo2 to accommodate the increased load current Iload. For example, the second control signal Va2 provided by the second differential amplifier AMP2 decreases the second pass device MP2's resistance by increasing the second pass device MP2's gate-to-source voltage, so as to increase the second LDO current Ildo2.

At the time t2, the second pass device MP2's resistance has decreased to its minimum drain-to-source resistance (R_DS(on)), so the second LDO current Ildo2 flowing through the second sub voltage regulating circuit 120 (or, LDO2) reaches a maximum constant level, i.e., the second sub voltage regulating circuit 120 (or, LDO2) is no longer be able to provide any additional current to accommodate the increased load current Iload or regulate the output voltage vreg anymore. At this time, the feedback voltage Vfb that is indicative of the output voltage Vreg becomes equal to the first reference voltage Vref1, causing the first PMPS pass device MP1 in the first sub voltage regulating circuit 110 (or, LDO1) to be turned on, so as to enable providing current (e.g., the first LDO current Ildo1) from the first input terminal 130 to the output terminal 150. As such, the first sub voltage regulating circuit 110 may assist in providing the first LDO current Ildo1 and regulating the output voltage Vreg without turning off the second sub voltage regulating circuit 120 when the second sub voltage regulating circuit 120 falls out of regulation. As a result, a undershoot may be reduced since there is no hard handover between the main power supply and the auxiliary power supply, i.e., first turning off the main power supply and then turning on the auxiliary power supply.

It should be understood that what shown in FIG. 2a is only an example, in other embodiment where the first reference voltage Vref1 is equal to said out-regulation value plus the predetermined threshold value, the first PMPS pass device MP1 may also be turned on before the time t2, that is, before the pass device MP2 reaches to its minimum drain-to-source resistance (R_DS(on).

Until time t3, the output current Iload (i.e., Ildo1+Ildo2) provided by LDO1 and LDO2 becomes larger than the load current Iload, which brings the output voltage Vreg up to the second target voltage value V_target2 at time t4. In other words, the dual-input LDO voltage regulating circuit 100 is brought to another steady state (hereinafter referred to as a first steady state) at the time t4. As can be seen from FIG. 2a, even when the dual-input LDO voltage regulating circuit 100 returns to the steady state (e.g., the first steady state), the output voltage Vreg is at a constant voltage value that is slightly lower than the second target voltage value V_target2 because the first LDO current Ildo1 has increased since the time t2.

From the time t4 to time t5, the dual-input LDO voltage regulating circuit 100 is maintained at the first steady state through the regulation of both the first sub voltage regulating circuit 110 (or, LDO1) and the second sub voltage regulating circuit 120 (or, LDO2).

At the time t5, the load resistance suddenly decreases, causing the load current Iload starts to decrease from Iload1 to Iload2), and causing the output voltage Vreg to rise/increase.

From the time t5 to time t6, the output voltage Vreg increases from the constant voltage value that is slightly lower than the first target voltage value V_target1 to the first target voltage value V_target1. During this period, LDO1 and LDO2 operate simultaneously to provide the first LDO current Ido1 and the second LDO current Ido2 to the output terminal 150. As the output voltage increases, the second pass device MP2's resistance remains at its minimum the time t5 to time t6, so the second LDO current Ildo2 stays unchanged. The first control signal Va1 drives the first pass device MP1's gate to increase MP1's resistance and decrease the first LDO current Ido1 flowing through LDO1, so as to accommodate the decreased load current Iload.

At the time t6, the feedback voltage Vfb that is indicative of the output voltage Vreg becomes higher than the first reference voltage Vref1. The first PMOS pass device MP1 is turned off to cutoff the first LDO current Ildo1. From this time, the pass device MP2 starts to increase from its minimum drain-to-source resistance (R_DS(on)), and the second LDO current Ildo2 flowing through the second sub voltage regulating circuit 120 (or, LDO2) starts to decrease. It should be understood that what shown in FIG. 2a is only an example. In other embodiment where the first reference voltage Vref1 is equal to said out-regulation value plus the predetermined threshold value, the first PMPS pass device MP1 may also be turned off after the time t6, that is, after the pass device MP2 starts to increase from its minimum drain-to-source resistance (R_DS(on)).

From the time t6 to time t7, the output voltage Vreg continues to increase. The first PMOS pass device MP1 remains off, and the second sub voltage regulating circuit 120 decreases the second LDO current Ilod2 to accommodate the decreased load current Iload and to regulate the output voltage Vreg back to the second target voltage value V_target2. Specifically, the second control signal Va2 provided by the second differential amplifier AMP2 increases the second pass device MP2's resistance by decreasing the second pass device MP2's gate-to-source voltage to decrease the second LDO current Ildo2.

Until the time t7, the output current (i.e., the second LDO current Ildo2 provided by LDO2) becomes lower than the load current Iload, which brings the output voltage Vreg down to the second target voltage value V_target2 at time t8. In other words, the dual-input LDO voltage regulating circuit 100 is brought to the second steady state at the time t8.

FIG. 2b shows a waveform graph illustrating waveforms of the second input voltage Vin_L, the regulated voltage Vreg, the first LDO current Ildo1 flowing through the first sub voltage regulating circuit 110 (shown as LDO1 in FIG. 2b) and the second LDO current Ildo2 flowing through the second sub voltage regulating circuit 120 (shown as LDO2 in FIG. 2b) when a line transient occurs, in accordance with an embodiment of the present invention. In an embodiment, the line transient may occur due to factors like the second input voltage Vin_L's variations or disturbances. As shown in FIG. 2b, the line transient response of the dual-input Voltage regulating circuit 100 is similar with that of the load transient response. The only difference is that decreases or increases of the output voltage Vreg in FIG. 2a is caused by the decrease or increase of the second input voltage Vin_L. In order to facilitate the description of the present invention, the description for the details of the waveforms in FIG. 2b is omitted.

As such, by setting the second reference voltage Vref2 to be higher than the first reference voltage Vref1, the lower input voltage Vin_L may act as the main power supply to provide the regulated voltage, and the higher input voltage Vin_H may assist in providing power only when the second voltage regulating circuit 120 falls or is about to fall out of regulation. In this way, the overall power loss and heat dissipation can be reduced. Moreover, a undershoot may also be reduced since there is no hard handover between the main power supply and the auxiliary power supply.

In the embodiment shown in FIG. 1, the first sub voltage regulating circuit 110 can assist in supplying current and regulate the output voltage when the second sub voltage regulating circuit 120 no longer has the ability to provide additional current. However, a delay time exist from a time when the feedback voltage Vfb becomes lower than the first reference voltage Vref1 to a time when the control signal Va1 turning on the first pass device MP1 in the first sub voltage regulating circuit 110 to enabling the providing of the first LDO current Ildo1 from the first input terminal 130 to the output terminal 150, which may inevitably increase the undershoot. The present invention proposes another improved dual-input voltage regulating circuit which may further reduce the undershoot on the output. FIG. 3 illustrates a circuit diagram of a dual-input Voltage regulating circuit 300, in accordance with another embodiment of the present invention.

As can be seen from FIG. 3, as compared with the dual-input voltage regulating circuit 100 as shown and described in FIG. 1 and FIGS. 2a to 2b, the dual-input voltage regulating circuit 300 shown in FIG. 3 further includes a clamping circuit 350 which is configured to reduce the time delay from the time when the feedback voltage Vfb becomes lower than the first reference voltage Vref1 to the time when the control signal Va1 turning on the first pass device MP1. Specifically, the clamping circuit 350 may clamp a voltage on a control terminal of the first pass device MP1 to a reference voltage Vclp, such that a gate-to-source voltage of the first pass device MP1 is kept at its minimum threshold voltage VGS(th). The clamping circuit 350 shown in FIG. 3 is only for illustration. The present invention may include any type of clamping circuit that may clamp the voltage on the control terminal of the first pass device MP1 to a certain value (for example, the reference voltage Vclp) such that the gate-to-source voltage of the first pass device MP