130, 230 and row address predecoder 140, 240, respectively, may be associated with memory structure 100, 200 as a whole (before partitioning). Column address predecode logic block 134, 234 can be configured to predecode Add_C such that Add_Cpd indicates a specific bank and column therein. Similarly, row address predecode logic block 144, 244 can be configured to predecode Add_R such that Add_Rpd indicates a specific bank and row therein. Such predecode logic blocks are known in the art and, thus, more specific details thereof have been omitted from the specification in order to allow the reader to focus on salient aspects of the disclosed embodiments (e.g., related to the novel components of predecoders discussed in greater detail below).

A redundancy logic block can, optionally, be included in a row address predecoder (e.g., see redundancy logic block 245 in row address predecoder 240 of memory structure 200 of FIG. 2). Such a redundancy logic block 245 can be configured to enable a row redundancy scheme. For example, in memory structure 200, performance can be improved through the use of one or more redundant rows of cells 201 (also referred to as spare or secondary rows) so that, if/when one or more cells in a primary row in a bank is/are determined to be defective, a redundant row (in the same or a different bank) can be used, thereby avoiding memory failures. To implement a redundancy scheme, defective row information can be stored in a defective row memory (e.g., a fused-based memory) and row redundancy logic block 245 (also referred to herein as a row redundancy control circuit) can be configured to determine whether or not to use a primary row (as indicated by the received row address signal) or one of the redundant rows, based on this defective row information, and can output the appropriate signals to make that happen. Such row redundancy logic blocks are known in the art and, thus, more specific details thereof have been omitted from the specification in order to allow the reader to focus on salient aspects of the disclosed embodiments (e.g., related to the novel components of predecoders discussed in greater detail below).

As mentioned above, in some NVM structures (e.g., in NVM structures that support sector erase or the like), in the column address predecoders and in the row address predecoders, the received address signal (i.e., a column address signal or a row address signal, as applicable) may be latched by an input address latch and then propagated through the write logic block during any type of memory operation (i.e., during both write and read operations). However, propagation of the address signal through the write logic block is not required for read operations and, thus, results in unnecessary delay in read operation setup time. In order to avoid this unnecessary added setup time delay during read operations, the disclosed predecoder embodiments each include a combination of first and second latches (also referred to herein as input and output latches) controlled by different write and read clock signals, respectively, and a multiplexer-enabled write logic bypass path. In these embodiments, during the read operations, processing by a write logic block is bypassed altogether and address signal predecoding is performed before the second latch is opened by a read clock signal. Thus, the setup time between receiving an address signal to outputting a predecoded address signal is significantly reduced during a read operation as compared to the setup time typically seen in prior art predecoders where only a single input address latch is included upstream of all logic blocks. Thus, the read cycle time is also significantly reduced over such conventional predecoders.

More specifically, referring to FIGS. 1 and 2, column address predecoder 130, 230 of memory structure 100, 200 can include a first signal node 139a, 239a (also referred to herein as a column address input node), which is connected to receive Add_C. Column address predecoder 130, 230 can further include a second signal node 139b, 239b (also referred to herein as a predecoded column address output node) for outputting Add_Cpd. Between first signal node 139a, 239a and second signal node 139b, 239b, column address predecoder 130, 230 can further include a multiplexer 133, 233. Multiplexer 133, 233 can include two input terminals: one input terminal 133a, 233a connected to first signal node 139a, 239a; and an additional input terminal 133b, 233b. Multiplexer 133, 233 can further include an output terminal 133c, 233c.

Column address predecoder 130, 230 can further include a first latch 131, 231 (also referred to herein as a column address input latch), which is controlled by a first clock signal (also referred to herein as a write clock signal (CLKw)), and a column address write logic block 132, 232 (e.g., including a column address counter, as discussed in above). First latch 131, 231 and write logic block 132, 232 can be series-connected between first signal node 139a, 239a and additional input terminal 133b, 233b of multiplexer 133, 233.

Column address predecoder 130, 230 can further include a column address predecode logic block 134, 234 (as discussed in greater detail above) and a second latch 137 (also referred to herein as a predecoded column address output latch), which are series-connected between output terminal 133c, 233c of multiplexer 133, 233 and second signal node 139b, 239b. Second latch 137, 237 can be controlled by a second clock signal (also referred to herein as a read clock signal (CLKr)). Optionally, column address predecoder 130, 230 can further include an output buffer 138, 238, which is series-connected between second latch 137, 237 and second signal node 139b, 239b.

Referring specifically to memory structure 100 of FIG. 1, row address predecoder 140 can be configured similarly to column address predecoder 130. That is, row address predecoder 140 can include a first signal node 149a (also referred to herein as a row address input node), which is connected to receive Add_R. Row address predecoder 140 can further include a second signal node 149b (also referred to herein as a predecoded row address output node) for outputting Add_Rpd. Between first signal node 149a and second signal node 149b, row address predecoder 140 can further include a multiplexer 143. Multiplexer 143 can include two input terminals: one input terminal 143a connected to first signal node 149a; and an additional input terminal 143b. Multiplexer 143 can also include an output terminal 143c.

Row address predecoder 140 can further include a first latch 141 (also referred to herein as a row address input latch), which is controlled by CLKw and a row address write logic block 142 (e.g., including a row address counter, as discussed above). First latch 141 and write logic block 142 can be series-connected between first signal node 149a and additional input terminal 143b of multiplexer 143.

Row address predecoder 140 can further include a row address predecode logic block 144 (as discussed in greater detail above) and a second latch 147 (also referred to herein as a predecoded row address output latch), which are series-connected between output terminal 143c of multiplexer 143 and second signal node 149b. Second latch 147 can be controlled by CLKr. Optionally, row address predecoder 140 can further include an output buffer 148, which is series-connected between second latch 147 and second signal node 149b.

Referring specifically to memory structure 200 of FIG. 2, row address predecoder 240 can be somewhat more complex than row address predecoder 140 in that it also incorporates a redundancy logic block 245 (as discussed in greater detail below). In this case, row address predecoder 240 can include a first signal node 249a (also referred to herein as a row address input node), which is connected to receive Add_R. Row address predecoder 240 can further include a second signal node 249b (also referred to herein as a predecoded row address output node) for outputting Add_Rpd. Between first signal node 249a and second signal node 249b, row address predecoder 240 can further include a first multiplexer 243. First multiplexer 243 can include two first input terminals: one first input terminal 243a connected to first signal node 249a; and an additional first input terminal 243b. First multiplexer 243 can further include a first output terminal 243c.

Row address predecoder 240 can further include a first latch 241 (also referred to herein as a row address input latch), which is controlled by CLKw and a row address write logic block 242 (e.g., including a row address counter, as discussed above). First latch 241 and write logic block 242 can be series-connected between first signal node 249a and additional first input terminal 243b of first multiplexer 243.

Row address predecoder 240 can further include a second multiplexer 246. Second multiplexer 246 can have two second input terminals (i.e., a second input terminal 246a and an additional second input terminal 246b) and a second output terminal 246c. Second multiplexer 246 can be controlled, for example, by predecode/redundancy select signal (SELpre/red). Row address predecoder 240 can further include a redundancy logic block 245 and a row address predecode logic block 244 (as discussed in greater detail above). Redundancy logic block 245 can be connected between first output terminal 243c of first multiplexer 243 and second input terminal 246a of second multiplexer 246. Predecode logic block 244 can be connected between first output terminal 243c of first multiplexer 243 and additional second input terminal 246b of second multiplexer 246. Thus, redundancy logic block 245 and predecode logic block 244 are connected in parallel between first multiplexer 243 and second multiplexer 246.

Row address predecoder 240 can further include a second latch 247, which is connected between second output terminal 246c of second multiplexer 246 and a second signal node 249b. Second latch 247 can be controlled by CLKr. Optionally, row address predecoder 240 can further include an output buffer 248, which is series-connected between second latch 247 and second signal node 249b.

Referring again to FIGS. 1 and 2 in combination, in column address predecoder 130, 230 and row address predecoder 140, 240, multiplexers 133, 233 and 143, 243 can be controlled by the same read/write select signal (SELrw). SELrw can be switchable to cause multiplexers 133, 233 and 143, 243 to connect only one of two input terminals thereof to the output terminal, depending upon whether a write operation or a read operation is to be performed.

For example, consider column address predecoder 130 shown in FIG. 1 or 230 shown in FIG. 2. During a write operation, SELrw can switch to a first state to cause multiplexer 133, 233 to connect additional input terminal 133b, 233b (and thereby write logic block 132, 232) to output terminal 133c, 233c (and thereby to predecode logic block 134, 234). However, during a read operation, SELrw can switch to a second state to cause multiplexer 133, 233 to connect input terminal 133a, 233a (and thereby first signal node 139a, 239a) to output terminal 133c, 233c (and thereby to predecode logic block 134, 234). Thus, in the read operation, a write logic bypass path 150, 250 (also referred to herein as a multiplexer-enabled write logic bypass path) is created to supply Add_C to predecode logic block 134, 234 without passing through first latch 131, 231 or write logic block 132, 232 to reduce the read operation setup time.

Also consider row address predecoder 140 shown in FIG. 1. During a write operation, SELrw can switch to the first state to cause multiplexer 144 to connect additional input terminal 143b (and thereby write logic block 142) to output terminal 143c (and thereby to predecode logic block 144). However, during a read operation, SELrw can switch to the second state to cause multiplexer 143 to connect input terminal 143a (and thereby first signal node 149a) to output terminal 143c (and thereby to predecode logic block 144). Thus, in the read operation, a write logic bypass path 160 is created to supply Add_R to predecode logic block 144 without passing through first latch 141 or write logic block 142 to reduce the read operation setup time.

Also consider row address predecoder 240 shown in FIG. 2. During a write operation, SELrw can switch to the first state to cause first multiplexer 243 to connect additional first input terminal 243b (and thereby write logic block 242) to first output terminal 243c (and thereby to both predecode logic block 244 and redundancy logic block 245). However, during a read operation, SELrw can switch to the second state to cause first multiplexer 243 to connect first input terminal 243a (and thereby first signal node 249a) to first output terminal 243c (and thereby to predecode logic block 244 and redundancy logic block 245). Thus, in the read operation, a write logic bypass path 260 (also referred to herein as a multiplexer-enabled write logic bypass path) is created to supply Add_R to predecode logic block 244 and redundancy logic block