14) to adjust the frequency response and wireless performance of antenna 42 over time.

Radio-frequency transmission line path 36 may be coupled to an antenna feed on antenna 42. The antenna feed may, for example, include a positive antenna feed terminal and a ground antenna feed terminal. Radio-frequency transmission line path 36 may have a positive transmission line signal path such that is coupled to the positive antenna feed terminal on antenna 42. Radio-frequency transmission line path 36 may have a ground transmission line signal path that is coupled to the ground antenna feed terminal on antenna 42. This example is illustrative and, in general, antennas 42 may be fed using any desired antenna feeding scheme. If desired, antenna 42 may have multiple antenna feeds that are coupled to one or more radio-frequency transmission line paths 36.

Radio-frequency transmission line path 36 may include transmission lines that are used to route radio-frequency antenna signals within device 10 (FIG. 1). Transmission lines in device 10 may include coaxial cables, microstrip transmission lines, stripline transmission lines, edge-coupled microstrip transmission lines, edge-coupled stripline transmission lines, transmission lines formed from combinations of transmission lines of these types, etc. Transmission lines in device 10 such as transmission lines in radio-frequency transmission line path 36 may be integrated into rigid and/or flexible printed circuit boards. In one suitable arrangement, radio-frequency transmission line paths such as radio-frequency transmission line path 36 may also include transmission line conductors integrated within multilayer laminated structures (e.g., layers of a conductive material such as copper and a dielectric material such as a resin that are laminated together without intervening adhesive). The multilayer laminated structures may, if desired, be folded or bent in multiple dimensions (e.g., two or three dimensions) and may maintain a bent or folded shape after bending (e.g., the multilayer laminated structures may be folded into a particular three-dimensional shape to route around other device components and may be rigid enough to hold its shape after folding without being held in place by stiffeners or other structures). All of the multiple layers of the laminated structures may be batch laminated together (e.g., in a single pressing process) without adhesive (e.g., as opposed to performing multiple pressing processes to laminate multiple layers together with adhesive).

Transceiver circuitry 28 may include wireless local area network transceiver circuitry that handles WLAN communications bands (e.g., Wi-Fi® (IEEE 802.11) or other WLAN communications bands) such as a 2.4 GHz WLAN band (e.g., from 2400 to 2480 MHz), a 5 GHZ WLAN band (e.g., from 5180 to 5825 MHz), a Wi-Fi® 6E band (e.g., from 5925-7125 MHz), and/or other Wi-Fi® bands (e.g., from 1875-5160 MHz), wireless personal area network transceiver circuitry that handles the 2.4 GHz Bluetooth® band or other WPAN communications bands, cellular telephone transceiver circuitry that handles cellular telephone bands (e.g., bands from about 600 MHz to about 5 GHz, 3G bands, 4G LTE bands, 5G New Radio Frequency Range 1 (FR1) bands below 10 GHz, 5G New Radio Frequency Range 2 (FR2) bands between 20 and 60 GHz, etc.), near-field communications (NFC) transceiver circuitry that handles near-field communications bands (e.g., at 13.56 MHz), satellite navigation receiver circuitry that handles satellite navigation bands (e.g., a GPS band from 1565 to 1610 MHz, a Global Navigation Satellite System (GLONASS) band, a BeiDou Navigation Satellite System (BDS) band, etc.), ultra-wideband (UWB) transceiver circuitry that handles communications using the IEEE 802.15.4 protocol and/or other ultra-wideband communications protocols, and/or any other desired radio-frequency transceiver circuitry for covering any other desired communications bands of interest.

In performing wireless transmission, processing circuitry 26 may provide digital signals to transceiver 28 over path 34. Transceiver 28 may further include circuitry for converting the baseband signals received from processing circuitry 26 into corresponding intermediate frequency or radio-frequency signals. For example, transceiver circuitry 28 may include mixer circuitry 50 for up-converting (or modulating) the baseband signals to intermediate frequencies or radio frequencies prior to transmission over antenna 42. Transceiver circuitry 28 may also include digital-to-analog converter (DAC) and/or analog-to-digital converter (ADC) circuitry for converting signals between digital and analog domains. Transceiver 28 may include a transmitter component to transmit the radio-frequency signals over antenna 42 via radio-frequency transmission line path 36 and front-end module 40. Antenna 42 may transmit the radio-frequency signals to external wireless equipment by radiating the radio-frequency signals into free space.

In performing wireless reception, antenna 42 may receive radio-frequency signals from external wireless equipment. The received radio-frequency signals may be conveyed to transceiver 28 via radio-frequency transmission line path 36 and front-end module 40. Transceiver 28 may include circuitry for converting the received radio-frequency signals into corresponding intermediate frequency or baseband signals. For example, transceiver 28 may use mixer circuitry 50 for downconverting (or demodulating) the received radio-frequency signals to baseband frequencies prior to conveying the received signals to processing circuitry 26 over path 34.

Mixer circuitry 50 can include local oscillator circuitry such as local oscillator (LO) circuitry 52. Local oscillator circuitry 52 can generate oscillator or oscillating signals that mixer circuitry 50 uses to modulate transmitting signals from baseband frequencies to radio frequencies and/or to demodulate the received signals from radio frequencies to baseband or intermediate frequencies. Local oscillator circuitry 52 can generally include phase-locked loop (PLL) circuitry configured to generate the oscillating signals being fed to inputs of mixer circuitry 50.

In practice, phase noise in this local oscillator path can have a direct impact on the signal-to-noise and distortion ratio (SNDR), which, if care is not taken, can degrade the error vector magnitude (EVM) of wireless circuitry 24. As state-of-the-art modulation schemes impose more stringent EVM requirements, the phase noise in the oscillator path can become a dominant factor in the overall link budget. The PLL circuitry can include an oscillator such as a voltage controlled oscillator (VCO). It can be challenging to design a VCO for wireless circuitry 24.

FIG. 3 is a diagram of illustrative oscillator circuitry such as oscillator circuitry 90 having a transformer based phase noise filter in accordance with some embodiments. Oscillator circuitry 90 can represent an oscillator such as a voltage controlled oscillator (VCO) that may be part of a phase-locked loop (PLL) for generating oscillating signals in LO circuitry 52. As shown in FIG. 3, oscillator circuitry 90 may include an oscillator subcircuit 60 that includes inductor (L) and capacitor (C) components and is thus sometimes referred to herein as an “LC” oscillator subcircuit or portion. Oscillator subcircuit 60 may further include n-type switches such as n-type transistors 62 and p-type switches such as p-type transistors 64. Oscillator subcircuit 60 that includes both n-type transistors and p-type transistors is sometimes referred to and defined herein as a “complementary” oscillator subcircuit.

In the example of FIG. 3, the n-type transistors 62 can be coupled to a first tail coil (inductor) such as first tail coil Lsn via connection path 63. The first tail coil Lsn can have a first terminal coupled to the n-type transistors 62 and a second terminal coupled to a ground power supply line 66 (e.g., a ground power supply terminal on which ground voltage Vss is provided). Tail coil Lsn having one side coupled to a power supply line can be referred to as a “single-ended” coil or inductor. On the other end, the p-type transistors 64 can be coupled to another tail coil (inductor) such as second tail coil Lsp via connection path 65. The second tail coil Lsp can have a first terminal coupled to the p-type transistors 64 and a second terminal coupled to a positive power supply line 68 (e.g., a positive power supply terminal on which positive power supply voltage Vdd is provided). Tail coil Lsp having one side coupled to a power supply line can also be referred to as a “single-ended” coil or inductor.

In the example of FIG. 3, one or more phase noise filter components 70 can be magnetically coupled between the first tail coil Lsn and the second tail coil Lsp. For instance, phase noise filter components 70 can include a first filter component that is magnetically coupled to tail coil Lsn (as indicated by arrow 72) and can include a second filter component that is magnetically coupled to tail coil Lsp (as indicated by arrow 74). The tail coils Lsn and Lsp, along with the phase noise filter components 70, can collectively form part of a phase noise filter that is configured to suppress close-in phase (flicker) noise for oscillator circuitry 90. Such phase noise filter that can include the tail coils Lsn and Lsp and filter components 70 can thus sometimes be referred to as a phase noise “tail” filter.

FIG. 4 is a circuit diagram showing an illustrative implementation of complementary oscillator circuitry 90 of the type described in connection with FIG. 3. As shown in FIG. 4, oscillator circuitry 90 can include n-type transistors N1 and N2, p-type transistors P1 and P2, capacitors 78a and 78b, an output capacitor such as tunable load capacitor Cd, an output inductor such as load inductor Ld, and one or more associated coils (inductors) such as tail coils Lsn and Lsp.

Transistors N1 and N2 may be n-type (n-channel) transistors such as n-type metal-oxide-semiconductor (NMOS) devices and can represent the n-type switches 62 shown in FIG. 3. Transistor N1 may have a source terminal coupled to a first tail node such as tail node Tn, a drain terminal coupled to a first output terminal OUT1 of circuitry 90, and a gate terminal that is cross-coupled to a second output terminal OUT2 of circuitry 90. Transistor N2 may have a source terminal coupled to the first tail node Tn, a drain terminal coupled to the second output terminal OUT2, and a gate terminal that is cross-coupled to the first output terminal OUT1. Output terminals OUT1 and OUT2 may serve collectively as a differential output port of oscillator circuitry 90. Oscillating (local oscillator or “LO”) signals can be generated on the differential output port. Transistors N1 and N2 arranged in this way are sometimes referred to as “cross-coupled” differential n-type transistors.

The terms “source” and “drain” terminals used to refer to current-conveying terminals of a transistor may be used interchangeably and are sometimes referred to as “source-drain” terminals. Thus, the source terminal of transistor N1 can sometimes be referred to as a first source-drain terminal, and the drain terminal of transistor N1 can be referred to as a second source-drain terminal (or vice versa). The term “activate” with respect to a switch (or transistor) may refer to or be defined herein as an action that places the switch in an “on” or low-impedance state such that the two terminals of the switch are electrically connected to conduct current. The term “deactivate” with respect to a switch (or transistor) may refer to or be defined herein as an action that places the switch in an “off” or high-impedance state such that the two terminals of the switch/transistor are electrically disconnected with minimal leakage current.

At the other end, transistors P1 and P2 may be p-type (p-channel) transistors such as p-type metal-oxide-semiconductor (PMOS) devices and can represent the p-type switches 64 shown in FIG. 3. Transistor P1 may have a source terminal coupled to a second tail node such as tail node Tp, a drain terminal coupled to the first output terminal OUT1 of circuitry 90, and a gate terminal that is cross-coupled to the second output terminal OUT2 of circuitry 90. Transistor P2 may have a source terminal coupled to the second tail node Tp, a drain terminal coupled to the second output terminal OUT2, and a gate terminal that is cross-coupled to the first output terminal OUT1. Transistors P1 and P2 arranged in this way are sometimes referred to as “cross-coupled” differential p-type transistors.

A first capacitor 78a may have a first terminal coupled to output terminal OUT1 and a second terminal coupled to the ground line. A second capacitor 78b may have a first terminal coupled to output terminal OUT2 and a second terminal coupled to ground. Load (output) inductor Ld may have a first terminal coupled to output terminal OUT1 and a second terminal coupled to output terminal OUT2 (e.g., load inductor Ld may be coupled across the differential output port of oscillator circuitry 90). Tunable load (output) capacitor Cd may have a first terminal coupled to output terminal OUT1 and a second terminal coupled to output terminal OUT2. Load inductor Ld may thus be coupled in parallel with load capacitor Cd. Capacitor Cd may be implemented as a programmable bank of capacitors or other types of adjustable capacitive structure. The first tail coil Lsn may have a first terminal coupled to tail node Tn and a second terminal coupled to ground power supply line 66. The second tail coil Lsp may have a first terminal coupled to tail node Tp and a second terminal coupled to positive power supply line 68.

In the example of FIG. 4, the phase noise filter components can include a first filter coil such as first filter coil Ln, a second filter coil such as second filter coil Lp, a differential capacitor such as tunable differential capacitor Cdiff, a first tunable single-ended capacitor Csen, and a second tunable single-ended capacitor Csep. The first filter coil Ln may be magnetically coupled to first tail coil Lsn. Coils Lsn and Ln may collectively form a first 1:1 (one-to-one) impedance transformer. First filter coil Ln can have a first terminal coupled to differential capacitor Cdiff and a second terminal coupled to ground line 66. A “single-ended” capacitor can refer to and be defined herein as a capacitor having one of its terminals coupled to a static voltage line such as a power supply line. The second filter coil Lp may be magnetically coupled to second tail coil Lsp. Coils Lsp and Lp may collectively form a second 1:1 (one-to-one) impedance transformer. Second filter coil Lp can have a first terminal coupled to differential capacitor Cdiff and a second terminal coupled to ground line 66.

A 1:1 impedance transformer can, as an example, be implemented using a primary coil (winding) and a secondary coil (winding) with overlapping footprints and an identical number of turns and windings to ensure optimum coupling. Not all transformers are 1:1 impedance transformers; transformers having coils that are not substantially overlapping can have different impedance coupling ratios. In particular, the use of 1:1 impedance transformers can be technically advantageous to reduce the sensitivity of the phase noise tail filter to any difficult-to-model power supply routing inductances for minimizing phase noise.

Tunable differential capacitor Cdiff can, for example, be implemented as a bank of switchable capacitors (e.g., an array of capacitors each of which is selectively activated by a respective switch), a variable capacitor sometimes referred to as a varactor, a varicap diode, a metal-oxide-semiconductor capacitor (MOSCAP), and/or other components configured to provide a variable capacitance. Differential capacitor Cdiff can thus sometimes be referred to herein as an adjustable capacitor or a programmable capacitor. Tunable differential capacitor Cdiff can be adjusted by a digital control signal or an analog control signal to trim for minimum phase noise.

The phase noise tail filter is responsible for suppressing phase noise from both the n-type transistors N1 and N2 (i.e., the “n-side” components) and also the p-type transistors P1 and P2 (i.e., the “p-side” components). In practice, however, the condition/impedance for optimal flicker suppression by the phase noise tail filter may be different for the n-side components and the p-side components due to potentially differing characteristics and large signal behavior of the n-type and p-type transistors. For example, the n-type and p-type transistors can have different mobility and conductance values, different threshold voltages, differential parasitics due to process variations, different device parameters that can change as a function of temperature or other operating conditions, and/or other mismatched or unbalanced characteristics.

In accordance with some embodiments, the single-ended capacitors Csen and Csep can be configured as balance restoration components to individually optimize the n-side and p-side impedances for simultaneously minimizing flicker noise contribution from both ends. Capacitor Csen may have a first terminal coupled to a node disposed between coil Ln and capacitor Cdiff and a second terminal coupled to ground 66. In other words, capacitor Csen may be coupled across opposing terminals of coil Ln (e.g., capacitor Csen may be coupled “in parallel” with coil Ln). Capacitor Csep may have a first terminal coupled to a node disposed between coil Lp and capacitor Cdiff and a second terminal coupled to ground 66. In other words, capacitor Csep may be coupled across opposing terminals of coil Lp (e.g., capacitor Csep may be coupled “in parallel” with coil Lp).

Capacitors Csen and Csep can each be implemented as a bank of switchable capacitors (e.g., an array of capacitors each of which is selectively activated by a respective switch), a variable capacitor sometimes referred to as a varactor, a varicap diode, a metal-oxide-semiconductor capacitor (MOSCAP), and/or other components configured to provide a variable capacitance. Capacitors Csen and Csep can thus be referred to herein as tunable capacitors or programmable capacitors. Tunable single-ended capacitors Csen and Csep can be adjusted by digital control signals (e.g., digital codes) or analog control signals (e.g., analog control voltages).

FIG. 5 is a plot of phase noise as a function of differential tail capacitance (i.e., the capacitance of Cdiff) when the n-side and p-side components are unbalanced. Curve 100 represents the phase noise profile for the n-side components (e.g., the n-type transistors), whereas curve 102 represents the phase noise profile for the p-side components (e.g., the p-type transistors). As shown in FIG. 5, curve 100 can exhibit a minimum phase noise when the differential capacitor Cdiff has a capacitance value equal to Cn_opt, whereas curve 102 can exhibit a minimum phase noise when the differential capacitor Cdiff has a capacitance value equal to Cp_opt. Since the optimal Cdiff values for the n-side and p-side are different, the total flicker suppression is limited. Curve 104 represents the total phase noise profile, which sums the contribution from curve 100 and curve 102. Curve 104 can exhibit a minimum phase noise PN1 when differential capacitor Cdiff has a capacitance value equal to Copt, which sits somewhere between Cn_opt and Cp_opt. If care is not taken, Cn_opt and Cp_opt can be substantially offset from each other (e.g., if capacitors Csen and Csep are absent or not optimally tuned). Such offset or misalignment of Cn_opt and Cp_opt can be due to the mismatched characteristics between the n-side and p-side components, which can limit the total flicker suppression capabilities of the phase noise tail filter.

FIG. 6 is a plot of phase noise as a function of differential tail capacitance when the n-side and p-side components are optimized using balance restoring capacitors Csen and Csep to reduce phase noise in accordance with some embodiments. Curve 110 represents the phase noise profile for the n-side components (e.g., the n-type transistors), whereas curve 112 represents the phase noise profile for the p-side components (e.g., the p-type transistors). Curve 114 represents the total phase noise profile, which sums the contribution from curve 110 and curve 112. As shown in FIG. 6, curves 110, 112, and 114 can all exhibit a minimum phase noise when the differential capacitor Cdiff has a capacitance value approximately equal to Copt*. In particular, curve 114 can exhibit a minimum phase noise PN2 that is even less than phase noise PN1 associated with curve 104 of FIG. 5. Here, the alignment of the minimum phase noise can be achieved by tuning the single-ended capacitors Csen and Csep to restore the balance between the n-side and p-side components. Capacitors Csen and Csep operated in this way are therefore sometimes referred to as single-ended tunable/programmable balance restoration (restoring) capacitors. Oscillator circuitry 90 configured in this way is technically advantageous and beneficial by reducing the overall phase noise. The phase noise tail filter configured in this way is thus sometimes referred to as a balance restoring phase noise filter.

Capacitors Csen and Csep should be tuned in a particular way. For instance, when the capacitance of capacitor Csen is increased by a given amount, the capacitance of capacitor Csep should be decreased by the same given amount. Conversely, when the capacitance of capacitor Csen is decreased by a given amount, the capacitance of capacitor Csep should be increased by the same given amount. In other words, the total capacitance of Csen and Csep should be maintained when separately tuning the two balance restoring capacitors.