210a-d). These receptacles may be dedicated wide front slots that are configured for high powered optics and/or AI processor modules, reducing power and materials. Moreover, since receptacles are close (partially surround) the NPU 230, shorter electrical traces and the application of linear optic pluggable modules may be used that are much lower power then traditional pluggable optics at 400G and higher electrical signaling rates. In addition, for the configuration illustrated in FIG. 2, a printed circuit board trace loss of 1 dB/inch or less may be achieved by using ultra-low loss printed circuit board material. Further, the dual-purpose receptacles 210a-d allow for a dense coherent optical solutions and AI processing without using a spine/leaf architecture of related art.

With continued reference to FIGS. 1-2, FIG. 3 is a diagram illustrating a system 300 having a separate auxiliary power and control plane communications for AI modules in dual purpose receptacles, according to an example embodiment. The system 300 includes a housing assembly (a housing 310) having a chassis stack 320 of a plurality of chassis and an auxiliary power and control base plane 330 installed on a printed circuit board 332, for example.

In one example embodiment, the system 300 may be a core router that has AI/optic modules and is powered by fault managed power (FMP). The core router has a separate PCIe link to the GPU/DPU modules. In one or more example embodiments, a core router design having FMP power and 25GE SPE interconnection may further be simplified, described below with reference to FIG. 4.

In the housing 310, the chassis stack 320 includes a plurality of chassis (rack units). Each chassis may slide out about 40-45% of the way forward. For example, a chassis may be configured on respective sliding rails in the housing 310 and may slide forward out of the housing 310 to allow a user to access the components therein. As another example, the top may be lifted up and modules (e.g., fan tray, PSUs) may be replaced. The modular arrangement of the chassis stack 320 allows a user to easily remove a 1RU component within 90 second or less airtime.

Each chassis in the chassis stack 320 includes a faceplate around a portion of a respective chassis and an integrated circuit. This faceplate has multiple face portions that expose a plurality of receptacles or cages. The plurality of receptacles are configured to receive pluggable modules and include dual purpose receptacles 322 and transceiver receptacles 324. The integrated circuit may include an AI CPU 326.

The dual purpose receptacles 322 are configured to interchangeably receive optical transceiver modules and/or artificial intelligence processor modules and to enable connectivity with the at least one integrated circuit. A dual purpose receptacle detects the optical transceiver module or the artificial intelligence processor module when the pluggable module is plugged into the dual purpose receptacle. As such, some of the dual purpose receptacles 322 may have optical transceiver modules plugged in while others may have AI processor modules plugged in. In the example of FIG. 3, AI processor modules 340a-c are plugged into respective ones of the dual purpose receptacles 322. By way of an example, the AI processor modules 340a-c may include one wide AI processor module (e.g., 104 mm connector to provide 64 by 100GE) and two standard AI processor modules (e.g., 52 mm connector to provide 32 by 100GE).

The dual purpose receptacles 322 are positioned at a front face of the faceplate. By grouping the dual purpose receptacles 322 at the front face of the faceplate, a direct connection to the integrated circuit may be provided e.g., to a respective AI CPU 326 (as well as power and cooling). A peripheral component interconnect express (PCIe interface 328) may connect a respective AI processor module, plugged into one of the dual purpose receptacles 322, to the respective AI CPU 326. Additionally, the AI CPU 326 may control the plugged in AI processor module using the PCIe interface 328.

The transceiver receptacles 324 are configured to only receive the optical transceiver modules and are not configured to receive the AI processor modules and cannot detect a different type of module e.g., the AI processor module. The transceiver receptacles 324 are positioned on two sides of the faceplate and are configured to connect the optical transceiver modules plugged in therein to an integrated circuit, e.g., an NPU. Additionally, the transceiver receptacles 324 may accommodate high power optical transceiver modules that send processed data to an external device via a cloud, for example.

In one example embodiment, the transceiver receptacles 324 may be split into groups. In the example of FIG. 3, a first group of the transceiver receptacles 324 receive optical transceiver modules that serve as an uplink 350 e.g., for a full mesh to a two core router and a second group of the transceiver receptacles 324 receive optical transceiver modules that serve as a switch link 352 i.e., an on-premise switch access from Internet of Things (IoT) devices such as sensors or cameras that use a large language model (LLM) (AI processing) provided by the AI processor modules 340a-c, for example.

The auxiliary power and control base plane 330 on the printed circuit board 332 is configured to provide an auxiliary power and control plane communication for the modules plugged into the dual purpose receptacles 322. That is, the AI processor modules 340a-c (and/or optical transceiver modules) may need additional power and cooling for performing resource heavy AI operations (and/or providing a dense coherent optical solution). To provide additional resources that may be used by these modules, the auxiliary power and control base plane 330 includes a plurality of high voltage direct current (HVDC) power supply such as FMP power sources 334a-c and a cooling system 336 that may include one or more fans.

In the example of FIG. 3, each of the FMP power sources 334a-c is configured to respectively supply FMP power to a respective one of the AI processor modules 340a-c, shown at 338. This one to one configuration is just an example. In one example embodiment, several FMP power sources may be integrated to power a plugged in module or FMP power provided by one FMP power source may be shared by several plugged in modules. The number, types of components, connections, etc. may vary based on a particular deployment and use case scenario.

The cooling system 336 may include any number of fans to provide air cooling to the modules in the dual purpose receptacles 322 but this is just an example. The cooling system 336 may be a liquid cooling system e.g., a liquid cooling air assist system that is configured to cool the air provided to a cooling cover 360. That is, in the example of FIG. 3, the cooling system 336 is configured to circulate cool air in the cooling cover 360 positioned over the front of the faceplate in which dual purpose receptacles 322 are installed. The cooling cover 360 isolates the front of the faceplate i.e., forms a separate area (environment) for the modules plugged into the dual purpose receptacles 340a-c. The cooling system 336 may be configured to provide air to the cooling cover 360 to cool at least two artificial intelligence processor modules (the AI processor modules 340a-c plugged in therein) such that the air exits the cooling cover from a rear end of the housing, detailed below.

With continued reference to FIGS. 1-3, FIG. 4 is a diagram illustrating a system 400 with a direct attach switching fabric and a plurality of stackable auxiliary power and control base planes, according to an example embodiment. The system 400 includes a plurality of stackable auxiliary power and control base planes 410a-d (each being similar to the auxiliary power and control base plane 330 of FIG. 3), a plurality of chassis 420a-f (e.g., the chassis stack 320 of FIG. 3) having a direct attach switching fabric 430. The system 400 has a front 402 (with a faceplate), sides 404, and a rear end 406. The system 400 incorporates a new router method using the direct attach switching fabric 430. This dense configuration (the arrangement in the system 400) eliminates having complex spine/leaf configurations as this is relatively incorporated into a single configuration i.e., by having the direct attach switching fabric 430.

Each of the plurality of stackable auxiliary power and control base planes 410a-d may include a power shelf 412 that provides HVDC (e.g., FMP power) to the modules plugged into dual purpose receptacles and a fan tray 414 that provides cool air into the cooling cover 360. The fan tray 414 may include one or more fans.

The plurality of chassis 420a-f include dual purpose receptacles into which AI processor modules and/or optical transceiver modules may be plugged in. Specifically, the system 400 may include multiple sections 422 at the faceplate at the front 402. Each of the multiple sections 422 has dual purpose receptacles. This is provided by way of an example only, there may be any number of sections that include the dual purpose receptacles e.g., the number of sections may scale from one to eight. In the example of FIG. 4, six sections are shown. The rear end 406 of the plurality of chassis 420a-f includes the direct attach switching fabric 430 (in addition to other components such as at least one integrated circuit, power supply units, etc.). By way of an example, the plurality of chassis 420a-f include rear fan trays 424 that cool the integrated circuit and other components in a respective chassis.

The direct attach switching fabric 430 includes a plurality of fabric cards 432 configured to provide a mesh of connections between the plurality of chassis 420a-f. In the example of FIG. 4, the plurality of fabric cards 432 include eight fabric cards that are orthogonally installed into the plurality of chassis 420a-f at the rear end 406 thereof and that provide a mesh of connections. This is just one example, the plurality of fabric cards 432 may be four, six, eight, or another arrangement for the mesh of connections depending on a particular deployment and use case scenario. The direct attach switching fabric 430 further includes a connector 434 e.g., a rear fiber that provides an exit or an external connection to the plurality of fabric cards 432 i.e., connections to external devices and/or to a cloud. The direct attach switching fabric 430 allows for a single configuration as opposed to the spine/leaf architecture. For example, the dual FMP/25GE SPE interconnection (i.e., the direct attach switching fabric 430) may simplify the design or configuration of the system 400.

With continued reference to FIGS. 1-4, FIG. 5 is a diagram illustrating a cooling system 500 in an auxiliary power and control base plane 510 configured to cool an area in which dual purpose receptacles of one or more chassis 520 are installed, according to an example embodiment. The cooling system 500 includes a liquid cooling assist arrangement 512 and a plurality of auxiliary fans 514 in the auxiliary power and control base plane 510, a cooling cover 522 such as the cooling cover 360 of FIG. 3 and a plurality of fans 524 in the one or more chassis 520.

In addition to a plurality of FMP modules 516 in the auxiliary power and control base plane 510, the plurality of auxiliary fans 514 provide air to the cooling cover 522. In other words, the liquid cooling assist arrangement 512 and the plurality of auxiliary fans 514 are components of the cooling system 500 dedicated to cooling AI processor modules and/or optical transceiver modules installed in dual purpose receptacles a the faceplate of the one or more chassis 520.

In one or more example embodiments, the liquid cooling assist arrangement 512 is a an arrangement of pipes or tube(s) 552 that circulate cooling fluid for cooling air to be provided to the cooling cover 522. This is just one example and other arrangements which use cooling liquid for auxiliary cooling of air are within the scope of this disclosure.

In FIG. 5, cooling liquid enters at 550, flows through the tube(s) 552 in the auxiliary power and control base plane 510 and exits the tube(s) 552, at 554. The tube(s) 552 may be positioned near or align with the plurality of auxiliary fans 514 to cool the air being provided from the outside to the plurality of auxiliary fans 514. In yet another example embodiment, the tube(s) 552 may be positioned such that air from the plurality of auxiliary fans 514 are cooled prior to entering the cooling cover 522.

Specifically, at 560, outside air enters the auxiliary power and control base plane 510 through one or more holes or openings e.g., front openings. The air is cooled by the liquid cooling assist arrangement 512 i.e., passes between the tube(s) 552 and approaches the plurality of auxiliary fans 514, at 562. The plurality of auxiliary fans 514 blow the air into the cooling cover 522. That is, the cooled air exits the auxiliary power and control base plane 510 and enters the cooling cover 522 of the one or more chassis 520, at 564.

The cooling cover 522 may be a housing or a cover over the AI/optics modules plugged into the dual purpose receptacles. The cooling cover 522 is configured to form an area 572 around the front of the faceplate with one or more AI/optic modules inserted therein. This arrangement may provide superior cooling to the AI processor modules such as GPUs and DPUs and/or high power optical transceiver modules (AI/optic modules) that are plugged into the dual purpose receptacles. This arrangement, however, does not provide direct liquid cooling to the AI/optic modules and instead super cools the area 572 in which the AI/optic modules are installed, shown at 566. The air exits the cooling cover 522 at sides thereof and/or at a rear end of the one or more chassis 520, at 568. In one example embodiment, the air may exit at a top of the one or more chassis 520. In one or more example embodiments, cold plates 570 may be added to the area 572 formed by the cooling cover 522. As such, air circulating in the cooling cover 522 is further cooled by the cold plates 570.

An additional or main airflow to cool other components of the one or more chassis 520 such as the ones described in FIG. 2 (e.g., AI CPU, CPU, etc.) is also provided. The main airflow is configured to provide cooling to the components in the one or more chassis 520 including the integrated circuit or ASIC therein. For example, the air enters at the faceplate i.e., at a front of the one or more chassis 520, shown at 580, circulates through the one or more chassis 520 and exits at the rear end of the one or more chassis 520, shown at 582. The main air flow is facilitated by the plurality of fans 524. Moreover, the offset configuration of the receptacles allows for greater air intake for enhanced cooling.

With continued reference to FIGS. 1-5, FIG. 6 is a diagram illustrating an on-premise AI application system 600 that processes image data from one or more camera and outputs results to a dashboard, according to an example embodiment. The on-premise AI application system 600 includes IoT devices 610, a switch 620, a network device 630 such as the network device 100 of FIG. 1, a cloud 640, and a dashboard 650. The cloud 640 and the dashboard 650 are just examples of outputting data processed by the network device 630 and other external systems/networks are within the scope of this disclosure.

The IoT devices 610 may include a plurality of data gathering devices such as cameras that gather image data or sensors that collect sensed data that is to be processed by an AI application or an AI tool. At 612, the IoT devices 610 sends gathered data to the network device 630, via the switch 620.

The network device 630 executes AI application using one or more AI processor modules 632 such as the AI processor modules 340a-c of FIG. 3. That is, the network device 630 receives input data via optical transceiver modules e.g., inserted into a first group of transceiver receptacles 634a. At 636, the network device 630 performs machine learning (AI processing) of the input/received data using the AI processor modules 632 e.g., GPUs and/or DPUs. For example, the network device 630 may execute a large language model (LLM) to analyze image data from a plurality of cameras.

At 638, the network device 630 transmits the processed data (results) via optical transceiver modules e.g., inserted into a second group of transceiver receptacles 634b, via a cloud 640 (i.e., network), to the dashboard 650. At 652, the dashboard 650 outputs results to a user displayed on a user interface. This, however, is just an example. The processed data may be provided via a network to a backend application such as a network management service that may further analyze and/or process the data to determine whether to output an alert, etc. The example of FIG. 6 illustrates simplicity of providing an on-premise AI application for camera or other processing without using multiple rack locations of routers and separate AI systems.

FIG. 7 is a diagram illustrating a network device 700 in which artificial intelligence processor modules and/or optical transceiver modules inserted into dual purpose receptacles are provided with an integrated power, communication and cooling, according to an example embodiment. The network device 700 includes an auxiliary power and control base plane 710, a chassis stack 720 into which AI processor modules and/or optical modules (AI/optical modules 730) are inserted. Additionally, each of the AI/optical modules 730 is connected to the auxiliary power and control base plane 710 via a cable 740.

The AI/optical modules 730 are connected to FMP power, communication, and cooling via the cable 740. That is, a single cable (the cable 740) is configured to provide high voltage direct current (HVDC) power (e.g., FMP power) and 25GE or 40GE SPE communication. Moreover, direct cooling may be provided via the cable 740. For example, the FMP application is with SPE to deliver 1000 watts or more to an AI processor module or optical transceiver module or other high power application needing large amounts of power and cooling that typically may not be delivered from the router itself (i.e., the chassis stack 720). This configuration allows for colder air at the AI/optical modules 730 to the sides of this router configuration, allowing for higher power QSFP-DD or optic modules beyond 100 watts.

The techniques presented herein provide a network device such as multi one rack unit (RU) stackable router design with dedicated wide front module cages (dual purpose receptacles) for advanced high voltage optics and GPU/DPU modules. In addition, the techniques described herein allow for forced air cooling and/or auxiliary liquid cooling specific to these pluggable models (without direct cooling) and support power delivery significantly beyond 2000 watts as may be used by AI applications. The arrangement(s) provided herein allow for focused deployment of power, cooling, and control plane communications e.g., via a single cable. The techniques presented herein reduce power consumption and the number of communication components.

Reference is now made to FIG. 8. FIG. 8 is a flow diagram illustrating a method 800 of creating a chassis with dual purpose receptacles for inserting an optical transceiver module or an artificial intelligence module, according to an example embodiment.

At 802, at least one integrated circuit is positioned into a chassis. At 804, a faceplate is positioned around a portion of the chassis. The faceplate has multiple face portions that expose a plurality of receptacles. At least one receptacle of the plurality of receptacles is a dual purpose receptacle configured to interchangeably receive an optical transceiver module or an artificial intelligence processor module and to enable connectivity with the at least one integrated circuit.

At 806, the optical transceiver module or the artificial intelligence processor module is inserted into the dual purpose receptacle.

In one form, the operation 804 of positioning the faceplate around the portion of the chassis may include positioning the plurality of receptacles around two or more sides of the at least one integrated circuit and connecting high voltage power to the optical transceiver module or the artificial intelligence processor module inserted into the dual purpose receptacle.

In another form, the operation 804 of positioning the faceplate around the portion of the chassis may include positioning the plurality of receptacles around two or more sides of the at least one integrated circuit and connecting fault managed power (FMP) to the optical transceiver module or the artificial intelligence processor module inserted into the dual purpose receptacles.

In yet another form, the operation 804 of positioning the faceplate around the portion of the chassis may include positioning a first set of dual purpose receptacles at a front face of the faceplate and detecting the optical transceiver module or the artificial intelligence processor module when plugged in therein.

In one instance, the operation 804 of positioning the faceplate around the portion of the chassis may further include positioning a second set of receptacles on two sides of the faceplate and receiving only the optical transceiver module in each of the second set of receptacles.

According to one or more example embodiments, the method 800 may further include providing fault managed power (FMP) using an auxiliary power and control base plane to a plurality of dual purpose receptacles of the plurality of receptacles. The method 800 may further include inserting at least two artificial intelligence processor modules into the plurality of dual purpose receptacles.

FIG. 9 is a hardware block diagram of a computing device 900 that may perform functions associated with any combination of operations in connection with the techniques depicted and described in FIGS. 1-8, according to various example embodiments. The computing device 900 may be a network device that hosts various components to perform at least some of the computing functions. The computing device 900 may be a server that executes an application that provides a dashboard or a user device that gathers data for AI processing. It should be appreciated that FIG. 9 provides only an illustration of one embodiment and does not imply any limitations with regard to the environments in which different embodiments may be implemented. Many modifications to the depicted environment may be made.

In at least one embodiment, computing device 900 may include one or more processor(s) 902, one or more memory element(s) 904, storage 906, a bus 908, one or more network processor unit(s) 910 interconnected with one or more network input/output (I/O) interface(s) 912, one or more I/O interface(s) 914, and control logic 920. In various embodiments, instructions associated with logic for computing device 900 can overlap in any manner and are not limited to the specific allocation of instructions and/or operations described herein.

In at least one embodiment, processor(s) 902 is/are at least one hardware processor configured to execute various tasks, operations and/or functions for computing device 900 as described herein according to software and/or instructions configured for computing device 900. Processor(s) 902 (e.g., a hardware processor) can execute any type of instructions associated with data to achieve the operations detailed herein. In one example, processor(s) 902 can transform an element or an article (e.g., data, information) from one state or thing to another state or thing. Any of potential processing elements, microprocessors, digital signal processor, baseband signal processor, modem, PHY, controllers, systems, managers, logic, and/or machines described herein can be construed as being encompassed within the broad term ‘processor’.

In at least one embodiment, one or more memory element(s) 904 and/or storage 906 is/are configured to store data, information, software, and/or instructions associated with computing device 900, and/or logic configured for memory element(s) 904 and/or storage 906. For example, any logic described herein (e.g., control logic 920) can, in various embodiments, be stored for computing device 900 using any combination of memory element(s) 904 and/or storage 906. Note that in some embodiments, storage 906 can be consolidated with one or more memory elements 904 (or vice versa), or can overlap/exist in any other suitable manner.

In at least one embodiment, bus 908 can be configured as an interface that enables one or more elements of computing device 900 to communicate in order to exchange information and/or data. Bus 908 can be implemented with any architecture designed for passing control, data and/or information between processors, memory elements/storage, peripheral devices, and/or any other hardware and/or software components that may be configured for computing device 900. In at least one embodiment, bus 908 may be implemented as a fast kernel-hosted interconnect, potentially using shared memory between processes (e.g., logic), which can enable efficient communication paths between the processes.

In various embodiments, network processor unit(s) 910 may enable communication between computing device 900 and other systems, entities, etc., via network I/O interface(s) 912 to facilitate operations discussed for various embodiments described herein. In various embodiments, network processor unit(s) 910 can be configured as a combination of hardware and/or software, such as one or more Ethernet driver(s) and/or controller(s) or interface cards, Fibre Channel (e.g., optical) driver(s) and/or controller(s), and/or other similar network interface driver(s) and/or controller(s) now known or hereafter developed to enable communications between computing device 900 and other systems, entities, etc. to facilitate operations for various embodiments described herein. In various embodiments, network I/O interface(s) 912 can be configured as one or more Ethernet port(s), Fibre Channel ports, and/or any other I/O port(s) now known or hereafter developed. Thus, the network processor unit(s) 910 and/or network I/O interface(s) 912 may include suitable interfaces for receiving, transmitting, and/or otherwise communicating data and/or information in a network environment.

I/O interface(s) 914 allow for input and output of data and/or information with other entities that may be connected to computing device 900. For example, I/O interface(s) 914 may provide a connection to external devices such as a keyboard, keypad, a touch screen, and/or any other suitable input device now known or hereafter developed. In some instances, external devices can also include portable computer readable (non-transitory) storage media such as database systems, thumb drives, portable optical or magnetic disks, and memory cards. In still some instances, external devices can be a mechanism to display data to a user, such as, for example, a computer monitor 916, a display screen, or the like.

In various embodiments, control logic 920 can include instructions that, when executed, cause processor(s) 902 to perform operations, which can include, but not be limited to, providing overall control operations of computing device; interacting with other entities, systems, etc. described herein; maintaining and/or interacting with stored data, information, parameters, etc. (e.g., memory element(s), storage, data structures, databases, tables, etc.); combinations thereof; and/or the like to facilitate various operations for embodiments described herein.

In another example embodiment, an apparatus or a device is provided. The device includes a chassis that contains at least one integrated circuit. The device further includes a faceplate around a portion of the chassis. The faceplate has multiple face portions that expose a plurality of receptacles. At least one receptacle of the plurality of receptacles is a dual purpose receptacle configured to interchangeably receive an optical transceiver module or an artificial intelligence processor module and to enable connectivity with the at least one integrated circuit.

In one form, the plurality of receptacles may be positioned around two or more sides of the at least one integrated circuit and may be configured to connect high voltage power to the optical transceiver module or the artificial intelligence processor module, which are pluggable modules.

In another form, the plurality of receptacles may be positioned around two or more sides of the at least one integrated circuit and may be configured to connect fault managed power (FMP) to the optical transceiver module or the artificial intelligence processor module, which are pluggable modules.

In yet another form, the plurality of receptacles may include a first set of dual purpose receptacles that are positioned at a front face of the faceplate and are configured to detect the optical transceiver module or the artificial intelligence processor module when plugged in therein.

In one instance, the plurality of receptacles may include a second set of receptacles that are positioned on two sides of the faceplate and are configured to only receive the optical transceiver module.

According to one or more example embodiments, the multiple face portions may include front face portions and side face portions. Each front face portion may be offset from each adjacent front face portion and may expose the dual purpose receptacle. A side face portion may connect a front face portion to an adjacent front face portion.

According to one or more example embodiments, the plurality of receptacles may include a plurality of dual purpose receptacles positioned at a front of the faceplate and may be configured to receive at least two artificial intelligence processor modules. The device may further include a housing that includes the chassis and a printed circuit board that includes an auxiliary power and control base plane that provides fault managed power (FMP) to the plurality of dual purpose receptacles for the at least two artificial intelligence processor modules.

In one form, the at least one integrated circuit may include an artificial intelligence central processing unit (AI CPU). The housing may further include a communication interface that is integrated with fault managed power and is configured to connect the at least two artificial intelligence processor modules to the AI CPU.

In another form, at least one integrated circuit may include an artificial intelligence central processing unit (AI CPU). The housing may further include a communication interface configured to connect the at least two artificial intelligence processor modules to the AI CPU.

In one instance, the housing may further include a cooling cover positioned over the front of the faceplate in which dual purpose receptacles are installed. The auxiliary power and control base plane may further include a cooling system configured to provides air to the cooling cover to cool the at least two artificial intelligence processor modules plugged in therein such that the air exits the cooling cover from a rear end of the housing.

In another instance, the auxiliary power and control base plane may further include a liquid cooling air assist system that is configured to cool the air provided to the cooling cover.

In yet another instance, the device may further include at least one power supply, positioned in the housing, that powers the at least one integrated circuit and is configured to power a plurality of optical transceiver modules plugged into at least two of the plurality of receptacles other than the dual purpose receptacle.

According to one or more example embodiments, the device may further include a housing that includes the chassis and at least one additional chassis that contains at least one additional integrated circuit and at least one additional faceplate with another plurality of receptacles including at least one additional dual purpose receptacle.

In one form, the device may further include a plurality of fabric cards configured to provide a mesh of connections between the chassis and the at least one additional chassis.

In another form, the device may further include a plurality of stackable auxiliary power and control base planes that provide fault managed power (FMP) to a plurality of dual purpose receptacles for at least two artificial intelligence processor modules.

In yet another example embodiment, a system is provided. The system includes a housing that contains a chassis stack of a plurality of chassis. Each chassis of the plurality of chassis includes at least one integrated circuit and a faceplate around a portion of a respective chassis. The faceplate has multiple face portions that expose a plurality of receptacles. The plurality of receptacles include at least one dual purpose receptacle configured to interchangeably receive an optical transceiver module or an artificial intelligence processor module and to enable connectivity with the at least one integrated circuit and a transceiver receptacle configured to only receive the optical transceiver module.

In one form, the system may further include a switch configured to provide data from at least one external device to a plurality of artificial intelligence processor modules plugged into respective ones of dual purpose receptacles in the chassis stack via a plurality of optical transceiver modules plugged into respective receptacles of the dual purpose receptacles and transceiver receptacles in the chassis stack.

In one instance, the system may further include the plurality of optical transceiver modules provide processed data from the plurality of artificial intelligence processor modules to a cloud.

In another instance, the system may further include a cooling cover positioned over a front of a plurality of faceplates of the chassis stack, in which dual purpose receptacles are installed.

According to one or more example embodiments, the system may further include at least one auxiliary power and control base plane, each including a cooling system configured to provides air to the cooling cover to cool at least two artificial intelligence modules plugged in therein such that the air exits the cooling cover from a rear end of the housing.

In yet another example embodiment, an arrangement may be provided that includes the devices and operations explained above with reference to FIGS. 1-9.

The programs described herein (e.g., control logic 920) may be identified based upon the application(s) for which they are implemented in a specific embodiment. However, it should be appreciated that any particular program nomenclature herein is used merely for convenience, and thus the embodiments herein should not be limited to use(s) solely described in any specific application(s) identified and/or implied by such nomenclature.

In various embodiments, entities as described herein may store data/information in any suitable volatile and/or non-volatile memory item (e.g., magnetic hard disk drive, solid state hard drive, semiconductor storage device, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM), application specific integrated circuit (ASIC), etc.), software, logic (fixed logic, hardware logic, programmable logic, analog logic, digital logic), hardware, and/or in any other suitable component, device, element, and/or object as may be appropriate. Any of the memory items discussed herein should be construed as being encompassed within the broad term ‘memory element’. Data/information being tracked and/or sent to one or more entities as discussed herein could be provided in any database, table, register, list, cache, storage, and/or storage structure: all of which can be referenced at any suitable timeframe. Any such storage options may also be included within the broad term ‘memory element’ as used herein.