As illustrated in FIG. 2, the trigger input 25 is connected to a first input of the first gate 51 and the interrupt input 27 is connected to a second input of the gate 51. An output of the gate 51 is connected to an input of the second gate 52. The other input of the second gate 52 is connected to the gate of the switching transistor 54. The output of the second gate 52 is connected to an input of the third gate 53. Another input of the third gate 53 is connected to an enabling input en, which may be controllable by the receiver circuit 30. The output of the third gate 53 is connected to the gate of the switching transistor 54. An input of the inverter 56 is also connected to the gate of the switching transistor 54 and the output of the inverter 56 is connected to or forms the current cell activation indicator output 28 at which a step_k+1 signal and hence a flag signal can be detected.

In an initial configuration and, when the electronic circuit 10 is in an idle mode before start-up, the trigger input 25 will not yet be provided with a trigger signal trig_k. The su_detb signal is initially at a logical 1. Accordingly, and in the initial state of the current cell 20 the output of the first gate 51 is a logical 1. The gate of the switching transistor 54 is at a logical 1 as well such that the output of the second gate 52 is at a logical 0. Since the electronic circuit 10 is in a working mode the enable signal en is at logical 1.

Accordingly, the output of the third gate 53 is at a logical 1 as well. Since the interrupt output 28 is connected to the gate of the switching transistor 54 via the inverter 56, there will be no signal present at the current cell activation indicator output 28.

When the electronic circuit 10 is now activated to generate a ramped current signal there will be provided a trigger signal trig_k at the trigger input 25. Toggling of the trigger input 25 from logical 0 to logical 1 will lead to the generation of a logical 0 at the output of the first gate 51. This logical 0 then leads to the generation of a logical 1 at the output of the second gate 52 and will induce generation of a logical 0 at the output of the third gate 53. Turning down the gate of the PMOS switch 54 from logical 1 to logical 0 will activate the switch 54 such that the current source 55 will be activated and will provide a current source specific current to the current output 60. Furthermore, the logical 0 at the gate of the switching transistor 54 will be transferred into a logical 1 via the inverter 56 at the current cell activation indicator output 28.

Hence, at the current cell activation indicator output 28 there will arise a flag signal step_k+1 indicating that the current source 55 has been switched on or has been activated.

As already indicated above providing the trigger signal trig_k to the trigger input 25 will generate a respective trigger signal trig_k+1 at the trigger output 26, wherein the trigger signal trig_k+1 at the output will arise or will be generated after lapse of a predefined transition time interval. Thereafter, a proceeding current source 21 will undergo the same transition and will add a respective supplemental current to the current supply 24.

The cascade of numerous current cells 20, 21, 22 will continue and each current cell 20, 21, 22 will add current cell specific current to the current supply 24 until the oscillation detector 32 detects that the total current as provided by the current supply 24 reaches or exceeds the critical current requested to start the regenerative oscillator. When reaching such target, the oscillation detector 32 generates a feedback signal and transfers this feedback signal as a logical 0 via the feedback line 35 to all interrupt inputs 27 of all current cells 20, 21, 22.

With the trigger signal 25 at a logical 1 and with a switching of the su_detb signal from a logical 1 to a logical 0 the trigger input 25 will be effectively decoupled from the logic unit 50 and hence from the current source 55. Insofar and by setting the interrupt inputs 27 of one of the current cells 20, 21, 22 to a logical 0 there can be provided an effective decoupling of the trigger input 25 from the current source 55. Then, the output of the first gate 51 will always be at a logical 1 irrespective of the value or signal provided at the trigger input 25.

Insofar, setting the su_detb signal at each interrupt input 27 of the current cell 20, 21, 22 to a logical 0 effectively freezes the current switching state of all current cells 20, 21, 22 even though the trigger signal may further propagate through the number of individual current cells 20, 21, 22. It may have no longer an effect on the switching behavior of a respective switching transistor 54.

At the same time and with the freezing of each current cell 20, 21, 22 there can be provided a stable and continuous current at the current supply 24. At the same time the current cell activation indicator output 28 of all current cells 20, 21, 22 is immediately indicative of the activation of the respective current source 55 of each activated current cell 20, 21, 22. This way, there is immediately provided a digital signal being indicative of a number of current cells 20, 21, 22 that have been activated until the reference current has been reached by the ramped current signal as provided at the current supply 24.

With a given transition time of each buffer 40 of the individual current cells 20, 21, 22, there can be derived a total ramp time in the digital domain that is required by the electronic circuit 10 to reach a predefined amplitude of an output current at the current supply 24.

The ramped current signal at the current supply 24 can be resetted by supplying a reset signal to the enabling input en. Then, and in response to such a reset signal the gate of the switching transistor 54 may be set to a logical 1 thus switching the switching transistor off.

It should be noted that the presently illustrated implementation of the basis of NAND gates and on the basis of PMOS transistors 54, 55 is only illustrative. The same or similar implementation can be easily obtained also on the basis of a positive logic and on the basis of NMOS switching devices.

Especially in the case of implementing a so-called super-regenerative receiver, the generation of a current ramp by the present regenerative receiver 1 is of particular benefit as it becomes possible to obtain a start-uptime directly in the digital domain by stopping the progression of the trigger chain, i.e., when the super-regenerative oscillator starts up, and consulting the thermometric number of current sources 55, 55′, 55″ that have been switched on, e.g., at the time the aforementioned oscillator starts up.

A simple thermometric to binary conversion can then be used to deduce the equivalent start-up time. The present type of thermometric generator is particularly well-suited to operation at very low voltages and has an ideal characteristic for “shrink” to smaller technologies. In the case of current generation, because the number of analog components is extremely limited, the noise performance of the system is excellent.