FIG. 1, the pattern memory 3 is rewritable such that the pattern stored therein can be changed or updated. It is noted that in the optional case that the pattern memory (PM) is suitable for storing therein a dynamic pattern, typically the procedure to update the PM may include the PM receiving a write enable signal along with a data input indicating the desired pattern, so that the pattern stored in the PM is modified as commanded by said data input and write enable signal.

In the embodiment of FIG. 1, the pattern-enable array 4 comprises memory elements 6 each of which is associated with a respective address of a corresponding one of the entries of the target memory 2 and is configured to be reversibly set to a state which is indicative of whether the respective address of the corresponding entry of the target memory 2 is associated with the stored pattern or not. Preferably said state corresponds to the value of at least one bit that may be stored in each of said elements. Therefore, in a non-limiting example, when the value of a bit stored in a memory element of the pattern-enable array is “1” and said memory element is associated with an address of the target memory, wherein in said address an entry or part of said entry is stored, then said value of “1” may indicate that said address is associated with the pattern which is stored in the pattern memory. If however said value is “0”, then this may indicate that the said address of the target memory, and consequently the entry that is stored in said address, is not associated with the pattern stored in the pattern memory. However, it is noted that the opposite may also occur in some embodiments i.e. when the value of a bit stored in a memory element of the pattern-enable array is 0 that may indicate that the corresponding address and stored entry in the target memory are associated with the pattern, whereas when said value is “1” that may indicate that said corresponding address and stored entry are not associated with the pattern. It is also noted that, in the present text saying that a memory element has been set to a state that indicates that the corresponding address or entry in the target memory is associated with the pattern stored in the pattern memory, may also be expressed by saying that said memory element or the pattern-enable array as a whole has been “enabled”. Also, in the present text saying that said address or entry in the target memory is associated with the pattern, may also be expressed by saying that for said address or entry the pattern is “active”. Also, with respect to the memory elements of the pattern-enable array, it is noted that preferably each one of said memory elements is able to (i.e. is configured to or suitable to): store at least one bit per every accessible entry in the target memory in order to indicate whether the pattern is active or not; and be written in the desired access time (in particular, for 1-cycle writes this element must be able to write in 1 cycle). In some non-limiting examples, said memory elements are composed of flip-flops or latches, which may store 1 bit of information per element as a bistable multivibrator. However, other types of memory elements may alternatively be used.

In the embodiment of FIG. 1, the pattern-enable array 4 is further configured to receive a corresponding input related to any one of the memory elements 6, and to output a respective output PEA_outwhich is indicative of the state of the corresponding memory element 6. More specifically, when in the embodiment of FIG. 1 the digital circuit is in operation, the input that may be received by pattern-enable array 4 may comprise a pattern address input P1 and a pattern enable input PE. The pattern address input P1 indicates the address of a respective entry with which the pattern is to be associated with. The pattern enable input PE indicates that the address of the respective entry indicated by the pattern address input P1 should be associated with the pattern. Therefore, in a an operation of a preferred embodiment, P1 may indicate a specific address or entry in the target memory, and PE may indicate that the corresponding memory element (i.e. the memory element that corresponds to said specific address or entry) in the pattern-enable array should be “enabled” (e.g. set the value of a bit stored in said memory element to “1”) so that the pattern is “active” for said specific address or entry. Also, in the embodiment of FIG. 1, when the digital circuit is in operation, the input that may be received by pattern-enable array 4 may further comprise the input read address R1, the input write address W1 and the write enable input WE which have been mentioned further above.

Also, in the embodiment of FIG. 1, the multiplexer 5 is configured to receive as respective inputs the output TM_outof the target memory 2, the output PM_outof the pattern memory 3 and the output PEA_outof the pattern-enable array 4. Also, the multiplexer 5 is configured to select between said output TM_outof the target memory 2 and said output PM_outof the pattern memory 3, using the output PEA_outof the pattern-enable array 4 for enabling the selection. Specifically, as can be understood from FIG. 1, the output PEA_outof the pattern-enable array 4 is received by the multiplexer 5 as an input, and acts as a select line that determines which one of the other two inputs TM_outand PM_outof the multiplexer should be passed to the output D_outof the multiplexer 5.

A preferred embodiment of a digital circuit of the first aspect of the disclosure is explained next with reference to FIG. 2. The embodiment of FIG. 2 is according to the embodiment of FIG. 1 and hence comprises all the aforementioned features of the embodiment of FIG. 1. Also, the embodiment of FIG. 2 comprises an additional multiplexer 7 via which the output PEA_outof the pattern-enable array 4 is provided to the first multiplexer 5 of the digital circuit. Said additional multiplexer may preferably be integrated in, and hence be part of, the pattern enable array, or may be a separate part of the digital circuit. Also, in the embodiment of FIG. 2, said additional multiplexer 7 is configured to receive the input read address R1 as a select line. Hence, in the embodiment of FIG. 2 said input read address R1 is used to feed the additional multiplexer 7 in order to select the proper entry/stored information in the PEA which will indicate whether the data from the TM or the pattern from the PM should be the output D_outof the first multiplexer 5. It is noted that other schemes are also possible depending on the characteristics of the TM. In particular, it is a contemplated that in the optional case that the TM outputs data in a cycle different than when the address is set (a common case for larger memories), the address may need to be stored in the PEA or in another suitable optional component of the digital circuit, in order to facilitate or enable that a pattern enable bit in the PEA is driven at the appropriate time.

An operation that may be made in/with any one of the preferred embodiments of FIG. 1 and FIG. 2 is illustrated by the diagram of FIG. 3. In the diagram of FIG. 3 “clk” indicates clock pulses of a repeating clock signal used in the digital circuit, and the time interval between two consecutive pulses sets the duration of 1 cycle (i.e. clock cycle) as indicated in FIG. 3. If when using said digital circuit a user of the circuit wants to read entry A, then R1 will be fed into the TM to indicate that entry A must be read/accessed, and the resulting output TM_outfrom the TM will be D[A] as shown in FIG. 3. Also, if according to the information stored in the PEA, the pattern which is stored in the PM is “active” for said entry A, then this is indicated by the output PEA_outshown in FIG. 3. Also, the PM outputs an output PM_outwhich corresponds to the pattern and is the signal PAT that is indicated in FIG. 3. Due to the fact that the PEA_outindicates that the pattern is “active” for said entry A, the multiplexer 5 selects PAT over TM_out, and hence, the output D_outof the multiplexer 5 will be PAT as shown in FIG. 3. Therefore, the data that are read during the operation illustrated by FIG. 3, will be the data contained in the pattern. However, in the same preferred embodiment, if the pattern was not set for entry A, i.e. if said pattern is not “active” for said entry A and, hence, the corresponding state of the respective memory element of the PEA indicates that there is no association between the pattern and the respective address of the entry in the TM (e.g. if the value of a bit stored in said memory element is set to “0”) then PEA_outmay be a flat signal as illustrated in FIG. 4. Then, as is also illustrated by FIG. 4, during the operation of the digital circuit the data that would be read and outputted by the multiplexer would be the data contained in the TM. Hence, in the case of the operation illustrated by FIG. 4, D_out=D[A]. It is noted that in/with some embodiments which are similar to the ones of FIG. 1 and FIG. 2, there may be performed operations which are similar to the ones shown in FIG. 3 and FIG. 4, but in which the duration from the moment R1 is fed into the TM until the moment that the D_outis outputted by the multiplexer 5 may be different compared to the one shown in FIG. 3 and FIG. 4, and particularly, said duration may be less than the duration of one cycle or may be equal to the total duration of a plurality of cycles.

A preferred embodiment of a digital circuit of the first aspect of the disclosure is explained next with reference to FIG. 5. The embodiment of FIG. 5 is according to the embodiments of FIG. 1 and FIG. 2, and hence comprises all the aforementioned features of the embodiments of FIGS. 1 and 2. However, in contrast to the embodiment of FIG. 2, in the embodiment of FIG. 5 the additional multiplexer 7 is part of the pattern-enable array 4 (“PEA”). Also, in the embodiment of FIG. 5 said pattern-enable array 4 comprises two decoders shown on the left of FIG. 5. The decoders are configured to transform an address into a 1-hot bit that corresponds to the entry of the address. For example, an address “5” will be decoded into a series of “0”s where only the bit number “5” will be set to “1” instead of “0”. The decoder on top is configured to decode the write address which is indicated by W1, while the decoder on the bottom is configured to decode the pattern address which is indicated by P1. When the pattern enable signal PE is set, i.e. when PE indicates that the pattern should be associated with the address given by P1, the pattern enable cell (i.e. the memory element of the PEA) corresponding to said address given by P1 will be set to “1”. When the write enable signal WE is set, i.e. when WE indicates a modification/update of the entry in the address indicated by W1, then the Pattern Enable cell corresponding to the write address given by W1 will be set to “0”. If both addresses aim at the same entry, the corresponding Pattern Enable cell will be set to “0”. It is noted that for memories with several write ports, several decoders may be used. Similarly, it is possible to add several pattern enable ports by adding more decoders.

In a preferred embodiment which is according to the embodiments of FIG. 1 and FIG. 5, the target memory 2 is configured to allow updating one or more portions of one of the entries while leaving the rest of said one entry unchanged, each of said portions corresponding to a byte, such that the target memory 2 has a byte enable functionality. Also, in said embodiment where the target memory has the byte enable functionality, the respective input of the target memory 2 further comprises a byte enable signal input BE. Said byte enable signal input BE comprises bits each of which corresponds to a respective byte of the data bus input WD, such that the value of each bit of the byte enable signal input BE indicates whether each of the bytes of the corresponding entry of the target memory 2 should be updated according to the corresponding byte of the data bus input WD or not.

A non-limiting example of an operation that may be performed in a preferred embodiment that comprises the aforementioned target memory with the byte enable functionality is explained next with reference to FIG. 7 and FIG. 8. In the latter preferred embodiment, the target memory with the byte enable functionality advantageously allows writing only in portions of a memory entry, while leaving the other portions undisturbed. For the implementation of said byte enable functionality the target memory may be able to receive as input a byte enable signal BE via a byte enable bus. A byte enable bus may be ⅛th of the size of a data bus. Every bit in the byte enable bus may corresponds to a byte in the data bus. FIG. 7 schematically illustrates a 32-bit data bus with enumerated bits from “0” to “31”, and also illustrates a corresponding byte enable bus of four bits (since 32/8=4). When writing into said target memory that has the byte enable functionality, only the bytes that correspond to the byte enable signal BE set to “1” will be written. For example, FIG. 8 shows an entry A stored in the target memory memory.