>FIG. 2A to FIG. 2C are cross-sectional diagrams of the manufacturing process of a magnetoresistive random access memory according to an embodiment of the disclosure.

FIG. 2A to FIG. 2C are cross-sectional diagrams of a forming method of a magnetoresistive random access memory, and are also cross-sectional diagrams of a forming method of the integrated circuit 10 of FIG. 1.

As mentioned above, since the magnetoresistive random access memory is disposed in the BEOL process, it may be readily integrable with the manufacturing processes of other semiconductor devices, forming a multifunctional and highly efficient integrated circuit.

In order to better understand the advantages of the disclosure, the following cross-sectional diagrams of the manufacturing process illustrate the magnetoresistive random access memory of the disclosure side by side with the logic device. However, the application of the disclosure is not limited thereto. The magnetoresistive random access memory of the disclosure may be used together with other semiconductor devices.

Firstly, please refer to the integrated circuit 10 shown in FIG. 2A, which includes a magnetoresistive random access memory region A and a logic device region B.

As shown in FIG. 1, in order to focus on the magnetoresistive random access memory in the BEOL process of the disclosure, FIG. 2A to FIG. 2C omit the logic devices disposed in/on the semiconductor substrate 100 and the first half portion of the metal interconnect layered structure disposed on the semiconductor substrate 100. The first half portion of the metal interconnect layered structure (not shown) includes one or more interlayer dielectric layers. The first interlayer dielectric layer includes contact plugs that are in direct contact with the logic devices. The other interlayer dielectric layers include via plugs, metal conductive lines, and various other components.

In the first half portion of the omitted metal interconnect layered structure and the metal interconnect layered structure mainly described in the disclosure, the referred dielectric layer may include, for example, nitride (e.g., silicon nitride, silicon oxynitride), carbide (e.g., silicon carbide), oxides (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), low dielectric constant oxide (e.g., carbon-doped oxide, SiCOH), or some other suitable dielectric material. Various components such as contact plugs, via plugs, and metal conductive lines may include tantalum, titanium, copper, tungsten, aluminum, or some other suitable conductive material.

Moreover, the process for forming the first half portion of the omitted metal interconnect layered structure and the metal interconnect layered structure mainly described in the disclosure includes various steps, and the various steps include a deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PE-CVD), atomic layer deposition (ALD), sputtering, etc.), a removal process (e.g., wet etching, dry etching, chemical mechanical planarization (CMP), etc.), and/or a patterning process (e.g., lithography/etching).

Continue referring to FIG. 2A, in the magnetoresistive random access memory region A and the logic device region B, a lower dielectric layer 200 and a lower metal layer 250 are formed on the semiconductor substrate 100, and the lower metal layer 250 is located in the lower dielectric layer 200 and is electrically connected to the front and rear conductive layers.

Referring to FIG. 2B, in the magnetoresistive random access memory region A, on the lower metal layer 250, the via plug 310, the magnetic tunnel junction 320, and the additional metal layer 330 are formed in sequence. The via plug 310 is electrically connected to the lower metal layer 250, the magnetic tunnel junction 320 is disposed on the via plug 310, and the additional metal layer 330 is disposed on the magnetic tunnel junction 320.

The magnetic tunnel junction 320 includes a multilayer structure, such as a bottom electrode, a magnetic memory body, an upper cap layer, and an upper electrode, but not limited thereto. The magnetic tunnel junction 320 may also include other materials and structures that serve as the magnetic tunnel junction. For the sake of simplicity and clarity, the multilayer structure is not shown in the figures of this application and may be formed in various ways.

Continue referring to FIG. 2B, in the magnetoresistive random access memory region A and the logic device region B, a dielectric layer 300 is formed on the lower dielectric layer 200 and the lower metal layer 250, and covers the via plug 310, the magnetic tunnel junction 320, and the additional metal layer 330 in the magnetoresistive random access memory region A. The dielectric layer 300 may be formed one or more times as required. For example, an insulating material such as silicon nitride may be initially formed on the sidewalls of the via plug 310, the magnetic tunneling junction 320, and the additional metal layer 330, followed by a comprehensive deposition of dielectric materials such as silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), or SiCOH.

Next, chemical mechanical polishing (CMP) or other methods may be used as required to comprehensively planarize the dielectric layer 300, and the dielectric layer 300 is etched to expose the upper surface 330U of the additional metal layer 330 and the upper surface 250U of the lower metal layer 250 in the logic device region B.

The upper surface 330U of the additional metal layer 330 is coplanar with the upper surface 300U of the dielectric layer 300, and the lower surface 310L of the via plug 310 is coplanar with the lower surface 300L of the dielectric layer 300.

Next, as shown in FIG. 2B, a via plug 340 and a metal layer 350 are formed in the logic device region B.

Continue referring to FIG. 2B, the via plugs 310 in the magnetoresistive random access memory region A and the via plugs 340 in the logic device region B are both made of conductive materials, but may have different sizes and depths based on the different devices/components connected, and may be filled with different conductive materials to match with the requirements. For example, the via plug 310 in the magnetoresistive random access memory region A is made of tungsten, and the via plug 340 in the logic device region B is made of copper, but not limited thereto.

Referring to FIG. 2C, in the magnetoresistive random access memory region A and the logic device region B, an upper dielectric layer 400 is formed on the dielectric layer 300, the additional metal layer 330 and the metal layer 350, and an upper via plug 440 and an upper metal layer 450 are formed in the upper dielectric layer 400. The upper via plug 440 located in the magnetoresistive random access memory region A is electrically connected to the additional metal layer 330, and the upper via plug 440 located in the logic device region B is electrically connected to the metal layer 350 to complete the integrated circuit 10 as shown in FIG. 1.

FIG. 3 is a cross-sectional diagram of a magnetoresistive random access memory according to another embodiment of the disclosure.

Since the integrated circuit 20 of FIG. 3 has some similar structures to the integrated circuit 10 of FIG. 1, the same components are labeled with the same symbols, and repeated descriptions are omitted. The following only describes the differences in components.

As shown in FIG. 3, the magnetoresistive random access memory region A includes a via plug 310, a bottom electrode 360, and a magnetic tunnel junction 320 disposed in the dielectric layer 300. The via plug 310 is electrically connected to the lower metal layer 250, the bottom electrode 360 is disposed on the via plug 310, and the magnetic tunnel junction 320 is disposed on the bottom electrode 360.

Due to the existence of the bottom electrode 330 in the magnetoresistive random access memory region A, the upper surface 320U of the magnetic tunnel junction 320 is coplanar with the upper surface 300U of the dielectric layer 300, and the lower surface 310L of the via plug 310 may be coplanar with the lower surface 300L of the dielectric layer 300.

It is worth noting that the thickness of the bottom electrode 360 is different from the bottom electrode of the conventional magnetic tunnel junction. Generally speaking, the bottom electrode 360 used in the disclosure is thicker than the bottom electrode layer of the conventional magnetic tunnel junction. The bottom electrode 360 is adjusted with the objective of making the upper surface 320U of the magnetic tunnel junction 320 coplanar with the upper surface 300U of the dielectric layer 300.

The thickness of the bottom electrode 360 is thickened from the conventional thickness of about 120 angstroms to 180 angstroms to about 550 angstroms to 600 angstroms, preferably about 580 angstroms to 600 angstroms, and most preferably about 590 angstroms to 600 angstroms.

The bottom electrode 360 includes tantalum, tantalum nitride, titanium, titanium nitride, copper, tungsten or some other suitable conductive material. For example, tantalum or tantalum nitride is used.

By forming the bottom electrode 360 under the magnetic tunnel junction 320 through this disclosure, the via depths required for the via plugs between different devices may be close or even the same. This reduces the need for excessive etching and resolves issues such as the abnormal profile of the upper via plug 440 in the MRAM region A and the open phenomenon of the upper via plug 440 in the logic device region B. Consequently, the electrical performance of the integrated circuit 20 is maintained within the desired range, thereby improving the overall yield of the wafer.

FIG. 4A to FIG. 4B are cross-sectional diagrams of the manufacturing process of a magnetoresistive random access memory according to another embodiment of the disclosure.

FIG. 4A to FIG. 4B are cross-sectional diagrams of a forming method of another magnetoresistive random access memory, and are also cross-sectional diagrams of a forming method of the integrated circuit 20 of FIG. 3.

Since the forming method of the integrated circuit 20 in FIG. 4A to FIG. 4B and the forming method of the integrated circuit 10 in FIG. 2A to FIG. 2C have similar processes and the same components, the same components are labeled with the same symbols, and repeated descriptions are omitted. The following only describes the differences in forming methods.

Firstly, referring to FIG. 4A, which corresponds to the aforementioned FIG. 2B, but in the magnetoresistive random access memory region A, on the lower metal layer 250, a via plug 310, a bottom electrode 360, and a magnetic tunnel junction 320 are sequentially formed. The via plug 310 is electrically connected to the lower metal layer 250, the bottom electrode 360 is disposed on the via plug 310, and the magnetic tunnel junction 320 is disposed on the bottom electrode 360.

The magnetic tunnel junction 320 includes a multilayer structure, such as a magnetic memory body, an upper cap layer, and an upper electrode, but not limited thereto. The magnetic tunnel junction 320 may also include other materials and structures that serve as the magnetic tunnel junction. For the sake of simplicity and clarity, the multilayer structure is not shown in the figures of this application and is formed in various ways.

The bottom electrode 360 may include tantalum, tantalum nitride, platinum, titanium, copper, tungsten, aluminum or some other suitable conductive material. For example, tantalum nitride or platinum is used.

Continue referring to FIG. 4A, in the magnetoresistive random access memory region A and the logic device region B, a dielectric layer 300 is formed on the lower dielectric layer 200 and the lower metal layer 250, and covers the via plug 310, the bottom electrode 360, and the magnetic tunnel junction 320 in the magnetoresistive random access memory region A. The dielectric layer 300 may be formed one or more times as required. For example, an insulating material such as silicon nitride may be initially formed on the sidewalls of the via plug 310, the bottom electrode 360, and the magnetic tunneling junction 320, followed by a comprehensive deposition of dielectric materials such as silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), or SiCOH.

Next, chemical mechanical polishing (CMP) or other methods may be used as required to comprehensively planarize the dielectric layer 300, and the dielectric layer 300 is etched to expose the upper surface 320U of the magnetic tunnel junction 320 and the upper surface 250U of the lower metal layer