In the wireless communications system 100, an electromagnetic (EM) spectrum may be split, based on frequency or wavelength, into various classes, frequency bands, frequency channels, etc. By way of example, the wireless communications system 100 may support one or multiple operating frequency bands, such as frequency range designations FR1 (410 MHz-7.125 GHZ), FR2 (24.25 GHz-52.6 GHZ), FR3 (7.125 GHZ-24.25 GHZ), FR4 (52.6 GHz-114.25 GHZ), FR4a or FR4-1 (52.6 GHz-71 GHz), and FR5 (114.25 GHz-300 GHz). In some implementations, the NEs 102 and the UEs 104 may perform wireless communications over one or more of the operating frequency bands. In some implementations, FRI may be used by the NEs 102 and the UEs 104, among other equipment or devices for cellular communications traffic (e.g., Econtrol information, data). In some implementations, FR2 may be used by the NEs 102 and the UEs 104, among other equipment or devices for short-range, high data rate capabilities.

FR1 may be associated with one or multiple numerologies (e.g., at least three numerologies). For example, FR1 may be associated with a first numerology (e.g., μ=0), which includes 15 kHz subcarrier spacing; a second numerology (e.g., μ=1), which includes 30 kHz subcarrier spacing; and a third numerology (e.g., μ=2), which includes 60 kHz subcarrier spacing. FR2 may be associated with one or multiple numerologies (e.g., at least 2 numerologies). For example, FR2 may be associated with a third numerology (e.g., μ=2), which includes 60 kHz subcarrier spacing; and a fourth numerology (e.g., μ=3), which includes 120 kHz subcarrier spacing.

A UE 104 transmits to the NE 102 (e.g., a gNB) an indication of differences in insertion losses between a reference SRS port and each of one or more additional SRS ports. This indication of differences in insertion losses can be, for example, at least one of the differences in insertion losses between the reference SRS port and each of the one or more additional ports or differences in configured maximum power values between the reference SRS port and each of the one or more additional ports. The UE 102 also transmits to the NE 102 (e.g., a gNB) a power headroom report for less than all SRS ports in a set of SRS ports that include the reference SRS port and the one or more additional SRS ports. The reference SRS port can be, for example, an SRS port of the UE 104 having a smallest insertion loss, and the power headroom report can include a configured maximum power for the SRS port having the smallest insertion loss. This information allows the NE 102 (e.g., a gNB) to compute the transmit power for each of the SRS ports.

FIG. 2 illustrates an example 200 of power headroom reporting for sounding reference signal transmissions in accordance with aspects of the present disclosure. In the example 200, an NE 102 (e.g., a gNB) transmits an SRS configuration 202 to a UE 104, indicating to the UE 104 when and how to transmit SRS. The UE 104 transmits an indication of differences in insertion losses 204, such as at least one of insertion losses between a reference SRS port of the set or SRS ports 206 and each of one or more additional ports in the set of SRS ports 206, or differences in configured maximum power values between the reference SRS port of the set of SRS ports 206 and each of one or more additional ports in the set of SRS ports 206 to the NE 102. The reference SRS port can be any of the SRS ports 206, such as the SRS port with the smallest insertion loss.

The UE 104 also transmits to the NE 102 a power headroom report 208 in response to various events or at various times, which may be configured by the NE 102. The power headroom report indicates how much transmission power is left for the UE 104 to use in addition to the amount of transmission power already being used. The power headroom report is transmitted for one SRS port of the UE 104 (e.g., the SRS port with the smallest insertion loss). The power headroom report is for less than all SRS ports in the set of SRS ports 206, e.g., for a single SRS port of the SRS ports 206. Furthermore, the indication of differences in insertion losses 204 need not be reported to the NE 102 every time a power headroom report 208 is reported to the NE 102. Rather, the indication of differences in insertion losses 204 can be reported to the NE 102 in response to a change in the insertion losses, such as change in the SRS port to antenna mappings.

The techniques discussed herein are directed to the issue of insertion loss imbalance across SRS ports. These additional insertion losses arise from transmitting SRS from antenna ports that are receive only except for SRS transmission.

With respect to the impact of SRS power relaxations on power control behavior, the UE 104 is allowed to specify its maximum configured power PC_MAX,f,cin the range

P

CMAX
⁢
_
⁢
L

,
f
,
c

≤

P

CMAX
,
f
,
c

≤
H

,

P

CMAX
⁢
_
⁢
H

,
f
,
c

⁢

with

P

CMAX
⁢
_
⁢
L

,
f
,
c

=
 

MIN
⁢

{

P

EMAX
,
c

-
Δ
⁢

T

C
,
c

,

(

P
PowerClass

-

Δ
⁢

P
PowerClass

+

Δ
⁢

P
PowerBoost

)

-
 

MAX
⁢

(

MAX
⁢

(

MPR
c

+

Δ
⁢

MPR
c

,

A
-

MPR
C

)

+
 

Δ
⁢

T

IB
,
c

+

Δ
⁢

T

C
,
c

+

Δ
⁢

T
RxSRS

,
 

P
-

MPR
c

)

}

P

CMAX
⁢
_
⁢
H

,
f
,
c

=

MIN
⁢

{

P

EMAX
,
c

,

P
PowerClass

-

Δ
⁢

P
PowerClass

+

Δ
⁢

P
PowerBoost

}

,

where PC_{MAX_H,f,c}is the upper bound on maximum configured power and PC_{MAX_L,f,c}is the lower bound on maximum configured power. Because different SRS ports can have different values of ΔT_RxSRS, each SRS port can set its own maximum configured power. Further, since the configured maximum power PC_MAX,f,cis not required to be equal to PC_{MAX_L,f,c}, the configured maximum power PC_MAX,f,cand PC_MAX,f,ccan be different for two SRS ports even if they have the same value of ΔT_RxSRS.

The allowed power relaxations can be divided into two types, including Type 1: MPR_c, ΔMPR_c, A-MPR_c, P-MPR_c, ΔP_PowerClass, ΔP_PowerBoost; and Type 2: ΔT_IB,c, ΔT_C,c, ΔT_RxSRS.

Type 1 maximum power relaxations are taken by the UE 104 in order meet emissions, regulatory, or other requirements. The UE 104 knows both the values of these relaxations and the conditions under which they are taken. The UE 104 may take power relaxations less than the maximum allowed, but if it does, then the UE 104 knows the values.

Type 2 power relaxations are not applied by the UE 104 but are the result of implementation losses. These power relaxations exist at all output power levels unless compensated by the UE 104. The value of ΔT_C,cis 1.5 dB at the band edge and is otherwise 0. The value of ΔT_IB,cis typically less than 0.5 dB, but it can be as large as 1.5 dB.

The allowed relaxation ΔT_C,cis frequency dependent, while the relaxation ΔT_IB,cis band combination dependent. The allowed value of these relaxations is not port dependent, but the actual values could possibly be port dependent depending on the architecture and the filters used. The allowed relaxation ΔT_RxSRSis port dependent and so can be denoted ΔT_RxSRS,jfor the j-th SRS port.

Given that there are three types of power relaxations that are allowed for implementation losses, ΔT_C,c, ΔT_IB,c, and ΔT_RxSRS,j, one consideration is whether a UE 104 is expected to compensate all of these power relaxations below P_CMAX, or only expected to compensate ΔT_RxSRS,j. Another consideration is if a UE 104 indicates that it compensates the SRS power relaxations ΔT_RxSRS,jbelow P_CMAX, is the UE 104 expected or required to compensate all of the Type 2 power relaxations ΔT_C,c, ΔT_IB,c, and ΔT_RxSRS,j.

With respect to signaling and compensation of SRS power relaxation, let

Δ
⁢

T

RxSRS
,
j

A

denote the actual insertion loss associated with the j-th antenna port. For two antenna ports i and j, let the difference in the configured maximum power between two antenna ports be defined as δ_i,j, where

δ

i
,
j

=

P

CMAX
,
f
,
c

(
i
)

-

P

CMAX
,
f
,
c

(
j
)

,

and P_{CMAX_L,f,c}(i) denotes the P_CMAXvalue for the i-th antenna port. It can typically be expected that

P

CMAX
,
f
,
c

(
i
)

-

P

CMAX
,
f
,
c

(
j
)

=

Δ
⁢

T

RxSRS
,
j

A

-

Δ
⁢

T

RxSRS
,
i

A

so that

δ

i
,
j

=

Δ
⁢

T

RxSRS
,
j

A

-

Δ
⁢

T

RxSRS
,
i

A

,

though this is not a requirement. For example, a different MPR or A-MPR relaxation (less than the maximum allowed) could be chosen for the i-th antenna port than for the j-th antenna port, but in one or more implementations this behavior is not expected.

It is expected that the difference between the configured maximum power for two ports i and j given by

δ

i
,
j

=

P

CMAX
,
f
,
c

(
i
)

-

P

CMAX
,
f
,
c

(
j
)

is fixed and is independent of the resource block (RB) allocation and is equal to the difference in SRS insertion loss so that

δ

i
,
j

=

Δ
⁢

T

RxSRS
,
j

A

-

Δ
⁢

T

RxSRS
,
i

A

.

The N antenna ports used for SRS transmission are numbered such that

δ

1
,
j

≥

0
⁢

for
⁢

all
⁢

1

≤
j
≤

N
.

For example, port 1 could be defined for an SRS port for which no relaxation is allowed. If port 1 is used, this implies that

P

CMAX
,
f
,
c

(
1
)

-

P

CMAX
,
f
,
c

(
j
)

≥

0
⁢

for
⁢

all
⁢

1

≤
j
≤
N

or equivalently, that

P

CMAX
,
f
,
c

(
1
)

≥

P

CMAX
,
f
,
c

(
j
)

⁢

for
⁢

all
⁢

1

≤
j
≤
N

For each SRS occasion, it is assumed that the UE 104 signals two of the three quantities for port 1: i) the transmitted power p_t,1; ii) the maximum configured power P_CMAX,f,c(i); iii) the power headroom for port p_H,1. These three quantities have the relationship

P

CMAX
,
f
,
c

(
1
)

=

p

t
,
1

+

p

H
,
1

.

For the case in which the UE 104 signals the N−1 difference δ_i,j, 2≤j≤N, there are two alternative cases for handling insertion losses.

In Case 1, the UE 104 compensates the transmit power for the insertion losses for each antenna port i up to P_CMAX,f,c(i). In Case 2, the UE 104 does not compensate the transmit power for the insertion losses.

For Case 1, it can be assumed that the insertion loss that is compensated is the actual SRS insertion loss

Δ
⁢

T

RxSRS
,
j

A

,

or it can be assumed that the compensated insertion loss is the sum of the actual SRS insertion loss

Δ
⁢

T

RxSRS
,
j

A

and the other insertion losses ΔT_C,cand ΔT_IB,c. Unless ΔT_C,cand ΔT_IB,care port dependent, it should still be the case that

P

CMAX
,
f
,
c

(
i
)

-

P

CMAX
,
f
,
c

(
j
)

=

Δ
⁢

T

RxSRS
,
j

A

-

Δ
⁢

T

RxSRS
,
i

A

=

δ

i
,
j

.

For both Case 1 and Case 2, the transmit power for any port j can be determined from the difference in the insertion loss δ_1,j, the transmit power on the first antenna port, p_t,1, and the configured maximum power for the first antenna port P_CMAX,f,c(1)

For Case 1, the UE 104 compensates the insertion loss for the j-th antenna port up to PCMAX,f,c (j) for the j-th antenna port which can be expressed as

P

CMAX
,
f
,
c

(
j
)

=

P

CMAX
,
f
,
c

(
1
)

-
 

(

P

CMAX
,
f
,
c

(
1
)

-

P

CMAX
,
f
,
c

(
j
)

)

=

P

CMAX
,
f
,
c

(
1
)

-

δ

1
,
j

,

since the UE 104 compensates the insertion loss, the transmit power for the j-th antenna port is given by

p

t
,
j

=

{

p

t
,
1

p

t
,
1

≤

P

CMAX
,
f
,
c

(
1
)

-

δ

1
,
j

P

CMAX
,
f
,
c

⁢

(
1
)

-

δ

1
,
j

p

t
,
i

>

P

CMAX
,
f
,
c

(
1
)

-

δ

1
,
j

.

It should be noted that this approach only works if

P

CMAX
,
f
,
c

(
1
)

≥

P

CMAX
,
f
,
c

(
j
)

⁢

for
⁢

all

≤
j
≤

N
.

Otherwise, there exists an index j such that

P

CMAX
,
f
,
c

(
j
)

>

P

CMAX
,
f
,
c

(
1
)

from which it follows that δ_1,j<0. Since

p

t
,
1

≤

P

CMAX
,
f
,
c

(
1
)

and since δ_1,j<0, it must also be true that

p

t
,
1

≤

P

CMAX
,
f
,
c

(
1
)

-

δ

1
,
j

.

In this case in which the insertion losses are compensated,

p

t
,
j

=

{

p

t
,
1

p

t
,
1

≤

P

CMAX
,
f
,
c

(
1
)

-

δ

1
,
j

P

CMAX
,
f
,
c

⁢

(
1
)

-

δ

1
,
j

p

t
,
i

>

P

CMAX
,
f
,
c

(
1
)

-

δ

1
,
j

}

=

p

t
,
1

.

However, since it was assumed that

P

CMAX
,
f
,
c

(
j
)

>

P

CMAX
,
f
,
c

(
1
)

,

then p_t,jcan be larger than p_t,1, and so this is a contradiction.

For Case 2 in which the UE 104 does not compensate the insertion loss,

p

t
,
j

=

p

t
,
1

-

δ

1
,
j

,

where, as noted above

δ

l
,
j

=

P

CMAX
,
f
,
c

(
1
)

-

P

CMAX
,
f
,
c

(
j
)

=

Δ
⁢

T

RxSRS
,
j

A

-

Δ
⁢

T

RxSRS
,
i

A

.

From the above, the techniques correct the SRS based channel estimates for the allowed power imbalances.

In a first step or act, the UE 104 signals the set of values δ_1,jfor all 1≤j≤N to the NE 102 (e.g., a gNB) where N is the number of SRS ports,

δ

i
,
j

=

P

CMAX
,
f
,
c

(
i
)

-

P

CMAX
,
f
,
c

(
j
)

and the SRS ports are numbered such that

δ

1
,
j

≥

0
⁢

for
⁢

all
⁢

1

≤
j
≤

N
.

These values are a function of the switching and trace losses and can only be signaled when there is a change in the mapping or numbering of the antenna ports.

In a second step or act, the UE 104 indicates whether or not it compensates the SRS transmit power for the i-th antenna port up to the configured maximum power for the port given by PC_MAX,f,c(i).

In a third step or act, for each SRS occasion, it is assumed that the UE 104 signals two of the three quantities for port 1 as defined above: i) the transmitted power p_t,1; ii) the maximum configured power P_CMAX,f,c(1); iii) the power headroom for port P_H,1. These three quantities have the relationship

P

CMAX
,
f
,
c

(
1
)

=

p

t
,
1

+

p

H
,
1

.

In a fourth step or act, for a UE 104 that indicates that it compensates the SRS insertion loss for the j-th antenna port up to P_CMAX,f,c(1), the NE 102 (e.g., a gNB) corrects the channel estimate from δ_1,j, p_t,1, and P_CMAX,f,c(1) using

p

t
,
j

=

{

p

t
,
1

p

t
,
1

≤

P

CMAX
,
f
,
c

(
1
)

-

δ

1
,
j

P

CMAX
,
f
,
c

⁢

(
1
)

-

δ

1
,
j

p

t
,
i

>

P

CMAX
,
f
,
c

(
1
)

-

δ

1
,
j

.

For a UE 104 indicating that is does not compensate the SRS insertion loss, the NE 102 (e.g., a gNB) corrects the channel estimate for the j-th UE antenna port from δ_1,jand p_t,1using

p

t
,
1

≤

P

CMAX
,
f
,
c

(
1
)

-

δ

1
,
j

.

FIG. 3 illustrates an example 300 of compensation of implementation losses in accordance with aspects of the present disclosure. The example 300 illustrates compensation of

Δ
⁢

T
RxSRS
A

implementation losses. In the example 300, the behavior of the output power versus the power control setting P_SRS,b,f,c(i, q_s, l, p) in combination with the actual power relaxations

Δ
⁢

T
RxSRS
A

is considered. The UE 104 actively compensates for losses by adjusting the power at power amplifier 302 when switching at 304 between the SRS ports (e.g., port j 306, port k 308, and port l 310), as shown in this example 300.

FIG. 4 illustrates an example 400 of SRS output power versus power control with and without compensation in accordance with aspects of the present disclosure. The example 400 illustrates SRS output power vs. power control with and without compensation of

Δ
⁢

T
RxSRS
A

In the example 400, the SRS output power is shown as a function of the power control setting P_SRS,b,f,c(i, q_s, l, p) both when the implementation loss

Δ
⁢

T
RxSRS
A

is compensated and with it is not compensate. From the example 400, it can be seen that if the implementation loss is not compensated, the SRS output power is shifted down by

Δ
⁢

T
RxSRS
A

,

and furthermore, ine maximum power at the antenna connector is reduced to

P

CMAX
,
f
,
c
,
p

(
i
)

-

Δ
⁢

T
RxSRS
A

.

Unless the UE 104 compensates the SRS relaxations as indicated in FIG. 3, the SRS output power will lag the power control setting P_SRS,b,f,c(i, q_s, l, p) by

Δ
⁢

T

RxSRS
,
p

A

.

Since the maximum value of the power control setting P_SRS,b,f,c(i, q_s, l, p) is P_CMAX,f,c,p(i), the maximum power at the antenna connector will be

P

CMAX
,
f
,
c
,
p

(
i
)

-

Δ
⁢

T

RxSRS
,
p

A

.

Since P_CMAX,f,c,p(i) was already reduced by ΔT_RxSRS,p(assuming the maximum configured power is equal to its lower bound) the reduction of P_CMAX,f,c,p(i) by

Δ
⁢

T

RxSRS
,
p

A

without compensation by the power amplifier has the effect of reducing the maximum configured power by

2
·
Δ

⁢

T
RxSRS
A

.

Unless the SRS implementation loss

Δ
⁢

T

RxSRS
,
p

A

is compensated oy ine UL 104, the total reduction in maximum configured power will be

2
·
Δ

⁢

T
RxSRS
A

.

FIG. 5 illustrates an example 500 of power difference between SRS ports versus power control with compensation in accordance with aspects of the present disclosure. The example 500 illustrates power difference between SRS ports vs. power control with compensation of

Δ
⁢

T
RxSRS
A

.

In the example 500, the SRS output power is shown for SRS ports j and k as a function of the power control setting P_SRS,b,f,c(i, q_s, l, p) for the case that the SRS power relaxations are compensated by the UE 104. In the example 500, P_CMAX,f,c,j(i) and P_CMAX,f,c,k(i) denote the maximum configured power for SRS ports j and k, respectively, and

Δ
⁢

T

RxSRS
,
j

A

⁢

and
⁢

Δ
⁢

T

RxSRS
,
k

A

denote the actual SRS power relaxations. From the example 500, it can be seen that there is no difference in the output power for the two SRS ports unless the power control setting is greater than PC_MAX,f,c,j(i). In this region, the output power for the k-th SRS port exceeds the power for the j-th port by the difference P_SRS,b,f,c(i, q_s, l)−P_CMAX,f,c,j(i). It can also be noted that the difference in maximum power for the two SRS ports is given by

Δ
⁢

T

RxSRS
,
j

A

-

Δ
⁢

T

RxSRS
,
k

A

.

FIG. 6 illustrates an example of a UE 600 in accordance with aspects of the present disclosure. The UE 600 may include a processor 602, a memory 604, a controller 606, and a transceiver 608. The processor 602, the memory 604, the controller 606, or the transceiver 608, or various combinations thereof or various components thereof may be examples of means for performing various aspects of the present disclosure as described herein. These components may be coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces.

The processor 602, the memory 604, the controller 606, or the transceiver 608, or various combinations or components thereof may be implemented in hardware (e.g., circuitry). The hardware may include a processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or other programmable logic device, or any combination thereof configured as or otherwise supporting a means for performing the functions described in the present disclosure.

The processor 602 may include an intelligent hardware device (e.g., a general-purpose processor, a DSP, a CPU, an ASIC, an FPGA, or any combination thereof). In some implementations, the processor 602 may be configured to operate the memory 604. In some other implementations, the memory 604 may be integrated into the processor 602. The processor 602 may be configured to execute computer-readable instructions stored in the memory 604 to cause the UE 600 to perform various functions of the present disclosure.

The memory 604 may include volatile or non-volatile memory. The memory 604 may store computer-readable, computer-executable code including instructions when executed by the processor 602 cause the UE 600 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such as the memory 604 or another type of memory. Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that may be accessed by a general-purpose or special-purpose computer.

In some implementations, the processor 602 and the memory 604 coupled with the processor 602 may be configured to cause the UE 600 to perform one or more of the functions described herein (e.g., executing, by the processor 602, instructions stored in the memory 604). For example, the processor 602 may support wireless communication at the UE 600 in accordance with examples as disclosed herein. The UE 600 may be configured to or operable to support a means for transmitting an indication of differences in insertion losses between a reference SRS port and each of one or more additional SRS ports; and transmitting a power headroom report for less than all SRS ports in a set of SRS ports that include the reference SRS port and the one or more additional SRS ports.

Additionally, the UE 600 may be configured to support any one or combination of where the reference SRS port comprises an SRS port of the UE having a smallest insertion loss; transmitting the power headroom report for one SRS port of the set of SRS ports having a smallest insertion loss; where the power headroom report includes a configured maximum power for the SRS port having the smallest insertion loss; where the indication of differences in insertion losses comprises differences in insertion losses between the reference SRS port and each of the one or more additional ports; where the indication of differences in insertion losses comprises differences in configured maximum power values between the reference SRS port and each of the one or more additional ports; transmitting an identity of the SRS reference port; transmitting, in response to a change in SRS port mappings, an updated indication of differences in insertion losses between the reference SRS port and each of one or more additional SRS ports.

Additionally, or alternatively, the UE 600 may support at least one memory (e.g., the memory 604) and at least one processor (e.g., the processor 602) coupled with the at least one memory and configured to cause the UE to: transmit an indication of differences in insertion losses between a reference SRS port and each of one or more additional SRS ports; transmit a power headroom report for less than all SRS ports in a set of SRS ports that include the reference SRS port and the one or more additional SRS ports.

Additionally, the UE 600 may be configured to support any one or combination of the at least one processor is configured to where the reference SRS port comprises an SRS port of the UE having a smallest insertion loss; transmit the power headroom report for one SRS port of the set of SRS ports having a smallest insertion loss; where the power headroom report includes a configured maximum power for the SRS port having the smallest insertion loss; where the indication of differences in insertion losses comprises differences in insertion losses between the reference SRS port and each of the one or more additional ports; where the indication of differences in insertion losses comprises differences in configured maximum power values between the reference SRS port and each of the one or more additional ports; transmit an identity of the SRS reference port; transmit, in response to a change in SRS port mappings, an updated indication of differences in insertion losses between the reference SRS port and each of one or more additional SRS ports.

The controller 606 may manage input and output signals for the UE 600. The controller 606 may also manage peripherals not integrated into the UE 600. In some implementations, the controller 606 may utilize an operating system such as iOS®, ANDROID®, WINDOWS®, or other operating systems. In some implementations, the controller 606 may be implemented as part of the processor 602.

In some implementations, the UE 600 may include at least one transceiver 608. In some other implementations, the UE 600 may have more than one transceiver 608. The transceiver 608 may represent a wireless transceiver. The transceiver 608 may include one or more receiver chains 610, one or more transmitter chains 612, or a combination thereof.

A receiver chain 610 may be configured to receive signals (e.g., control information, data, packets) over a wireless medium. For example, the receiver chain 610 may include one or more antennas to receive a signal over the air or wireless medium. The receiver chain 610 may include at least one amplifier (e.g., a low-noise amplifier (LNA)) configured to amplify the received signal. The receiver chain 610 may include at least one demodulator configured to demodulate the receive signal and obtain the transmitted data by reversing the modulation technique applied during transmission of the signal. The receiver chain 610 may include at least one decoder for decoding the demodulated signal to receive the transmitted data.

A transmitter chain 612 may be configured to generate and transmit signals (e.g., control information, data, packets). The transmitter chain 612 may include at least one modulator for modulating data onto a carrier signal, preparing the signal for transmission over a wireless medium. The at least one modulator may be configured to support one or more techniques such as amplitude modulation (AM), frequency modulation (FM), or digital modulation schemes like phase-shift keying (PSK) or quadrature amplitude modulation (QAM). The transmitter chain 612 may also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level suitable for transmission over the wireless medium. The transmitter chain 612 may also include one or more antennas for transmitting the amplified signal into the air or wireless medium.

FIG. 7 illustrates an example of a processor 700 in accordance with aspects of the present disclosure. The processor 700 may be an example of a processor configured to perform various operations in accordance with examples as described herein. The processor 700 may include a controller 702 configured to perform various operations in accordance with examples as described herein. The processor 700 may optionally include at least one memory 704, which may be, for example, an L1/L2/L3 cache. Additionally, or alternatively, the processor 700 may optionally include one or more arithmetic-logic units (ALUs) 706. One or more of these components may be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses).

The processor 700 may be a processor chipset and include a protocol stack (e.g., a software stack) executed by the processor chipset to perform various operations (e.g., receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) in accordance with examples as described herein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the processor chipset (e.g., the processor 700) or other memory (e.g., random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and others).

The controller 702 may be configured to manage and coordinate various operations (e.g., signaling, receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) of the processor 700 to cause the processor 700 to support various operations in accordance with examples as described herein. For example, the controller 702 may operate as a control unit of the processor 700, generating control signals that manage the operation of various components of the processor 700. These control signals include enabling or disabling functional units, selecting data paths, initiating memory access, and coordinating timing of operations.

The controller 702 may be configured to fetch (e.g., obtain, retrieve, receive) instructions from the memory 704 and determine subsequent instruction(s) to be executed to cause the processor 700 to support various operations in accordance with examples as described herein. The controller 702 may be configured to track memory addresses of instructions associated with the memory 704. The controller 702 may be configured to decode instructions to determine the operation to be performed and the operands involved. For example, the controller 702 may be configured to interpret the instruction and determine control signals to be output to other components of the processor 700 to cause the processor 700 to support various operations in accordance with examples as described herein. Additionally, or alternatively, the controller 702 may be configured to manage flow of data within the processor 700. The controller 702 may be configured to control transfer of data between registers, ALUs 706, and other functional units of the processor 700.

The memory 704 may include one or more caches (e.g., memory local to or included in the processor 700 or other memory, such as RAM, ROM, DRAM, SDRAM, SRAM, MRAM, flash memory, etc. In some implementations, the memory 704 may reside within or on a processor chipset (e.g., local to the processor 700). In some other implementations, the memory 704 may reside external to the processor chipset (e.g., remote to the processor 700).

The memory 704 may store computer-readable, computer-executable code including instructions that, when executed by the processor 700, cause the processor 700 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such as system memory or another type of memory. The controller 702 and/or the processor 700 may be configured to execute computer-readable instructions stored in the memory 704 to cause the processor 700 to perform various functions. For example, the processor 700 and/or the controller 702 may be coupled with or to the memory 704, the processor 700, and the controller 702, and may be configured to perform various functions described herein. In some examples, the processor 700 may include multiple processors and the memory 704 may include multiple memories. One or more of the multiple processors may be coupled with one or more of the multiple memories, which may, individually or collectively, be configured to perform various functions herein.

The one or more ALUs 706 may be configured to support various operations in accordance with examples as described herein. In some implementations, the one or more ALUs 706 may reside within or on a processor chipset (e.g., the processor 700). In some other implementations, the one or more ALUs 706 may reside external to the processor chipset (e.g., the processor 700). One or more ALUs 706 may perform one or more computations such as addition, subtraction, multiplication, and division on data. For example, one or more ALUs 706 may receive input operands and an operation code, which determines an operation to be executed. One or more ALUs 706 may be configured with a variety of logical and arithmetic circuits, including adders, subtractors, shifters, and logic gates, to process and manipulate the data according to the operation. Additionally, or alternatively, the one or more ALUs 706 may support logical operations such as AND, OR, exclusive-OR (XOR), not-OR (NOR), and not-AND (NAND), enabling the one or more ALUs 706 to handle conditional operations, comparisons, and bitwise operations.

The processor 700 may support wireless communication in accordance with examples as disclosed herein. The processor 700 may be configured to or operable to support at least one controller (e.g., the controller 702) coupled with at least one memory (e.g., the memory 704) and configured to cause the processor to: transmit an indication of differences in insertion losses between a reference SRS port and each of one or more additional SRS ports; transmit a power headroom report for less than all SRS ports in a set of SRS ports that include the reference SRS port and the one or more additional SRS ports.

Additionally, the processor 700 may be configured to or operable to support any one or combination of the at least one controller is configured to cause the processor to where the reference SRS port comprises an SRS port, of a UE that includes the processor, having a smallest insertion loss; transmit the power headroom report for one SRS port of the set of SRS ports having a smallest insertion loss; where the power headroom report includes a configured maximum power for the SRS port having the smallest insertion loss; where the indication of differences in insertion losses comprises at least one of differences in insertion losses between the reference SRS port and each of the one or more additional ports, or differences in insertion losses comprises differences in configured maximum power values between the reference SRS port and each of the one or more additional ports; where the at least one controller is further configured to cause the processor to transmit an identity of the SRS reference port; transmit, in response to a change in SRS port mappings, an updated indication of differences in insertion losses between the reference SRS port and each of one or more additional SRS ports.

FIG. 8 illustrates an example of a NE 800 in accordance with aspects of the present disclosure. The NE 800 may include a processor 802, a memory 804, a controller 806, and a transceiver 808. The processor 802, the memory 804, the controller 806, or the transceiver 808, or various combinations thereof or various components thereof may be examples of means for performing various aspects of the present disclosure as described herein. These components may be coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces.