To reduce a FIT rate of a system caused by packaging failures, a memory device may use a control signal to indicate when a bus that connects the memory device and a host device is in an idle state (e.g., a floating state) or when the bus is in an active state. Thus, a host device may, in some examples, discard the data after determining that a data signal is obtained from an idle bus (e.g., floating bus). In some examples, a host device may transmit a request for data to a memory device. In some examples, the memory device may fail to receive the request—e.g., if the memory device is in an idle state. In other examples, the memory device may receive, but fail to decode, the request—e.g., if a package used for the memory device is defective. In both cases, the memory device may not one or more operations used to retrieve and output the requested data to the host device, and the bus may enter or remain in an idle state (e.g., a floating state). Accordingly, an indeterminate signal (e.g., random, unknown, invalid, erroneous), such as an indeterminate data signal, may develop on the data lines of the bus—e.g., as the voltage of the data line trends toward a voltage of a voltage source or voltage sink coupled with the data lines. Also, a voltage of a control line of the bus used to convey a bus state indication and, in some examples, one or more error signals may develop on the control line of the bus—e.g., the voltage of the control line may be at or near a voltage of a voltage source or voltage sink coupled with the control line. The host device may sample the control line to obtain the bus state indication, which may have a first voltage indicating the bus is in the idle state. Thus, the host device may refrain from decoding the indeterminate data signal and avoid further disadvantages that may otherwise occur as a result of decoding the indeterminate data signal.

FIG. 2 illustrates an example of a memory die 200 that supports techniques for detecting a state of a bus in accordance with examples as disclosed herein. The memory die 200 may be an example of the memory dies 160 described with reference to FIG. 1. In some examples, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory die 200 may include one or more memory cells 205 that may each be programmable to store different logic states (e.g., programmed to one of a set of two or more possible states). For example, a memory cell 205 may be operable to store one bit of information at a time (e.g., a logic 0 or a logic 1). In some examples, a memory cell 205 (e.g., a multi-level memory cell) may be operable to store more than one bit of information at a time (e.g., a logic 00, logic 01, logic 10, a logic 11). In some examples, the memory cells 205 may be arranged in an array, such as a memory array 170 described with reference to FIG. 1.

A memory cell 205 may store a charge representative of the programmable states in a capacitor. DRAM architectures may include a capacitor that includes a dielectric material to store a charge representative of the programmable state. In other memory architectures, other storage devices and components are possible. For example, nonlinear dielectric materials may be employed. The memory cell 205 may include a logic storage component, such as capacitor 230, and a switching component 235. The capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. A node of the capacitor 230 may be coupled with a voltage source 240, which may be the cell plate reference voltage, such as Vpl, or may be ground, such as Vss.

The memory die 200 may include one or more access lines (e.g., one or more word lines 210 and one or more digit lines 215) arranged in a pattern, such as a grid-like pattern. An access line may be a conductive line coupled with a memory cell 205 and may be used to perform access operations on the memory cell 205. In some examples, word lines 210 may be referred to as row lines. In some examples, digit lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, or bit lines, or their analogues, are interchangeable without loss of understanding or operation. Memory cells 205 may be positioned at intersections of the word lines 210 and the digit lines 215.

Operations such as reading and writing may be performed on the memory cells 205 by activating or selecting access lines such as one or more of a word line 210 or a digit line 215. By biasing a word line 210 and a digit line 215 (e.g., applying a voltage to the word line 210 or the digit line 215), a single memory cell 205 may be accessed at their intersection. The intersection of a word line 210 and a digit line 215 in either a two-dimensional or three-dimensional configuration may be referred to as an address of a memory cell 205.

Accessing the memory cells 205 may be controlled through a row decoder 220 or a column decoder 225. For example, a row decoder 220 may receive a row address from the local memory controller 260 and activate a word line 210 based on the received row address. A column decoder 225 may receive a column address from the local memory controller 260 and may activate a digit line 215 based on the received column address.

Selecting or deselecting the memory cell 205 may be accomplished by activating or deactivating the switching component 235 using a word line 210. The capacitor 230 may be coupled with the digit line 215 using the switching component 235. For example, the capacitor 230 may be isolated from digit line 215 when the switching component 235 is deactivated, and the capacitor 230 may be coupled with digit line 215 when the switching component 235 is activated.

The sense component 245 may be operable to detect a state (e.g., a charge) stored on the capacitor 230 of the memory cell 205 and determine a logic state of the memory cell 205 based on the stored state. The sense component 245 may include one or more sense amplifiers to amplify or otherwise convert a signal resulting from accessing the memory cell 205. The sense component 245 may compare a signal detected from the memory cell 205 to a reference 250 (e.g., a reference voltage). The detected logic state of the memory cell 205 may be provided as an output of the sense component 245 (e.g., to an input/output 255), and may indicate the detected logic state to another component of a memory device that includes the memory die 200.

The local memory controller 260 may control the accessing of memory cells 205 through the various components (e.g., row decoder 220, column decoder 225, sense component 245). The local memory controller 260 may be an example of the local memory controller 165 described with reference to FIG. 1. In some examples, one or more of the row decoder 220, column decoder 225, and sense component 245 may be co-located with the local memory controller 260. The local memory controller 260 may be operable to receive one or more of commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with a host device 105, another controller associated with the memory die 200), translate the commands or the data (or both) into information that can be used by the memory die 200, perform one or more operations on the memory die 200, and communicate data from the memory die 200 to a host device 105 based on performing the one or more operations. The local memory controller 260 may generate row signals and column address signals to activate the target word line 210 and the target digit line 215. The local memory controller 260 may also generate and control various voltages or currents used during the operation of the memory die 200. In general, the amplitude, the shape, or the duration of an applied voltage or current discussed herein may be varied and may be different for the various operations discussed in operating the memory die 200.

The local memory controller 260 may be operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, access operations may be performed by or otherwise coordinated by the local memory controller 260 in response to various access commands (e.g., from a host device 105). The local memory controller 260 may be operable to perform other access operations not listed here or other operations related to the operating of the memory die 200 that are not directly related to accessing the memory cells 205.

The local memory controller 260 may be operable to perform a read operation (e.g., a sense operation) on one or more memory cells 205 of the memory die 200. During a read operation, the logic state stored in a memory cell 205 of the memory die 200 may be determined. The local memory controller 260 may identify a target memory cell 205 on which to perform the read operation. The local memory controller 260 may identify a target word line 210 and a target digit line 215 coupled with the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 260 may activate the target word line 210 and the target digit line 215 (e.g., applying a voltage to the word line 210 or digit line 215) to access the target memory cell 205. The target memory cell 205 may transfer a signal to the sense component 245 in response to biasing the access lines. The sense component 245 may amplify the signal. The local memory controller 260 may activate the sense component 245 (e.g., latch the sense component) and thereby compare the signal received from the memory cell 205 to the reference 250. Based on that comparison, the sense component 245 may determine a logic state that is stored on the memory cell 205.

A package may be used to contain and provide access to and from a memory device, such as the memory device 110 in FIG. 1, which may include a memory die 200. The package may include pins that give access to and from components within the memory device 110, such as the memory die 200. For example, a memory controller (e.g., a device memory controller 155 in FIG. 1, a local memory controller 165 in FIG. 1, the local memory controller 260) in the memory device may be coupled with a set of DQ pins that allow data to be inputted to or outputted from the memory controller. The package may also include a read data strobe (RDQS) pin that is used by the memory controller to output a clock signal (which may also be referred to as an RDQS signal) for sampling a data signal on the DQ pins—e.g., when the memory device is configured to operate using a frequency that falls within a range of frequencies. Also, the package may include a data mask inversion (DMI) pin that is used to output error management information—e.g., information for detecting and/or correcting errors.

The pins of the package may also be coupled with a bus (or transmission bus) that includes lines (or transmission lines). The bus may be used to provide a communicative path between the memory device and a host device (e.g., host device 105 of FIG. 1). The transmission lines of the bus may include data lines and control lines. In some examples, the DQ pins may be coupled with data lines of the bus, the RDQS pin may be coupled with a control (or clock) line of the bus, and the DMI pin may be coupled with a control line of the bus. In some examples, the pins of the package and/or the transmission lines of the bus may be terminated (e.g., weakly) to a voltage source or voltage sink (e.g., a ground reference). Thus, when the bus is not being used (e.g., is in an idle, inactive, or floating state), the voltage of the pins and transmission lines may trend toward the voltage of the voltage source or voltage sink. Alternatively, when the bus is being used (e.g., is in an active state) by either the memory device or the host device, the voltage of the transmission lines may be driven by the memory device or the host device.

A failure rate for a system (e.g., system 100) that includes a host device and memory device may be determined by testing multiple similarly-constructed systems for a time interval and determining a quantity of failures that occur per aggregate hour—e.g., if one hundred systems are tested for one hundred hours, the failure rate may determine a quantity of failures that occur in around 10,000 hours. A failure may include a scenario where a host device receives invalid data from a memory device without determining that the data is invalid—in such cases, the host device may use the invalid data to perform an operation. In some examples, the testing may yield a quantity of failures expected to occur in one billion hours of operation for the system, which may also be referred to as a FIT rate. The system may be configured to have an acceptable FIT rate—e.g., a FIT rate that is below a threshold. In some examples, the threshold is set based on the ramifications of a failure. For example, the more severe an injury that may result from a failure, the stricter the FIT rate may be—e.g., the threshold value may be lower (e.g., less than 4 FITs) if the system is deployed in an application used to operate an automobile (e.g., in an autonomous vehicle).

A system may employ data-reliability techniques to achieve an acceptable FIT rate. For example, the system may store parity bits with data, where the parity bits may be used to identify and/or correct errors in the data when the data is output to a host device. In some examples, the parity bits may be used to generate one or more syndrome bits that indicate which bits in a data packet are defective. In some examples, a memory device may include a syndrome check circuit 265 that generates a syndrome check signal that enables a host device to quickly identify whether received data includes one or more errors. The syndrome check circuit 265 may check syndrome bits associated with a set of data and generate an indication (which may be referred to as the syndrome check signal) for a host device that indicates whether there is in an error in the data—e.g., if the syndrome bits include any non-zero syndrome bits. The syndrome check circuit 265 may also be configured to indicate additional information such as a quantity of errors, phantom errors, a type of error, and the like. In some examples, the memory device also signals the syndrome bits used to generate the syndrome check signal to the host device—the host device may use the syndrome bits to detect and/or correct one or more errors in the received data. A host device may use the information to avoid failures that would otherwise contribute to the FIT rate.

In some examples, the memory die 200 may also include a master error circuit to improve a reliability of data transfer. The master error circuit may enable a memory device to identify errors caused by the memory controller. For example, the master error circuit may identify errors that occur when a memory device writes different data to memory than what is received or outputs different data to a host device than what is stored in memory—e.g., by accessing an incorrect row when writing to or reading from memory. In some examples, the syndrome check signal generated by the syndrome check circuit 265, a syndrome bit signal including the syndrome bits, the master error status signal generated by the master error circuit, or any combination thereof, may be outputted on the DMI pin. The memory device may include a multiplexer that may be used to switch from the syndrome check signal to the master error status signal to the syndrome bit signal. In some examples, during a first unit interval of a read operation, no signal is outputted on the DMI pin; during a next set of unit intervals of the read operation, the syndrome check signal is outputted on the DMI pin; during a following set of unit intervals of the read operation, the master error status signal is outputted on the DMI pin; and during a subsequent set of unit intervals of the read operation, the syndrome bit signal is outputted on the DMI pin.

In some examples, the unit intervals are determined based on a read clock signal outputted on the RDQS pin, where each unit interval corresponds to the duration between a falling edge of the read clock and a subsequent rising edge of the read clock. The read clock may be aligned with the outputting of data packets on the DQ pins. In some examples, the read clock is output by the memory device when the memory device is operated within a particular frequency range. When operating outside of the frequency range, the memory device may not output the read clock signal. In such cases, the unit intervals may be determined based on a write clock signal generated at the host device. In some examples, the RDQS signal may be generated using differential signals that correspond to a write clock signal received from the host device—e.g., an inverted and non-inverted version of the write clock signal (which may be referred to as a differential strobe technique). In other examples, the RDQS signal may be generated using the non-inverted version of a write clock signal received from the host device (which may be referred to as a single-ended strobe technique).

A failure rate of a system may be affected by a type of packaging used for a memory device—e.g., a failure rate may increase as a footprint of the packaging decreases or a density of the packaging is increased, or both, and vice versa. In some examples, changing a package used to contain a memory device may cause the FIT rate for a system that previously satisfied a FIT rate threshold when the memory device was packaged in a prior package to exceed the FIT rate threshold when the memory device is packaged in a current package—e.g., due to an increased quantity of mechanical failures that may occur, such as soldering failures or shorting scenarios. For example, packaging a memory device in a fine-pitch ball grid array may cause the FIT rate for the system to increase (e.g., to 25.5 FITs) relative to, for example, packaging the memory device in a ball grid array having a larger pitch (e.g., from 2.4 FITs).

In some examples, packaging errors that cause a bus between the memory device and host device to improperly enter or remain in a floating state significantly contribute to the increased FIT rate. In such cases, the host device may be unable to determine whether a signal on the bus is a data signal driven by the memory device (which may also be referred to as a valid data signal) or a random data signal that results on the bus when the bus is in a floating state (which may also be referred to as an invalid data signal). Also, in some examples, the host device may determine that a random data signal on the bus is a valid data signal and use invalid data obtained from the random data signal to perform an operation, increasing a FIT rate for the system.

To reduce a FIT rate of a system caused by packaging failures, a memory device may use a signal, such as a control signal, to indicate when a bus that connects the memory device and a host device is in an idle state (e.g., a floating state) or when the bus is in an active state. The signal, such as the control signal, may be referred to as a valid read operation flag. Thus, a host device may, in some examples, discard the data after determining that a data signal is obtained from an idle bus (e.g., a floating bus).

In some examples, a host device may transmit a request for data to a memory device. In some examples, the memory device may fail to receive the request—e.g., if the memory device is in an idle state. In other examples, the memory device may receive, but fail to decode, the request—e.g., if a package used for the memory device is defective. In both cases, the memory device may not execute a sequence of operations used to retrieve and output the requested data to the host device, and the bus may enter or remain in an idle state (e.g., a floating state). Accordingly, an indeterminate signal (e.g., random, unknown, invalid, erroneous), such as an indeterminate data signal, may develop on the data lines of the bus—e.g., as the voltage of the data line trends toward a voltage of a voltage source or voltage sink coupled with the data lines. Also, a voltage of a control line of the bus used to convey a bus state indication (e.g., a valid read operation flag) and, in some examples, one or more error signals may develop on the control line of the bus—e.g., the voltage of the control line may be at or near a voltage of a voltage source or voltage sink coupled with the control line. The host device may sample the control line to obtain the bus state indication, which may have a first voltage indicating the bus is in the idle state. Thus, the host device may refrain from decoding the indeterminate data signal.

Alternatively, if the memory device receives and decodes the request, the memory device may output a data signal (which may be referred to as a valid data signal) and bus state indication signal on the bus, which may be in an active state. In such cases, the host device may sample the control line to obtain the bus state indication, which may have a second voltage indicating the bus is in the active state. Thus, the host device may decode the data signal obtained from bus. By indicating the state of the bus, the host device may avoid errors that may occur if the host were to otherwise use indeterminate data obtained from a floating bus, reducing a FIT rate for a memory system.

In some examples, local memory controller 260 may include drive condition validator 275. Drive condition validator 275 may be used to determine when a bus is being driven by a memory device. Drive condition validator 275 may generate a validation indicator based on an RDQS signal generated by the memory device—e.g., drive condition validator 275 may indicate the bus is being driven after detecting consecutive rising and falling edges for an RDQS signal. Local memory controller 260 may transmit the output of drive condition validator 275 over the bus. In some examples, the output signal of drive condition validator 275 is consistent with the valid read operation flag output over the bus.

FIG. 3 illustrates an example of a timing diagram that supports techniques for detecting a state of a bus in accordance with examples as disclosed herein.

Timing diagram 300 depicts an exchange of signaling between a host device and a memory device, which may be example of a host device and memory device described in FIGS. 1 and 2. Timing diagram 300 may depict command signals 310 that may be transmitted over one or more command lines of a bus, clock signals 315 that may be transmitted over a clock line of the bus, data signals 320 that may be transmitted over one or more data lines of the bus, and error signals 330 that may be transmitted a control line of the bus.

In some examples, timing diagram 300 depicts an exemplary read operation between a host device and a memory device. To initiate the read operation, the host device may transmit, to the memory device via command lines, one or more read commands 305 requesting data stored in a memory array. After successfully receiving and/or decoding read commands 305, the memory device may initiate a sequence of operations for outputting the data requested by read commands 305. In such cases, the memory device may retrieve data and error management information (e.g., parity bits) from one or more memory locations addressed by the one or more read commands.

The memory device may use the error management information to determine whether there are one or more errors in the data and to generate error management signaling (e.g., a syndrome bit signal, a syndrome check signal) that may be used to detect and/or correct the one or more errors in the data. In some examples, the memory device generates the syndrome check signal based on processing (e.g., OR'ing) the syndrome bits together, where one or more syndrome check bits having a zero logic value (e.g., “0”, “00”, “000”) may result if no errors are identified in the data. And one or more syndrome check bits having a non-zero logic value (e.g., “1”, “001”, “010”, “111”) may result if one or more errors are identified in the data. In some examples, the generated syndrome check signal may have a consistently low voltage if the syndrome check bits indicate no errors in the data—e.g., if the syndrome check bits have a zero logic value. Or the generated syndrome check signal may have a consistently or intermittently high voltage if the syndrome check bits indicate one or more errors in the data—e.g., if the syndrome check bits have a non-zero logic value.

The memory device may output data signals 320 over data lines of the bus. Data signals 320 may include data stored in a memory array and requested by a host device. The memory device may also output clock signal 315 over a clock line of the bus, where clock signal 315 may be used to synchronize a sampling of the data lines at the host device with an output of subsets of the data from the memory device in data signals 320. In some examples, a new subset of the requested data is output on a rising edge of the read clock and a falling edge of the read clock. Each rising and falling edge of the read clock may be associated with a unit interval 323 of the data output operation. In some examples, the memory device only outputs clock signal 315 after being configured to operate within a frequency range (e.g., a high frequency range).

Also, the memory device may output one or more error signals 330 over the control line of the bus. Error signals 330 may be used to indicate one or more errors associated with corresponding data signals. In some examples, the memory device may transmit valid read operation flag 333 during the first unit interval of the data output operation. Valid read operation flag 333 may indicate whether the bus is in an idle or active state. During a valid read operation, valid read operation flag 333 may have a logic value (e.g., logic value 1) that indicates the bus is in an active state. When valid read operation flag 333 has the logic value that indicates the bus is in an active state, valid read operation flag 333 may also have a second voltage (e.g., a high voltage). If valid read operation flag 333 has a different logic value (e.g., logic value 0), valid read operation flag 333 may indicate that the bus is in an idle state. When valid read operation flag 333 has the logic value that indicates the bus is in an idle state, for example, valid read operation flag 333 may also have a first voltage (e.g., a low voltage) based on a voltage of the control line being or trending toward the first voltage when the bus is in the idle state.

In a second unit interval (e.g., a next unit interval), the memory device may output syndrome check signal 335 over the control line. A voltage of syndrome check signal 335 may indicate whether data signal 325 includes no errors or one or more errors.

Additionally or alternatively, the memory device may output master error status signal 340 over the control line of the bus. Master error status signal 340 may be transmitted in a unit interval that occurs after an end of syndrome check signal 335 (e.g., in the fifth unit interval) and may be used to indicate whether an error associated with the memory controller occurred. After transmitting master error status signal 340, the memory device may output syndrome bit signal 345, which may be used by the host device to detect, correct, and/or discard (if the errors are uncorrectable) data obtained in data signal 325. In some examples, the memory device switches between valid read operation flag 333, syndrome check signal 335, master error status signal 340, and syndrome bit signal 345 by modifying the output of a multiplexer that receives the four signals and is coupled with the control line used to convey the error management signals. That is, the multiplexer may pass one of the valid read operation flag 333, syndrome check signal 335, master error status signal 340, and syndrome bit signal 345 to the control line based on one or more signals inputted to the multiplexer to select one of the signals.

In some examples, in a prior or subsequent read operation, the host device may transmit another read command to the memory device, but the memory device may fail to receive or decode the read command. In some examples, the memory device may fail to receive the read command if the memory device is in an idle state when the read command is sent from the memory device. In some examples, the memory device may fail to decode the read command if a package used to contain the memory device is defective—e.g., if one of the connections used to convey the read command is broken or shorted. In both cases, the memory device may not identify the read command and, thus, may not initiate a sequence of operations for outputting the data requested by the read command. Accordingly, the bus may enter or remain in an idle state (e.g., floating state). In some examples, if the bus is already in a floating state, which may an example of an idle state, all or a majority of the data and control lines may be at or near a first voltage (e.g., a ground reference if the bus is terminated (e.g., weakly) to a ground reference). If the bus is entering the floating state, the voltages of the data and control lines may be indeterminate as the voltages of the data and control lines trend toward the ground reference. In some examples, the control line may be more strongly terminated to the ground reference to increase a speed at which the voltage of the control line reaches the ground reference when the bus is in a floating state. In either case, invalid data may develop on data lines of the bus. In some examples, the voltage of the clock line may also be indeterminate as the voltage of the clock line trends toward the ground reference.

After transmitting the read command and after a determined interval elapses, the host device may attempt to read a purported data signal (e.g., an indeterminate signal such as an indeterminate data signal) that has developed on the data lines and the purported error signals that have developed on the control line use to indicate error management information—e.g., in accordance with an write clock signal that is internal to the host device. In some examples, the host device may decode the purported data (which includes invalid data) and read a purported valid read operation flag that develops on the control line during an interval for communicating the valid read operation flag. The purported valid read operation flag may have a voltage that is at or near a ground reference—e.g., based on the control line being terminated (e.g., weakly) to a ground reference. The host device may treat the purported valid read operation flag as a true valid read operation flag, and thus, the host device may determine that the data obtained from the purported data signal has been obtained from an idle bus—e.g., based on determining that the purported valid read operation flag has a low voltage (throughout or during one of the corresponding unit intervals). After determining the purported data signal is obtained from an idle bus, the host device may discard the data signal. In some examples, the host device may refrain from decoding the data signal, reducing a processing load for the host device.

FIG. 4 illustrates an example of a process flow 400 that supports techniques for detecting a state of a bus in accordance with examples as disclosed herein.

Process flow 400 may be performed by host device 405 and memory device 410, which may be examples of a host device or memory device described above with reference to FIGS. 1 and 2. In some examples, process flow 400 illustrates an exemplary sequence of operations performed to detect a state of a bus. For example, process flow 400 depicts operations for indicating a data signal includes one or more errors when a host device samples the data signal from a floating bus.

It is understood that one or more of the operations described in process flow 400 may be performed earlier or later in the process, omitted, replaced, supplemented, or performed in combination with another operation. Also, additional operations described herein that are not included in process flow 400 may be included.

At 415, host device 405 may transmit one or more access commands to memory device 410. The one or more access commands may include one or more read commands, one or more write commands, one or more other commands, or a combination thereof. In some examples, the one or more access commands include one or more read commands for requesting data stored in a memory array of memory device 410 and one or more memory addresses targeted by the one or more read commands.

At 420, memory device 410 may receive the one or more access commands. However, in some examples, memory device 410 may not receive the one or more access commands—e.g., if the memory device 410 is in an idle state (e.g., a floating state) when the one or more access commands are transmitted.

At 425, memory device 410 may decode the one or more access commands based at least in part on successfully receiving the one or more access commands. In some examples, memory device 410 may fail to successfully decode the one or more access commands—e.g., if a connection (e.g., a wire, trace, pin) within a package that contains the memory device and connects the command lines to the memory device is broken or shorted, or otherwise defective. If memory device 410 fails to receive and, in some examples, decode the one or more access commands, the memory device 410 may not perform a series of operations for executing the one or more access commands and the bus may enter or remain in an idle state (e.g., a floating state).

In some examples, memory device 410 generates a drive validation signal that indicates the bus is in an idle state based on failing to receive or decode the one or more access commands. The drive validation signal may be based on an RDQS signal or another signal associated with the bus being driven by memory device 410. The memory device may process (e.g., apply) the drive validation signal to logic that receives the drive validation signal and a syndrome check signal. In such cases, the logic may output a low voltage (based on the drive validation signal having the low voltage) and may be used to drive a control line (e.g., a DMI line) to the low voltage while the bus is in the idle state.

At 430, host device 405 may sample the bus as if the memory device had executed the one or more access commands transmitted from host device 405. In some examples, in one or more unit intervals, if not each unit interval, of multiple unit intervals of a read operation, host device 405 may sample the data lines of the bus and control lines of the bus. In some examples, host device 405 samples the data lines based on a write clock signal generated at host device 405. In some examples, host device 405 samples the data lines based on noise on one or multiple RDQS lines that cause host device 405 to determine that data has been transmitted. In some examples, host device 405 may determine a logic value for each sampled signal to obtain data and control information. When memory device 410 fails to receive and, in some examples, decode the one or more access commands, the bus may be in an idle state, and thus, the data signal on the bus may include invalid data. In some examples, the data signal includes multiple signals which may be at or near a ground reference. In other examples, a subset of the multiple signals may be at or near a ground reference and a subset of the multiple signals may be near a high signaling voltage.

At 435, host device 405 may decode a valid read operation flag. Decoding the valid read operation flag may include sampling a control line of the bus in an interval in which the valid read operation flag is expected to be transmitted from memory device 410. When memory device 410 fails to receive, and, in some examples, decode the one or more access commands, the bus may be in an idle state, and thus, the valid read operation signal on the bus may have a voltage associated with a floating state of the bus. In some examples, the valid read operation signal may have a voltage that is at or near a ground voltage—e.g., based on the control line being weakly terminated to a ground reference. As described in FIG. 3, the valid read operation signal may be generated so that, when a voltage of the valid read operation signal matches (or nearly matches) a voltage of the floating control line, the valid read operation signal indicates that the bus is in an idle state.

At 440, host device 405 may determine that the bus is in an idle state based on the valid read operation flag. For example, after determining that the valid read operation flag (or the purported valid read operation flag) has a voltage that is associated with a first logic value (e.g., logic value 0), host device 405 may determine that the bus is in the idle state.

At 445, host device 405 may discard the invalid data obtained from the data signal on the floating data bus. In some examples, host device 405 discards the invalid data based on determining that bus is in the idle state.

At 450, host device 405 may retransmit the one or more access commands for the data. In some examples, host device 405 retransmits the one or more access commands based on discarding the data obtained as a result of previously transmitting the one or more access commands.

At 455, memory device 410 may receive and decode the one or more access commands. In some examples, memory device 410 successfully receives and decodes the one or more access commands—e.g., if memory device 410 is no longer in an idle state or if a mechanical failure that prevented memory device 410 from decoding the one or more access commands the first time has resolved itself (e.g., temporarily).

At 460, memory device 410 may generate a valid read operation flag. In some examples, memory device 410 generate a valid read operation flag to have a high voltage that corresponds to a second logic value (e.g., a logic value 1) and indicates that the bus is in an active state—e.g., based on successfully decoding the one or more access commands. In some examples, memory device 410 generates the valid read operation flag based on an RDQS signal—e.g., by identifying when the RDQS signal is toggling. In some examples, memory device 410 generates the valid read operation flag based on other signals that are generated to support a read operation. In some examples, the valid read operation flag is generated based on a combination of signals used to support a read operation (e.g., including the RDQS signal). In such examples, multiple signals that indicate a state of the bus may be generated and combined (e.g., using an AND gate) to generate the valid read operation flag.

At 465, memory device 410 may transmit a data signal including the requested data and a control signal including the valid read operation flag to the host device 405. The data signal may be transmitted over multiple data lines (e.g., DQ lines), and the valid read operation signal may be transmitted over a control line (e.g., DMI line). In some examples, a syndrome check signal, master error signal and syndrome bits may also be transmitted over the control line. Memory device 410 may include a multiplexer that is used to pass the different signals to a signal driver that is coupled with the control line.

At 470, host device 405 may sample the bus as similarly described with reference to 430.

At 475, host device 405 may decode the valid read operation flag as similarly described with reference to 435. In some examples, host device 405 may determine that the bus is in an active state while data is obtained from a corresponding data signal on the bus—e.g., based on the valid read operation flag having a first logic value (e.g., logic value 1).

At 480, host device 405 may decode a syndrome check signal after decoding the valid read operation flag. In some examples, host device 405 may determine that the corresponding data includes no errors if the syndrome check signal has a high voltage (e.g., that represents a logic value 1). In other examples, host device 405 may determine that the corresponding data includes one or more errors if the syndrome check signal has a low voltage (e.g., that represents a logic value 0).

At 485, host device 405 may use the data obtained from the data signal transmitted over the bus by memory device 410. In some examples, host device 405 may use the data obtained from the bus after determining that the bus is active (from the valid read operation flag) and that the corresponding data includes no errors (from the syndrome check signal). In other examples, host device 405 may use the data obtained from the bus after performing an error detection/correction operation after determining that the bus is active (from the valid read operation flag) and that the corresponding data includes one or more errors (from the syndrome check signal). In such cases, host device 405 may use syndrome bits obtained from a syndrome bit signal on the control line to detect and correct errors in the data obtained from the data signal. In some examples, host device may discard the data obtained from the data signal—e.g., based on determining that the corresponding data includes an uncorrectable quantity of errors (e.g., if the syndrome bits indicate there are two or more errors in the data).

FIG. 5 shows a block diagram 500 of a memory device 520 that supports techniques for detecting a state of a bus in accordance with examples as disclosed herein. The memory device 520 may be an example of aspects of a memory device as described with reference to FIGS. 1 through 4. The memory device 520, or various components thereof, may be an example of means for performing various aspects of techniques for detecting a state of a bus as described herein. For example, the memory device 520 may include a command receiver 525, a transmitter 530, a bus state indication circuit 535, or any combination thereof. Each of these components may communicate, directly or indirectly, with one another (e.g., via one or more buses).

The command receiver 525 may be configured as or otherwise support a means for receiving, over a bus, a first request for data, the first request including an error, where a first signal of a first type including invalid data and a first signal of a second type both result on the bus based at least in part on the first request including the error, the first signal of the second type indicating that the bus is in an idle state. In some examples, the command receiver 525 may be configured as or otherwise support a means for receiving, over the bus, a second request for the data based at least in part on the first signal of the second type resulting on the bus. The transmitter 530 may be configured as or otherwise support a means for transmitting, over the bus based at least in part on successfully receiving the second request, a second signal of the first type including the data and a second signal of the second type including an indication that the bus is in an active state.

In some examples, the bus state indication circuit 535 may be configured as or otherwise support a means for generating the second signal of the second type based at least in part on successfully decoding the second request for the data, where transmitting the second signal of the second type is based at least in part on generating the second signal of the second type.

In some examples, transmitting the second signal of the first type includes transmitting a plurality of subsets of the data in a plurality of intervals, each subset of the data being transmitted in a respective interval of the plurality of intervals. In some examples, transmitting the second signal of the second type includes transmitting the second signal of the second type in an initial interval of the plurality of intervals.

In some examples, the transmitter 530 may be configured as or otherwise support a means for transmitting the second signal of the second type comprises transmitting over a control line of the bus in an initial interval of a data output operation, the method further comprising. In some examples, the transmitter 530 may be configured as or otherwise support a means for transmitting, over the control line in a second interval that directly follows the initial interval, a signal of a third type that indicates whether the second signal of the first type is associated with one or more errors.

In some examples, a first logic value for the first signal of the second type indicates that the bus is in the idle state and a second logic value for the first signal of the second type indicates that the bus is in the active state, the first signal of the second type that results on the bus has the first logic value, and the second signal of the second type that is transmitted over the bus has the second logic value.

FIG. 6 shows a block diagram 600 of a host device 620 that supports techniques for detecting a state of a bus in accordance with examples as disclosed herein. The host device 620 may be an example of aspects of a host device as described with reference to FIGS. 1 through 4. The host device 620, or various components thereof, may be an example of means for performing various aspects of techniques for detecting a state of a bus as described herein. For example, the host device 620 may include a receiver 625, a decoder 630, a data manager 635, a bus state determination circuit 640, a transmitter 645, or any combination thereof. Each of these components may communicate, directly or indirectly, with one another (e.g., via one or more buses).

The receiver 625 may be configured as or otherwise support a means for receiving, over a bus in an idle state, a signal of a first type including invalid data and a signal of a second type including an indication that the bus is in the idle state. The decoder 630 may be configured as or otherwise support a means for decoding the signal of the second type based at least in part on receiving the signal of the first type and the signal of the second type. The data manager 635 may be configured as or otherwise support a means for discarding the invalid data obtained from the signal of the first type based at least in part on determining, from decoding the signal of the second type, that the bus is in the idle state.

In some examples, the bus state determination circuit 640 may be configured as or otherwise support a means for determining that the signal of the second type has a first logic value based at least in part on decoding the signal of the second type. In some examples, the bus state determination circuit 640 may be configured as or otherwise support a means for determining that the bus is in the idle state based at least in part on the signal of the second type having the first logic value, where discarding the invalid data is based at least in part on determining that the bus is in the idle state.

In some examples, receiving the signal of the first type includes sampling one or more data lines of the bus during a plurality of intervals to receive subsets of the invalid data, each subset of the invalid data being received in a respective interval of the plurality of intervals. In some examples, receiving the signal of the second type includes sampling a control line of the bus during an initial interval of the plurality of intervals.

In some examples, the transmitter 645 may be configured as or otherwise support a means for transmitting, over the bus, a first request for data, where receiving the signal of the first type and the signal of the second type is based at least in part on transmitting the first request. In some examples, the transmitter 645 may be configured as or otherwise support a means for transmitting, over the bus, a second request for the data based at least in part on discarding the invalid data obtained from the signal of the first type.

In some examples, the receiver 625 may be configured as or otherwise support a means for receiving, while the bus is in an active state and after receiving the signal of the first type, a second signal of the first type including data and a second signal of the second type including a second indication that the bus is in the active state. In some examples, the decoder 630 may be configured as or otherwise support a means for decoding the second signal of the second type based at least in part on the receiving. In some examples, the decoder 630 may be configured as or otherwise support a means for decoding the second signal of the first type based at least in part on determining, from decoding the signal of the second type, that the bus is in the active state.

In some examples, the receiver 625 may be configured as or otherwise support a means for receiving, the second signal of the second type comprises receiving over a control line of the bus in an initial interval of a data input operation. In some examples the receiver 625 may be configured as or otherwise support a means for receiving, over the control line in a second interval of the data input operation that directly follows the initial interval, a signal of a third type that indicates whether the second signal of the first type is associated with one or more errors.

In some examples, a first logic value for the signal of the second type indicates that the bus is in the idle state and a second logic value for the signal of the second type indicates that the bus is in the active state, and the signal of the second type has the second logic value.

In some examples, a first logic value for the signal of the second type indicates that the bus is in the idle state and a second logic value for the signal of the second type indicates that the bus is in an active state, and the signal of the second type has the first logic value.

FIG. 7 shows a flowchart illustrating a method 700 that supports techniques for detecting a state of a bus in accordance with examples as disclosed herein. The operations of method 700 may be implemented by a memory device or its components as described herein. For example, the operations of method 700 may be performed by a memory device as described with reference to FIGS. 1 through 5. In some examples, a memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally, or alternatively, the memory device may perform aspects of the described functions using special-purpose hardware.

At 705, the method may include receiving, over a bus, a first request for data, the first request including an error, where a first signal of a first type including invalid data and a first signal of a second type both result on the bus based at least in part on the first request including the error, the first signal of the second type indicating that the bus is in an idle state. The operations of 705 may be performed in accordance with examples as disclosed herein and with reference to FIG. 5. In some examples, aspects of the operations of 705 may be performed by a command receiver 525 as described with reference to FIG. 5.

At 710, the method may include receiving, over the bus, a second request for the data based at least in part on the first signal of the second type resulting on the bus. The operations of 710 may be performed in accordance with examples as disclosed herein and with reference to FIG. 5. In some examples, aspects of the operations of 710 may be performed by a command receiver 525 as described with reference to FIG. 5.

At 715, the method may include transmitting, over the bus based at least in part on successfully receiving the second request, a second signal of the first type including the data and a second signal of the second type including an indication that the bus is in an active state. The operations of 715 may be performed in accordance with examples as disclosed herein and with reference to FIG. 5. In some examples, aspects of the operations of 715 may be performed by a transmitter 530 as described with reference to FIG. 5.

In some examples, an apparatus as described herein may perform a method or methods, such as the method 700. The apparatus may include, features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving, over a bus, a first request for data, the first request including an error, where a first signal of a first type including invalid data and a first signal of a second type both result on the bus based at least in part on the first request including the error, the first signal of the second type indicating that the bus is in an idle state, receiving, over the bus, a second request for the data based at least in part on the first signal of the second type resulting on the bus, and transmitting, over the bus based at least in part on successfully receiving the second request, a second signal of the first type including the data and a second signal of the second type including an indication that the bus is in an active state.

Some examples of the method 700 and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for generating the second signal of the second type based at least in part on successfully decoding the second request for the data, where transmitting the second signal of the second type may be based at least in part on generating the second signal of the second type.

Some examples of the method 700 and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for transmitting the second signal of the first type includes transmitting a plurality of subsets of the data in a plurality of intervals, each subset of the data being transmitted in a respective interval of the plurality of intervals and transmitting the second signal of the second type includes transmitting the second signal of the second type in an initial interval of the plurality of intervals.

In some examples of the method 700 and the apparatus described herein, and the method, apparatuses, and non-transitory computer-readable medium may include further operations, features, circuitry, logic, means, or instructions for transmitting, over the control line in a second interval that directly follows the initial interval, a signal of a third type that indicates whether the second signal of the first type may be associated with one or more errors.

In some examples of the method 700 and the apparatus described herein, a first logic value for the first signal of the second type indicates that the bus may be in the idle state and a second logic value for the first signal of the second type indicates that the bus may be in the active state, the first signal of the second type that results on the bus may have the first logic value, and the second signal of the second type that may be transmitted over the bus may have the second logic value.

FIG. 8 shows a flowchart illustrating a method 800 that supports techniques for detecting a state of a bus in accordance with examples as disclosed herein. The operations of method 800 may be implemented by a host device or its components as described herein. For example, the operations of method 800 may be performed by a host device as described with reference to FIGS. 1 through 4 and 6. In some examples, a host device may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally, or alternatively, the host device may perform aspects of the described functions using special-purpose hardware.

At 805, the method may include receiving, over a bus in an idle state, a signal of a first type including invalid data and a signal of a second type including an indication that the bus is in the idle state. The operations of 805 may be performed in accordance with examples as disclosed herein and with reference to FIG. 6. In some examples, aspects of the operations of 805 may be performed by a receiver 625 as described with reference to FIG. 6.

At 810, the method may include decoding the signal of the second type based at least in part on receiving the signal of the first type and the signal of the second type. The operations of 810 may be performed in accordance with examples as disclosed herein and with reference to FIG. 6. In some examples, aspects of the operations of 810 may be performed by a decoder 630 as described with reference to FIG. 6.

At 815, the method may include discarding the invalid data obtained from the signal of the first type based at least in part on determining, from decoding the signal of the second type, that the bus is in the idle state. The operations of 815 may be performed in accordance with examples as disclosed herein and with reference to FIG. 6. In some examples, aspects of the operations of 815 may be performed by a data manager 635 as described with reference to FIG. 6.

In some examples, an apparatus as described herein may perform a method or methods, such as the method 800. The apparatus may include, features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving, over a bus in an idle state, a signal of a first type including invalid data and a signal of a second type including an indication that the bus is in the idle state, decoding the signal of the second type based at least in part on receiving the signal of the first type and the signal of the second type, and discarding the invalid data obtained from the signal of the first type based at least in part on determining, from decoding the signal of the second type, that the bus is in the idle state.

Some examples of the method 800 and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for determining that the signal of the second type may have a first logic value based at least in part on decoding the signal of the second type and determining that the bus may be in the idle state based at least in part on the signal of the second type having the first logic value, where discarding the invalid data may be based at least in part on determining that the bus may be in the idle state.

Some examples of the method 800 and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for receiving the signal of the first type includes sampling one or more data lines of the bus during a plurality of intervals to receive subsets of the invalid data, each subset of the invalid data being received in a respective interval of the plurality of intervals and receiving the signal of the second type includes sampling a control line of the bus during an initial interval of the plurality of intervals.

Some examples of the method 800 and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for transmitting, over the bus, a first request for data, where receiving the signal of the first type and the signal of the second type may be based at least in part on transmitting the first request and transmitting, over the bus, a second request for the data based at least in part on discarding the invalid data obtained from the signal of the first type.

Some examples of the method 800 and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for receiving, while the bus may be in an active state and after receiving the signal of the first type, a second signal of the first type including data and a second signal of the second type including a second indication that the bus is in the active state, decoding the second signal of the second type based at least in part on the receiving, and decoding the second signal of the first type based at least in part on determining, from decoding the signal of the second type, that the bus may be in the active state.

In some examples of the method 800 and the apparatus described herein, and the method, apparatuses, and non-transitory computer-readable medium may include further operations, features, circuitry, logic, means, or instructions for receiving, over the control line in a second interval of the data input operation that directly follows the initial interval, a signal of a third type that indicates whether the second signal of the first type may be associated with one or more errors.

In some examples of the method 800 and the apparatus described herein, a first logic value for the signal of the second type indicates that the bus may be in the idle state and a second logic value for the signal of the second type indicates that the bus may be in the active state, and the signal of the second type may have the second logic value.

In some examples of the method 800 and the apparatus described herein, a first logic value for the signal of the second type indicates that the bus may be in the idle state and a second logic value for the signal of the second type indicates that the bus may be in an active state, and the signal of the second type may have the first logic value.

FIG. 9 shows a flowchart illustrating a method 900 that supports techniques for detecting a state of a bus in accordance with examples as disclosed herein. The operations of method 900 may be implemented by a system or its components as described herein. For example, the operations of method 900 may be performed by a system as described with reference to FIGS. 1 through 6. In some examples, a system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally, or alternatively, the system may perform aspects of the described functions using special-purpose hardware.

At 905, the method may include transmitting, by a host device over a bus that is coupled with the host device and a memory device, a request for data to the memory device. The operations of 905 may be performed in accordance with examples as disclosed herein and with reference to FIG. 6. In some examples, aspects of the operations of 905 may be performed by a host device transmitter as described herein and with reference to FIG. 6.

At 910, the method may include decoding, by the memory device, the request transmitted by the host device, where a signal of a first type including invalid data and a signal of a second type both result on the bus based at least in part on the first request including an error, the signal of the second type indicating that the bus is in an idle state. The operations of 910 may be performed in accordance with examples as disclosed herein and with reference to FIG. 5. In some examples, aspects of the operations of 910 may be performed by a memory device decoder as described herein and with reference to FIG. 5.

At 915, the method may include decoding, by the host device while the bus is in the idle state, the signal of the second type based at least in part on the request including the error. The operations of 915 may be performed in accordance with examples as disclosed herein and with reference to FIG. 6. In some examples, aspects of the operations of 915 may be performed by a host device decoder as described herein and with reference to FIG. 6.

At 920, the method may include discarding the invalid data obtained from the signal of the first type based at least in part on determining, from decoding the signal of the second type, that the bus is in the idle state. The operations of 920 may be performed in accordance with examples as disclosed herein and with reference to FIG. 6. In some examples, aspects of the operations of 920 may be performed by a host device data manager described herein and with reference to FIG. 6.

In some examples, an apparatus as described herein may perform a method or methods, such as the method 900. The apparatus may include, features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for transmitting, by a host device over a bus that is coupled with the host device and a memory device, a request for data to the memory device, decoding, by the memory device, the request transmitted by the host device, where a signal of a first type including invalid data and a signal of a second type both result on the bus based at least in part on the first request including an error, the signal of the second type indicating that the bus is in an idle state, decoding, by the host device while the bus is in the idle state, the signal of the second type based at least in part on the request including the error, and discarding the invalid data obtained from the signal of the first type based at least in part on determining, from decoding the signal of the second type, that the bus is in the idle state.

Some examples of the method 900 and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for receiving, by the host device, the signal of the first type, where receiving the signal of the first type includes sampling one or more data lines of the bus during a plurality of intervals to obtain subsets of the invalid data, each subset of the invalid data being obtained in a respective interval of the plurality of intervals and receiving, by the host device, the signal of the second type, where receiving the signal of the second type includes sampling a control line of the bus during an initial interval of the plurality of intervals.

Some examples of the method 900 and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for transmitting, by the host device over the bus, a second request for the data to the memory device based at least in part on decoding the signal of the second type, decoding, by the memory device, the second request transmitted by the host device, transmitting, by the memory device, a second signal of the first type including the data and a second signal of the second type based at least in part on a successful decoding of the request, the second signal of the second type indicating that the bus may be in an active state, and decoding the second signal of the first type based at least in part on determining, from decoding the second signal of the second type, that the bus may be in the active state.

Some examples of the method 900 and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for receiving, by the host device from the memory device, a signal of a third type that indicates whether the second signal of the first type may be associated with one or more errors, where the second signal of the first type may be decoded based at least in part on the signal of the third type.

In some examples of the method 900 and the apparatus described herein, the second signal of the second type may be received over a control line of the bus in an initial interval of a data input operation and the signal of the third type may be received over the control line in a second interval of the data input operation that directly follows the initial interval.

It should be noted that the methods described herein describe possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Further, portions from two or more of the methods may be combined.

Another apparatus is described. The apparatus may include a memory array, a controller coupled with the memory array and configured to transmit, over a bus that is coupled with the memory array, a signal of a first type for communicating data based at least in part on a request for data in the memory array, a circuit coupled with the memory array and the controller and configured to, set a signal of a second type to a first logic value when the bus is in an idle state or to a second logic value when the bus is in an active state, or both, transmit, over the bus, the signal of the second type based at least in part on setting the signal of the second type to the first logic value or the second logic value, and a pin coupled with the circuit and the bus, where the pin is configured to have the first logic value when the bus is in the idle state.

In some examples of the apparatus, the bus includes a plurality of transmission lines coupled with the controller and associated with communicating data, a transmission line coupled with the pin and associated with communicating indications of whether signals of the first type may be associated with one or more errors, and a voltage source coupled with the plurality of transmission lines and the transmission line, the voltage source having a voltage corresponding to the first logic value.

In some examples of the apparatus, a memory die that includes the memory array, the controller, and the circuit and a package for accessing the memory die that includes the pin.

In some examples of the apparatus, a second circuit coupled with the memory array and the pin, where the second circuit may be configured to detect whether the data included in the signal of the first type may be associated with one or more errors.

In some examples of the apparatus, the pin may be coupled with a control line of the bus, the circuit may be configured to transmit the signal of the second type over the pin during an initial interval of a data output operation, and the second circuit may be configured to transmit a signal of a third type over the pin during a second interval of the data output operation, the second interval directly following the initial interval.

Another apparatus is described. The apparatus may include a memory array, a controller coupled with the memory array and configured to cause the apparatus to, receive, over a bus, a first request for data, the first request including an error, where a first signal of a first type including invalid data and a first signal of a second type both result on the bus based at least in part on the first request including the error, the first signal of the second type indicating that the bus is in an idle state, receive, over the bus, a second request for the data based at least in part on the first signal of the second type resulting on the bus, and transmit, over the bus based at least in part on successfully receiving the second request, a second signal of the first type including the data and a second signal of the second type including an indication that the bus is in an active state.

In some examples of the apparatus, the controller may be further configured to cause the apparatus to generate the second signal of the second type based at least in part on successfully decoding the second request for the data, where the controller may be further configured to transmit the second signal of the second type based at least in part on generating the second signal of the second type.

In some examples of the apparatus, to transmit the second signal of the first type, the controller may be further configured to transmit a plurality of subsets of the data in a plurality of intervals, each subset of the data being transmitted in a respective interval of the plurality of intervals and to transmit the second signal of the second type, the controller may be further configured to transmit the second signal of the second type in an initial interval of the plurality of intervals.

In some examples of the apparatus, to transmit the second signal of the second type, the controller may be further configured to transmit the second signal of the second type over a control line of the bus in an initial interval of a data output operation and the controller may be further configured to cause the apparatus to transmit, over the control line in a second interval that directly follows the initial interval, a signal of a third type that indicates whether the second signal of the first type may be associated with one or more errors.

Another apparatus is described. The apparatus may include a memory array, a controller coupled with the memory array and configured to cause the apparatus to, receive, over a bus in an idle state, a signal of a first type including invalid data and a signal of a second type including an indication that the bus is in the idle state, decode the signal of the second type based at least in part on the receiving, and discard the invalid data obtained from the signal of the first type based at least in part on determining, from decoding the signal of the second type, that the bus is in the idle state.

In some examples of the apparatus, the controller may be further configured to cause the apparatus to determine that the signal of the second type may have a first logic value based at least in part on decoding the signal of the second type and determine that the bus may be in the idle state based at least in part on the signal of the second type having the first logic value, where the invalid data may be discarded based at least in part on determining that the bus may be in the idle state.

In some examples of the apparatus, to receive the signal of the first type, the controller may be further configured to cause the apparatus to sample one or more data lines of the bus during a plurality of intervals to receive subsets of the invalid data, each subset of the invalid data being received in a respective interval of the plurality of intervals and to receive the signal of the second type, the controller may be further configured to cause the apparatus to sample a control line of the bus during an initial interval of the plurality of intervals.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings may illustrate signals as a single signal; however, it will be understood by a person of ordinary skill in the art that the signal may represent a bus of signals, where the bus may have a variety of bit widths.

The terms “electronic communication,” “conductive contact,” “connected,” and “coupled” may refer to a relationship between components that supports the flow of signals between the components. Components are considered in electronic communication with (or in conductive contact with or connected with or coupled with) one another if there is any conductive path between the components that can, at any time, support the flow of signals between the components. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with or connected with or coupled with) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between connected components may be a direct conductive path between the components or the conductive path between connected components may be an indirect conductive path that may include intermediate components, such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a time, for example, using one or more intermediate components such as switches or transistors.