_railand V_REFas described further below in connection with FIG. 3.

The voltage trim circuit 230 can be manually configured to adjust the voltage output by the voltage source 240. Some underlying theory is first provided. The length of a cable carrying wires 204A and 204B from the power transmitter 210 to the transformer 222 in the rail voltage converter 220 is known. The output voltage of the power transmitter 210 is generally a constant. For example, if set to 400 VDC, it will be always 400 V DC until there is not enough current, at which time the voltage source 240 will go into an over-current protection and shut down. The V_railto be provided as output to an ASIC and associated current draw range of the ASIC are generally known, according to ASIC application. V_Tx-V_{cable_drop}-V_Transformer=V_rail, where V_Txis the value to be set and V_Transformeris by design.

If the current of the power transmitter is set to approximately 3 amps and the voltage V_Txis set to approximately 400 V, then the associated power is approximately 1200 Watts. V_{cable_drop}at 3 amps over one meter on a 24 AWG cable is less than 1 V. Thus, the V_railthat is needed can be determined. Accordingly, V_Tx=V_rail+V_{cable_drop}+V_Transformer.

As shown in FIG. 2E, a DIP switch bank 280 may be provided to allow for manually configuring the voltage adjustment made by the voltage trim circuit. The DIP switch bank 280 may include 4 DIP switches to trim voltage in one (1) volt steps as shown in FIG. 2F to cover different ranges of voltage for V_Tx. In this example, the voltage steps start at 392 V with the DIP switches (sw4,sw3,sw2,sw1) set to “0000”, and go to 400 V with the DIP switches set to “1000” and to 407 V with the DIP switches set to “1111”.

Reference is now made to FIG. 3. FIG. 3 shows a flow chart depicting a method 300 that may be performed by the rail voltage converter (and the comparator circuit 226 in particular) to generate the feedback waveform referred to above. The frequency of the feedback waveform is used to encode or indicate whether the voltage of the power waveform should be kept where it is, increased or decreased. The method 300 includes, at step 310, the comparator circuit 226 compares the DC rail voltage with a voltage reference, V_REF. When, at step 312, it is determined that the difference between the DC rail voltage and the voltage reference is zero or some nominal amount, this indicates that the DC rail voltage is at a desired level, and no change needs to be made to the voltage of the power waveform provided by the power transmitter. Thus, the frequency of feedback waveform is kept (or set) to a default frequency (e.g., 2 MHz), at step 314. On the other hand, when at step 312 it is determined that the difference between the DC rail voltage and the voltage reference is not acceptable, then at step 320, it is determined if the level of the DC rail voltage is low. If it is determined that the level of the DC rail voltage is low (relative to the voltage reference), then at step 322, the frequency of the feedback waveform is increased by a predetermined incremental amount, e.g., by 0.5 MHz to 2.5 MHz. On the other hand, if at step 330 it is determined that the DC rail voltage is high (relative to the voltage reference), then at step 332, the frequency of the feedback waveform is decreased by a predetermined incremental amount, e.g., by 0.5 MHz to 1.5 MHz. The method 300 may repeat on a periodic basis.

Reference is now made to FIG. 4 for a description of a flow chart for a process 400 performed by the power transmitter for controlling the voltage level of the power waveform. At step 410, the voltage of the power waveform is set to an initial or desired level. In addition, in step 410, an error count is initialized, to enable error reporting, as described below. The power transmitter then monitors the incoming feedback waveform, and in particular evaluates the frequency of the feedback waveform. If at step 420, the power transmitter determines that the frequency of the feedback waveform is at a predetermined default frequency, e.g., 2 MHZ, then at step 422, the power transmitter holds the voltage level of the power waveform where it is (the initial or desired level). If at step 420, the power transmitter determines that the frequency of the feedback waveform is not at the predetermined default frequency, then at step 430, it determines whether the frequency of the feedback waveform is at first increased frequency (e.g., 2.5 MHz), and if so, then the power transmitter increases the voltage of the power waveform by one step or incremental amount (e.g., 5 V, or some other incremental amount), at step 432. If at step 430 the power transmitter determines that the frequency of the feedback waveform is not increased by a predetermined amount relative to the predetermined default frequency (e.g., to 2.5 MHz), then at step 440, the power transmitter determines whether the frequency of the feedback waveform has been decreased by a predetermined amount relative to the predetermined default frequency (e.g., to 1.5 MHz). At step 442, the power transmitter decreases the voltage of the power waveform by one step or incremental amount (e.g., 5 V). If at step 440 the power transmitter determines that the frequency of the feedback waveform has not been decreased by a predetermined amount, then the method proceeds to step 450 where an error is declared and reported. Next, at step 452, the error count is incremented. If the error count is greater than a threshold, then a step 454, power is disabled and at step 456 a report is made that the power has been disabled. If the error count is less than the threshold, then the process 400 repeats from step 410. The error threshold may be set to 3, in one example. Thus, if the feedback waveform does not match any of the frequencies (at steps 420, 430 and 440) three times, then an error has occurred and initialization is re-attempted. In this way, the output power can be fine-tuned with no additional switching circuit loss.

Thus, when the frequency of the feedback waveform is:

- Default Frequency (e.g., 2 MHZ)−Rail voltage is good and no change is needed
- Default Frequency+some incremental amount (e.g., 2.5 MHz)−Rail voltage is low so need to increase the voltage level of the power waveform
- Default Frequency−some incremental amount (e.g., 1.5 MHz)−Rail voltage is high so need to decrease the voltage of the power waveform

Reference is now made to FIG. 5. This figure shows a power waveform 500 and a feedback waveform 510. In this example, the power waveform 500 is a series of successive pulses of power on-times 502 separated by power off-times 504. The duty cycle of the power on-times relative to the power off-times may vary, and FIG. 5 is not meant to be suggestive of a particular duty cycle. The height or level of the pulses or power on-times 502 determines the voltage level of the power waveform 500 and thus the voltage level generated at the output of the rail voltage converter, referred to above, by operation of the transformer and rectifier circuit. It should be understood that the power waveform 500 need not have a square/rectangular wave shape, and it could be other shapes, such as a sinusoidal wave shape, triangular, etc.

The feedback waveform 510 may be a periodic waveform (of a sinusoidal or other shape) and the frequency of the feedback waveform 510 is used to signal the level of V_railrelative to the voltage reference V_REF. When V_railis substantially equal to V_REF(within some tolerance), the rail voltage converter keeps the frequency of the feedback waveform 510 at a default or nominal value referred to as F_def. The power transmitter detects that the frequency of the feedback waveform 510 is at the default or nominal value and does not change the voltage level of the power waveform 500, as shown at 520. When V_railis greater than V_REF, then the rail voltage converter reduces the frequency of the feedback waveform by an incremental amount (F_def−increment). The power transmitter detects that the frequency of the feedback waveform is an incremental amount below the default frequency value, and in response, decreases the voltage of the power waveform, i.e., by reducing the level of the pulses during the power on-times 502, as shown at 522. Conversely, when V_railis less than V_REF, then the rail voltage converter increases the frequency of the feedback waveform by an incremental amount (F_def+increment). The power transmitter detects that the frequency of the feedback waveform is an incremental amount above the default frequency value, and in response, increases the voltage of the power waveform, i.e., by increasing the level of the pulses during the power on-times 502, as shown at 524. It should be understood that the logic could be reversed such that when V_railis less than V_REF, the rail voltage converter could decrease the frequency of the feedback waveform by an incremental amount (F_def−increment) and when V_railis greater than V_REF, then the rail voltage converter could increase the frequency of the feedback waveform by an incremental amount (F_def+increment).

The feedback loop described above is not required. Instead, a “second step” in the transformer conversion can be added to regulate the component rail power directly at the transformer secondary windings. In some cases, this may not be as desirable, and for component distribution it may be simpler to adjust the voltage at the power transmitter side for fine control on the secondary side of the transformer.

FIG. 6 shows a single ferrite structure design for a transformer that may be used in the rail voltage converter for the various embodiments presented herein. The transformer 600 is a single (open) core, as opposed to the three-monument design of the transformer shown in FIGS. 2A and 2B. The transformer comprises a single core 602, a primary winding 604 around the core 602 and a secondary winding 606 around the primary winding 604. The power waveform from the power transmitter is coupled to the primary winding 604 and the secondary winding is connected to the rectifier circuit (not shown in FIG. 6 for simplicity).

Reference is now made to FIGS. 7A-7G that show examples of designs for a transformer that may be used in the system and configurations presented herein. FIG. 7A shows a three-monument transformer 700 that may have a two-piece design comprising a first portion 710A and a second portion 710B. Each of the first and second portions 710A and 710B comprises three-monument portions that connect together through an alignment mechanism to form the three-monument transformer. It is also envisioned that only one of the first portion 710A and the second portion 710B may be sufficient to form the transformer 700. A multi-monument transformer as shown in FIG. 7A has an advantage of being capable of handling higher power.

As shown in FIG. 7B, a transformer monument 720 (whether for a three monument transformer as shown in FIG. 7A or a single monument/single core transformer) may have a rectangular-rectangular cross-section or a square-rectangular cross section. Alternatively, as shown in FIG. 7C, a transformer monument 730 (whether for a three monument transformer as shown in FIG. 7A or a single monument/single core transformer) may have a circular cross section/cylindrical shape.

FIG. 7D shows a multi-monument transformer 740 in more detail, according to an example embodiment. In one example, the transformer 740 includes three monuments: a central monument 742A, a first secondary monument 742B and a second secondary monument 742C, but could have any number of monuments.

A primary winding 744A is wrapped around the central monument 742A. The primary winding is the high-voltage winding because it receives the high-voltage power waveform from the power transmitter. In one example, the primary winding is made of 22 AWG to 30 AWG insulated and/or enameled wire. The primary winding 744A may be relatively tightly wrapped around the central monument 742A. A first secondary winding 744B wraps around the first secondary monument 742B. In one example, the first secondary winding 744B comprises two turns of thick copper foil for a first (higher) rail voltage. For example, the first secondary winding is 250 mil wide×5 mil thick copper foil. A second secondary winding 744C wraps around the second secondary monument 742C. The second secondary winding 744C may comprise one turn (or almost one turn) of wide copper foil (e.g., 1 mil to 100 mil thick) tightly wrapped, but not shorting (that is, not fully around the second secondary monument 742C), for a second rail voltage. The second secondary winding 744C could be two pieces of copper foil broken up into 2 separate turn portions. As will be described below in connection with FIGS. 8A and 8B, the transformer 740 (within an appropriate package or housing) can be soldered to the back of an integrated circuit and the rail voltages connected into the integrated circuit (from the rectifier circuits).

FIG. 7E shows a transformer 760 having a single monument construction. The transformer 760 comprises a monument 762 with a primary winding 764 formed from a high voltage wire wrapped around the monument 762 closest to the core/center of the monument 762. A secondary winding 766 made of copper foil is wrapped around the outside of the primary winding 764. There may be a thin insulation between the primary winding 764 and the secondary winding 766. Also, the transformer 760 may have multiple primary windings: one with more turns than the other to provide selectable ranges of input voltage. In addition, there may be more than one copper foil winding overlaying or overlapping the primary winding(s). Moreover, as described below in connection with FIG. 7G, the copper foil used for the primary and/or secondary winding(s) could be integrated with graphene.

FIG. 7F shows a cross-section of a copper foil 770 that is solid copper 772. This may be used for a winding in any of the embodiments/configuration presented herein that involve use of a copper foil.

FIG. 7G shows a cross-section of a copper foil 780 that is comprised of multiple layers. For example, there are three copper layers 782A, 782B and 782C with two graphene layers 784A and 784B between copper layers to improve efficiency. Graphene may be used in the primary and secondary windings. Again, in the case of a single monument transformer, the primary winding is first applied to a monument/ferrite core, and the secondary winding may be wrapped over the primary winding, optionally with a high voltage isolation dielectric material between them.

Reference is now made to FIG. 8A. FIG. 8A shows a perspective view of a power delivery arrangement 800 employing the techniques presented herein. An integrated circuit package 810 is mounted on a printed circuit board (PCB) 820. A rail voltage converter package 830 is provided that includes therein a transformer (of any of the types described herein), one or more rectifier circuits and a comparator circuit, all contained within a housing or enclosure 832. A power transmitter 840 is coupled via the wire pair 842 to input leads 832A and 832B on the rail voltage converter package 830 to provide the high voltage power waveform to the rail voltage converter package 830.

The rail voltage converter package 830 has output leads 834 and is soldered or otherwise affixed to the underside of the integrated circuit package 810 or underside of the PCB 820. The rail voltage(s) produced by the rail voltage converter package 830 are connected via the output leads 834 to the integrated circuit package 810 or to PCB 820. In addition, the feedback waveform produced by the rail voltage converter package 830 is coupled by the wire pair 842 to the power transmitter 840. All the power components (e.g., power source and power transmitter) are separate from the integrated circuit package 810 and PCB 820 and just connected to the transformer by the wire pair 842.

FIG. 8B illustrates a power delivery arrangement 800′ that is a variation of the power delivery arrangement 800 shown in FIG. 8A. In the power delivery arrangement 800′, the direct attach of power is to the top side of an integrated circuit, rather than the bottom side of a PCB 820 as shown in FIG. 8A. The integrated circuit package 810 may include anchor pads 850 to support the rail voltage converter package 830 and rail pads 860 to connect with the output leads 834 on the rail voltage converter package 830. Cooling of the power delivery arrangement 800′ may be achieved in many ways, including liquid cooling, air cooling, etc., all of which are adaptable to the top side direct attach method depicted in FIG. 8B.

Turning now to FIG. 9, a perspective view is shown of an electronic device 900 having a plurality of PCB layers for power and other functions as well as processing modules or devices. In a bottom layer 910, there are power transmitters (power Tx) 920, 922 and 924, and the plurality of layers above the bottom layer 910, there are processing modules 930, 932 and 934 that plug into an associated slot or receptacle in an associated layer. The power Tx 920 is connected by wire pair 940 to processing module 930, the power Tx 922 is connected by wire pair 942 to processing module 932 and the power Tx 924 is connected by wire pair 944 to processing module 934. The processing modules 930, 932 and 934 could be networking processors, graphic processors, artificial intelligence (AI) processors, etc.

FIG. 10 illustrates a flow chart depicting a method 1000 according to an example embodiment. The method 1000 involves providing a DC rail voltage to one or more power consuming devices. At step 1010, the method includes, generating, with a power transmitter, a power waveform at a first voltage. The power waveform includes a series of successive on-times that are separated by an off-time. At step 1020, the method includes receiving the power waveform, via a wire pair, at a transformer. At step 1030, the method includes converting, with the transformer, the power waveform at the first voltage to an output waveform at a second voltage. At step 1040, the method includes, rectifying the output waveform to produce a direct current (DC) rail voltage for use by one or more power consuming devices.

In summary, presented herein are configurations for a single step source voltage direct to component rail power conversion using a transformer combined with a feedback control loop to adjust voltage at the power transmitter.

In some aspects, the techniques described herein relate to an apparatus including: a power transmitter configured to generate a power waveform at a first voltage, the power waveform including a series of successive on-times that are separated by an off-time; a transformer coupled to the power transmitter, wherein the transformer is configured to receive the power waveform and perform a single step down conversion of the power waveform at the first voltage to an output waveform at a second voltage; and a rectifier circuit coupled to the transformer to receive the output waveform and produce a direct current (DC) rail voltage for use by one or more power consuming devices.

In some aspects, the first voltage is in a range of 350 volts to 400 volts, and the DC rail voltage is in a range of 0.60 volts to 1.8 volts.

In some aspects, the techniques described herein relate to an apparatus, further including a wire pair that connects an output of the power transmitter to a primary winding of the transformer.

In some aspects, the techniques described herein relate to an apparatus, further including a comparator circuit that compares the DC rail voltage with a reference voltage and generates a feedback signal to be communicated to the power transmitter, wherein the power transmitter is configured to adjust the first voltage of the power waveform responsive to the feedback signal so as to maintain the DC rail voltage at a desired level.

In some aspects, the techniques described herein relate to an apparatus, wherein the comparator circuit is configured to generate the feedback signal so as to cause the power transmitter to decrease the first voltage when the DC rail voltage is greater than the reference voltage and to increase the first voltage when the DC rail voltage is less than the reference voltage.