Furthermore, at least two VCO cores are included and two adjacent VCO cores, among the at least two VCO cores, have at least some frequency segments with frequency overlaps.

Furthermore, between the two adjacent VCO cores, the VCO core having a higher frequency range only has its lowest frequency segment overlapped in frequency with the highest frequency segment of VCO having a lower frequency range.

Furthermore, among all the frequency segments, at least some of the adjacent frequency segments have the frequency overlap rate less than 3%.

Compared to existing technologies, the present invention has the following advantages and beneficial effects:

1. In the present invention, through real-time or periodic status checks for a tuning voltage input to the VCO core from the PLL, a frequency segment may be adjusted in advance by adjusting a segment selection signal when the tuning voltage is abnormal. This ensures that the output frequency of the VCO core always remains within a frequency segment having a matched frequency range. Consequently, the PLL can continuously maintain its lock status under temperature variations, preventing phase noise deterioration and sudden unlock caused by external temperature variations, thereby enhancing operation stability and reliability for the segmented-VCO-based PLL.

2. In the present invention, frequency segments may be adjusted in real-time by detecting in real-time or at predetermined intervals whether the tuning voltage is normal, and thus allowing each frequency segment within a VCO core of the PLL system to have a narrower frequency coverage range and a smaller frequency overlap rate compared to existing technologies. For example, at least some of the adjacent frequency segments may have a frequency overlap rate less than 3%, thereby ensuring that each frequency segment has a lower tuning sensitivity, which is advantageous for the signal source to exhibit sufficiently low in-band phase noise after frequency lock.

3. In the present invention, more stable and faster switching of frequency segments may be achieved by initializing the frequency sweeping to create a frequency segment look-up table. This effectively enhances operational stability and reliability for segmented-VCO-based PLLs.

4. The use of multiple VCO cores allows a narrower frequency range and a smaller frequency overlap rate for each frequency segment of each VCO core, thereby further reducing the tuning sensitivity of each frequency segment.

5. In the present invention, after the look-up table is established, redundant overlapped frequency segments are removed to not only shorten the lock time required for real-time calibration under temperature variations, but also reduce data volume needed for the lookup table and segment selection signal, thereby saving storage space and enhancing the retrieval speed of the output frequency.

BRIEF DESCRIPTION OF THE DRAWINGS

Reference will be made to exemplary embodiments of the present invention that are illustrated in the accompanying figures. Those figures are intended to be illustrative, rather than limiting. Although the present invention is generally described in the context of those embodiments, it is not intended by so doing to limit the scope of the present invention to the particular features of the embodiments depicted and described.

FIG. 1 depicts a block diagram of a calibration method in embodiments of the present invention;

FIG. 2 depicts a block diagram of adjustment process when the tuning voltage exceeds a normal operation range in embodiments of the present invention;

FIG. 3 depicts a calibration schematic diagram of segment switching within the same VCO core in embodiments of the present invention;

FIG. 4 depicts a calibration schematic diagram involving core-crossing between two adjacent VCO cores (VCOA, VCOB) in embodiments of the present invention;

FIG. 5 depicts a schematic diagram of deleting redundant segments when two adjacent VCO cores (VCOA, VCOB) in the look-up table have multiple overlapped frequency segment in embodiments of the present invention;

FIG. 6 depicts a block diagram of calibration system in embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following description, specific embodiments and figures are set forth in order to provide an understanding of purposes, technical solutions and benefits of the present invention. The exemplary embodiments of the present invention and descriptions hereinafter are explanations for the present invention only, rather than limitations for the present invention.

When the specification uses terms such as “front”, “back”, “left”, “right”, “above”, “below”, “vertical”, “horizontal”, “high”, “low”, “inside”, “outside”, and other terms of orientation or positional relationship, it is intended to make references to orientation or positional relationship described in the drawings. This is only for the convenience of simplifying the description when describing the invention. It does not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation. Thus, it is not intended by so doing to limit the scope of the present invention to the particular features of the embodiments depicted and described.

In the description of the present invention, it should be understood that the term “real-time” includes both continuous and uninterrupted execution, and execution at predetermined time intervals.

Embodiment 1

FIG. 1 depicts a frequency calibration method for a segmented-VCO-based PLL, which comprises at least one VCO core with each VCO core comprising multiple frequency segments. The calibration comprises following steps:

- receiving a request to lock a PLL to a desired output frequency;
- searching in a look-up table for a segment selection signal corresponding to the desired output frequency, and operating a current VCO core according to the segment selection signal to lock the PLL to the desired output frequency;
- obtaining a tuning voltage inputting to the current VCO core in real-time or at predetermined time intervals, evaluating whether the tuning voltage is within a normal operation range. If the tuning voltage exceeds the normal operation range, the segment selection signal is adjusted to switch the current VCO core from a current frequency segment to another frequency segment within the same VCO core, or switch from the current VCO core to another frequency segment of a different VCO core until the PLL is locked to the desired output frequency with the tuning voltage staying within the normal operation range.

In one or more embodiments, the look-up table only needs to be established once. After establishing the look-up table from frequency sweeping, the look-up table is stored in a non-volatile memory, e.g. ROM. Data may be retrieved directly from the look-up table for each calibration. In some embodiments, a look-up table can be established multiple times. Each time after power of PLL is on, a look-up table is re-established in a RAM through frequency sweeping.

In some preferred embodiments, based on whether a tuning voltage is within a normal operation range (for example, 0.5V-2.8V), the tuning voltage may be determined as normal or not. When the tuning voltage exceeds an upper bound of the normal operation range, (e.g., 2.8V), the segment selection signal is adjusted to switch from the current frequency segment of the VCO core to an adjacent frequency segment having a higher frequency range; when the tuning voltage falls below a lower bound of the normal operation range (e.g., 0.5V), the segment selection signal is adjusted to switch from the current frequency segment of the VCO core to an adjacent frequency segment having a lower frequency range. As temperature increases and the obtained tuning voltages reaches or exceeds the upper bound, an adjustment signal is characterized as +1 for the segment selection signal, meaning adjusting the segment selection signal to an adjacent segment having a higher frequency range. On the other hand, as temperature decreases and the acquired tuning voltages reaches or falls below the lower bound, the adjustment signal is characterized as −1 for the segment selection signal, meaning adjusting the segment selection signal to an adjacent segment having a lower frequency range.

In some embodiments, the adjacent frequency segment having a higher or lower frequency range than the current frequency segments may be located in the same VCO core as the current frequency segment or in a different VCO core. In one or more embodiments, when two adjacent VCO cores have multiple frequency segments with overlapping frequencies, the frequency ranges of the segments before and after the initial segment switching may not be adjacent. In this case, segment switching continues after the initial segment switching until a frequency segment is reached whose frequency range is adjacent to the frequency range of the segment before the initial segment switching.

In the present embodiment 1, by real-time status checking the tuning voltage input to the VCO core, the frequency segment may be adjusted in advance through an adjustment of the segment selection signal when the tuning voltage becomes abnormal. This ensures that the output frequency of the VCO core always remains within a frequency segment having a matched frequency range. Consequently, the PLL can continuously maintain its lock status under temperature variations, thus preventing phase noise deterioration and sudden unlock caused by external temperature variations or other factors, which affects stability of the PLL system.

Embodiment 2

On the basis of Embodiment 1, prior to adjusting the segment selection signal, determine whether the current segment frequency of the VCO core is located within the same VCO core as the adjacent frequency segment;

If yes, directly switching to the adjacent frequency segment is performed;

If no, the VCO core containing the adjacent frequency segment is enabled while all the other VCO cores are disabled, and a switching operation is made to the adjacent frequency segment.

As depicted in FIG. 2, when the tuning voltage (VT) is detected to exceed the normal operation range, if the tuning voltage is below the lower bound of the normal operation range, then the segment selection signal needs to be lowered to an adjacent frequency segment having a lower frequency range accordingly. Prior to adjustment, it is necessary to determine whether the segment selection signal involves VCO core-crossing. If no core-crossing involved, the target frequency segment is located in the same VCO core as the current frequency segment, and the segment selection signal may be directly adjusted by −1 for switching to the adjacent segment with a lower frequency range. If core-crossing involved, the target frequency segment is located in a different VCO from the initial frequency segment. In this case, the target VCO core with a lower frequency range is enabled first while the other VCO cores are disabled; the segment selection signal is adjusted to the highest frequency segment of the target VCO core. Subsequently, the segment selection signal is adjusted, by real-time detection of the tuning voltage, to an appropriate frequency segment within the target VCO core to achieve PLL lock.

Similarly, as depicted in FIG. 2, when the tuning voltage is detected to exceed the normal operation range, if the tuning voltage exceeds an upper bound of the normal operation range, the segment selection signal needs to be raised to select an adjacent frequency segment with a higher frequency range accordingly. Prior to adjustment, it is necessary to determine whether the segment selection signal adjustment involves VCO core crossing. With no core crossing, the segment selection signal is directly adjusted by +1 for switching to the adjacent segment having a higher frequency range. With core crossing involved, the target VCO core having a higher frequency range needs to be enabled while other VCO cores are disabled. The segment selection signal is then adjusted to the lowest frequency segment of the target VCO core. Subsequently, the segment selection signal is adjusted, by real-time detection of the tuning voltage, to an appropriate frequency segment within the target VCO core.

Embodiment 3

FIG. 3 depicts a calibration schematic diagram of segment switching within the same VCO core. In an example of a normal operation range of the tuning voltage between 0.5 V and 2.8V, when the tuning voltage is within the normal operation range, a frequencies overlap (with a frequency overlap rate <3%) between adjacent frequency segments may ensure a stable lock status and optimal performance. When the tuning voltage is less than 0.5 V or greater than 2.8 V, under external environmental influence such as temperature variations, the PLL is highly susceptible to phase noise deterioration or even a sudden unlock.

As depicted in FIG. 3, the tuning voltage is checked in real-time when the PLL is maintained in a closed-loop status. When the tuning voltage is less than 0.5V, the segment selection signal is adjusted by −1 for segment switching from the current frequency segment Seg 3 to an adjacent frequency segment Seg 2 that has a lower frequency range. When the tuning voltage is greater than 2.8V, the segment selection signal is adjusted by +1 for segment switching from the current frequency segment Seg 3 to an adjacent frequency segment Seg 4 that has a higher frequency range. Because the frequency segment is preemptively adjusted based on the condition of the tuning voltage, the output frequency of the VCO core remains stable. There is frequency overlap in frequency ranges of adjacent frequency segments when the tuning voltage is within the normal operation range. After segment switching upward or downward, the tuning voltage still falls within the normal operation range (0.5V-2.8V).

Embodiment 4

FIG. 4 depicts a calibration schematic diagram of core-crossing between two adjacent VCO cores (VCOA, VCOB). As shown, SegA16 to SegA20, which are the segments with five highest frequency ranges in VCOA overlap with SegB1 to SegB4, which are the segments of four lowest frequency ranges in VCOB. Similarly, the normal working range of the tuning voltage is 0.5V-2.8V. As shown in FIG. 4, the initial segment is SegB1 of VCOB (the lowest frequency segment of VCOB). When the tuning voltage VT falls below 0.5V, due to involvement of VCO core crossing, a downward switching is performed from SegB1 to segA20 of VCOA (the highest frequency segment of VCOA). After completing the cross-core switching, since a target frequency segment has not yet been reached, it is necessary to continue downward segment switching until the detected tuning voltage finally falls within the normal working range. As shown in