FIG. 7 is a cross-sectional side view of an embodiment of a portion of a host device 40. The host device 40 can be a module, card, blade, etc. associated with a network element, such as a switch, router, terminal, computing device, etc. The host device 40 includes a housing 42 in which a mounting assembly 44 is incorporated. The mounting assembly 44, for example, may include a socket interface 46 and a PCB 48. The socket interface 46 may include a receptacle 50 (or socket) configured to physically receive and support a pluggable module 52. The receptacle 50 may be accessible from a face plate 54 on the front of the host device 40. The pluggable module 52 includes pins and connectors for electrical connection with corresponding conductors 56 arranged within the receptacle 50. The socket interface 46 further includes connection (not shown) between the conductors 56 and conductors 58 (e.g., pins, etc.) arranged at a bottom portion of the socket interface 46 for electrical connection with electrical contacts arranged on the PCB 48.

To minimize the unwanted impedance characteristics introduced by the creation of stubs 30, 34 described with respect to FIGS. 3 and 4, the mounting assembly 44 is configured to remove the Surface Mount Technology (SMT) type pins (e.g., connector pins 26) and replace these elements with the conductors 58 (e.g., straight pin elements), which are configured to terminate at a smaller space. Likewise, the PCB 48 can be configured to include solder balls 60, which can be arranged directly below the location of the conductors 58. Therefore, this arrangement eliminates the creation of problematic stubs 30, 34 in the electrical signal path.

FIG. 7 illustrates a single host device 40 and associated socket interface 46 on the PCB 48. In a belly-to-belly configuration, arrangement, etc., there will be another host device 40 and associated socket interface 46 located below, so that the PCB 48 has socket interfaces 46 on both sides. That is, belly-to-belly refers to the fact there are conductors 56 and conductors 58 on both sides of the PCB 48. Further, the sizes of the pluggable optical modules are decreasing while the data rates are increasing, leading to the various problems addressed herein, especially in belly-to-belly configurations where space is limited.

FIG. 8 shows a front view of the face plate 54 of the host device 40 of FIG. 7. The face plate 54 may include multiple sockets or receptacles 50 for receiving multiple pluggable modules (e.g., pluggable module 52). Of note, a belly-to-belly configuration 64 is shown here in the host device 40, where there are associated socket interfaces 46 on both sides of the PCB 48.

FIG. 9 is a diagram showing a plan view of an embodiment of an electrical contact footprint 70 of the PCB 48 of the mounting assembly 44 shown in FIG. 7. Hence, to avoid above stated challenges, the connection arrangement, according to various implementations, may include solder ball terminations for connection with the vertically aligned pins or conductors 58 of the socket interface 46. For example, the electrical contact footprint 70 may have staggered Tx and Rx pair pins, as described in more detail below. It should be noted that the electrical contact footprint 70 of FIG. 9 differs from the electrical contact footprint 10 of FIG. 1 in some ways while also including some similarities. Nevertheless, the electrical contact footprint 70 can be implemented without modifications to standardized characteristics of pluggable modules 52 and receptables 50.

The electrical contact footprint 70 of the PCB 48 includes an arrangement of contacts 74 (e.g., Ball Grid Array (BGA) contacts), whereby each contact 74 includes a specific size and shape and whereby the contacts 74 are separated from each other in a particular pattern. For example, the contacts 74 are arranged in four rows, including (from back to front) a first row 76a, a second row 76b, a third row 76c, and a fourth row 76d. Ground contacts 78 are also arranged on the PCB 48.

Each contact 74 may be substantially circular and have a diameter of 0.31 mm±0.03 mm, in an example embodiment. The contacts 74 in each row 76 are separated by a pitch of 0.80 mm, in an example embodiment. The rows 76 are separated from each other to have a center-to-center spacing of 2.93 mm, in an example embodiment. The third and fourth rows 76c, 76d are offset from the first and second rows 76a, 76b by a lateral offset of 0.40 mm, in an example embodiment. Each row 76 may have 19 pins, whereby a pin numbering scheme may be defined whereby the contacts 74 of the fourth row 76d include (from left to right) PIN 1 through PIN 19, the contacts 74 of the first row 76a include (from right to left) PIN 20 through PIN 38, the contacts 74 of the third row 76c include (from left to right) PIN 39 through PIN 57, and the contacts 74 of the second row 76b include (from right to left) PIN 58 through PIN 76.

Furthermore, each row 76 may include three sets of contacts, including, for example, a first set 80a of contacts, a second set 80b of contacts, and a third set 80c of contacts. In some embodiments, the first set 80a in each row 76 may include seven contacts 74, the second set 80b in each row 76 may include five contacts 74, and the third set 80c in each row 76 may include seven contacts 74. The second set 80b of contacts in each row 76 may be offset (in a rearward direction) from the first set 80a of contacts by a distance of 0.5 mm, in an example embodiment. Also, the third set 80c of contacts in each row 76 may be offset (in a rearward direction) from the second set 80b of contacts by a distance of 0.5 mm.

Of course, those skilled in the art will appreciate these values in terms of number of rows, number of sets, sizes, offset amount, etc. are merely presented for illustration purposes; other values are contemplated. In a belly-to-belly configuration, the first set 80a and the third set 80c will be offset from the electrical contact footprint 70 on the other side, while the second set 80b will have little offset. This is advantageous as high-speed connections can be in the first set 80a and the third set 80c, while lower speed connections can be in the second set 80b.

Therefore, according to various embodiments, the present disclosure may include a host device 40 including a Printed Circuit Board (PCB) 48 including a first side with multiple rows 76 of Ball Grid Array (BGA) contacts 74; and a first socket interface 46 including a receptacle 50 configured to receive a pluggable optical module 52 for communication therewith, the socket interface 46 further including multiple electrical conductors 58 configured for electrical connection with the BGA contacts 74. Each row 76 of the BGA contacts 74 on the first side may include multiple first sets (80) of contacts 74 offset from each other in a first direction 82 with respect to a planar surface of the first side of the PCB 48.

The multiple first sets 80 of contacts 74 may include a first set 80a of solder balls, a second set 80b of solder balls, and a third set 80c of solder balls, and wherein the second set 80b of solder balls is offset from the first set 80a of solder balls in the first direction 82 and the third set 80c of solder balls is offset from the second set 80b of solder balls in the first direction 82. The first set 80a and the third set 80c may each be used for high-speed connections relative to the second set 80b.

The PCB 48 may include a second side with multiple second rows 76 of second BGA contacts 74, and the host device 40 includes a second socket interface 46 including a second receptacle 50 configured to receive a second pluggable module 52 for communication therewith, the second socket interface 46 further including multiple second electrical conductors 58 configured for electrical connection with the second BGA contacts 74. Each row 76 of the BGA contacts 74 on the second side may include multiple second sets 80 of contacts 74 offset from each other in a first direction 82 with respect to a planar surface of the second side of the PCB 48.

Some of the multiple first sets 80 of contacts 74 and the multiple second sets 80 of contacts 74 may be offset from each other in a belly-to-belly configuration. The multiple first sets 80 of contacts 74 and the multiple second sets 80 of contacts 74 each may include a first set 80a of solder balls, a second set 80b of solder balls, and a third set 80c of solder balls, and wherein the second set 80b of solder balls is offset from the first set 80a of solder balls in the first direction 82 and the third set 80c of solder balls is offset from the second set 80b of solder balls in the first direction 82. The first set 80a and the third set 80c may each be used for high-speed connections relative to the second set 80b.

The pluggable optical module 52 may include any of Small Form-factor Pluggable (SFP) transceivers, Quad SFP (QSFP) transceivers, QSFP Double-Density (QSFP-DD) transceivers, Octal SFP (OSFP) transceivers, C (100) Form-factor Pluggable (CFP) transceivers, and variants thereof.

In another embodiment, a network element includes one or more modules each includes a Printed Circuit Board (PCB) including a first side with multiple rows of Ball Grid Array (BGA) contacts; and a first socket interface including a receptacle configured to receive a pluggable optical module for communication therewith, the socket interface further including multiple electrical conductors configured for electrical connection with the BGA contacts.

In a further embodiment, a Printed Circuit Board (PCB) for use in networking hardware to support a belly-to-belly configuration of pluggable optical modules, the PCB includes a first side and a second side, each with multiple rows of Ball Grid Array (BGA) contacts; and a plurality of socket interfaces, each including a receptacle configured to receive a pluggable optical module for communication therewith, each socket interface further including multiple electrical conductors configured for electrical connection with the BGA contacts, wherein the belly-to-belly configuration includes at least one pair socket interfaces being disposed near one another of the first side and the second.

Thus, some advantages of the embodiments described with respect to FIGS. 7-9, as suggested above, include an arrangement where no extra fanout traces of microstrip lines are required in BGA, since via-on-pad elements can be used. Also, due to staggering of Tx and Rx pairs, fanout with respect to belly-to-belly arrangements is configured to leave sufficient space for back-drilling from both top and bottom sides of a PCB for SerDes vias. Also, the present embodiments allow easy implementation of impedance matching for fanouts as via-on-pad elements can be incorporated on BGA pads. Furthermore, the embodiments described herein avoid multiple impedance discontinuities being generated, as opposed to legacy configurations where rectangular SMT pads and their fanouts traces with legacy QSFP-DD footprints inherently create such unwanted discontinuities. Additionally, the systems of the present disclosure are configured to save up to four SerDes routing layers for belly-to-belly configurations and up to two SerDes routing layers for single side connector placements.

Belly-to-Belly Configuration

FIG. 10A shows a plan view of fanout microstrip lines for connection with a socket module in a belly-to-belly arrangement of a conventional implementation. In contrast, FIG. 10B shows a plan view of fanout microstrip lines for connection with the socket interface 46 of the mounting assembly 44 shown in FIG. 7 in a belly-to-belly arrangement. It may be noted that the arrangement of FIGS. 7-9 allows for a smaller overall footprint on the PCB, even in a belly-to-belly fanout arrangement.

In the traditional connector associated with the embodiment of FIG. 10A, SMT rectangular pads of the connector must be impedance matched, which can be more difficult since their pad width is generally more than PCB traces of the same impedance. To match the impedance, 3-4 layers under the top layer of the PCB must have cutouts. However, with respect to the embodiments of the present disclosure (e.g., the embodiment of FIG. 10B), the impedance issues are reduced, and any needed matching circuits can more easily be incorporated in the less congested design with the solder-ball terminated connectors.

Again, in a belly-to-belly configuration, the first set 80a and the third set 80c will be offset from the electrical contact footprint 70 on the other side, while the second set 80b will have little offset. This is advantageous as high-speed connections can be in the first set 80a and the third set 80c, while lower speed connections can be in the second set 80b. Specifically, there are less requirements for cutouts in the PCB 48 for impedance matching of the high-speed connections in the first set 80a and the third set 80c.

FIG. 11 shows a plan view of a multi-layer PCB with cutouts in layers underneath pads for connection with a socket module. For example, second, third, and fourth layers underneath the first layer where SMT pads are positioned may include cutouts, anti-pads, etc., allowing space for matching circuits if needed.