12, a transmit analog baseband (TX ABB) circuit 13, and a frequency mixer 14. Optionally, the communication apparatus may further include a power amplifier (PA) 15 and an antenna 16. Each radio frequency circuit 02 may include the TX ABB circuit 13, the frequency mixer 14, the PA 15, and the antenna 16. The PLL circuit 10 may include the ring oscillator provided in embodiments of this application. In a possible design, the DBB circuit 12 and the TX ABB circuit 13 are collectively referred to as a baseband circuit. First, connection relationships between the foregoing components are described.

An output end of the PLL circuit 10 is connected to an input end of the LO 11. For each radio frequency circuit 02, an output end of the LO 11 is connected to a first input end of the frequency mixer 14.

On a transmit link of each radio frequency circuit 02, the DBB circuit 12 is connected to an input end of the TX ABB circuit 13, an output end of the TX ABB circuit 13 is connected to a second input end of the frequency mixer 14, an output end of the frequency mixer 14 is connected to an input end of the PA 15, and an output end of the PA 15 is connected to the antenna 16.

The following describes functions of the foregoing components.

The PLL circuit 10 is configured to output, to the LO 11, a first oscillation signal of a fixed clock frequency of each channel. The first oscillation signal may also be referred to as a local carrier signal.

The LO 11 is configured to: process the first oscillation signal, and output, to the frequency mixer 14, transmit oscillation signals of a plurality of local oscillation frequencies.

The DBB circuit 12 is configured to send a digital signal to the transmit link of the radio frequency circuit 02.

The TX ABB circuit 13 is configured to perform filtering and amplification processing on the digital signal from the DBB circuit 12.

The frequency mixer 14 is configured to: mix the transmit oscillation signal and a signal output by the TX ABB circuit 13, and output a mixed signal to the PA 15.

The PA 15 is configured to amplify the signal obtained through frequency mixing.

The antenna 16 is configured to transmit the signal amplified by the PA 15.

The following describes in detail a specific structure of a phase locked loop circuit based on FIG. 4. FIG. 4 is a diagram of a structure of a phase locked loop circuit. The phase locked loop circuit may be the phase locked loop circuit shown in FIG. 3. The phase locked loop circuit includes a phase detector 401, a filter 402, a ring oscillator 403, and a frequency divider 404. The phase detector 401 is configured to: compare a reference signal with a local carrier signal fed back by the frequency divider 404 to obtain a phase difference signal, and convert the phase difference signal into a voltage signal for outputting, where the reference signal may be a signal provided by a reference frequency source. The filter 402 filters the voltage signal. The ring oscillator 403 is configured to output a local carrier signal based on the filtered voltage signal, where the local carrier signal may be fed back to the phase detector 401 through the frequency divider 404, to form a closed loop feedback circuit.

The following describes a specific structure of the ring oscillator based on FIG. 5. FIG. 5 is a diagram of a structure of a ring oscillator according to an embodiment of this application. The ring oscillator may be the ring oscillator provided in FIG. 3 or FIG. 4. The ring oscillator may include at least three differential inverting amplifiers that are coupled in a ring. Each differential inverting amplifier includes a first input end and a second input end that are differential, and a first output end and a second output end that are differential, and the first output end and the second output end of each differential inverting amplifier are respectively coupled to a first input end and a second input end of a next adjacent differential inverting amplifier. The at least three differential inverting amplifiers include a first differential inverting amplifier 50, a first input end 501 of the first differential inverting amplifier 50 is coupled to a first output end 502 of the first differential inverting amplifier 50, and a second input end 503 of the first differential inverting amplifier 50 is coupled to a second output end 504 of the first differential inverting amplifier 50. A polarity of the first input end 501 and a polarity of the first output end 502 are a first polarity, a polarity of the second input end 503 and a polarity of the second output end 504 are a second polarity, and the first polarity is opposite to the second polarity.

The differential inverting amplifier may also be usually referred to as a differential amplifier, a differential amplification circuit, or the like. For example, it is assumed that differential signals input to the differential inverting amplifier are V_in+ and V_in−. In this case, differential signals V_o+ and V_o− output by the differential inverting amplifier may be represented as follows: V_o+=Av (V_in+−V_in−), and V_o−=−Av (V_in+−V_in−), where A_vindicates an amplification gain. It can be learned that when the gain A_vof the differential inverting amplifier is equal to 1, the differential inverting amplifier may be considered as an inverter without an amplification function. In this case, the differential inverting amplifier may also be referred to as a differential inverter or an inverter.

In addition, the at least three differential inverting amplifiers may include three differential inverting amplifiers, or may include more than three differential inverting amplifiers. For example, when the at least three differential inverting amplifiers include more than three differential inverting amplifiers, the at least three differential inverting amplifiers may include five differential inverting amplifiers, 10 differential inverting amplifiers, or more differential inverting amplifiers. The differential inverting amplifier may also be referred to as an inverting delay unit or an inverting amplifier. In FIG. 5, an example in which the at least three differential inverting amplifiers include three differential inverting amplifiers is used for description.

In addition, each differential inverting amplifier includes the first input end and the second input end that are differential, that is, the polarity of the first input end is opposite to the polarity of the second input end. For example, when the first input end is a positive electrode, the second input end is a negative electrode; or when the first input end is a negative electrode, the second input end is a positive electrode. Each differential inverting amplifier includes the first output end and the second output end that are differential, that is, the polarity of the first output end is opposite to the polarity of the second output end. For example, when the first output end is a positive electrode, the second output end is a negative electrode; or when the first output end is a negative electrode, the second output end is a positive electrode.

Moreover, the first polarity may be positive or negative, and the first polarity is opposite to the second polarity. For example, when the first polarity is positive, the second polarity is negative; or when the first polarity is negative, the second polarity is positive. For example, in a first possible implementation, the first polarity is positive, and the second polarity is negative, that is, the first input end 501 and the first output end 502 are positive electrodes, and the second input end 503 and the second output end 504 are negative electrodes. In a second possible implementation, the first polarity is negative, and the second polarity is positive, that is, the first input end 501 and the first output end 502 are negative electrodes, and the second input end 503 and the second output end 504 are positive electrodes. In FIG. 5, an example in which the first polarity is positive and the second polarity is negative is used.

It should be noted that an input end (including the first input end and the second input end that are differential) and an output end (including the first output end and the second output end that are differential) of the differential inverting amplifier are determined as positive or negative electrodes from a perspective of an electric potential. From a perspective of a phase, the input end and the output end are in-phase ends or inverting ends. The in-phase ends indicate that polarities of two ends (including any two of the first input end and the second input end that are differential, and the first output end and the second output end that are differential) are the same, and it may also be understood that signals corresponding to the two ends have a same phase, that is, the phase is 0 degrees or 180 degrees. The inverting ends indicate that polarities of the two ends are opposite, and it may also be understood that signals corresponding to the two ends have opposite phases, that is, one phase is 0 degrees, the other phase is 180 degrees, one of a positive electrode and a negative electrode indicates 0, and the other represents 180 degrees. For example, the positive electrode may be represented as 0, and the negative electrode may be represented as 180 degrees. Therefore, the positive electrode and the negative electrode are in opposite phases. For example, the first input end 501 and the first output end 502, and the second input end 503 and the second output end 504 shown in FIG. 5 are in-phase ends, and the first input end 501 and the second input end 503, and the first output end 502 and the second output end 504 are inverting ends.

In addition, the first output end and the second output end of each differential inverting amplifier in the at least three inverting amplifiers are respectively coupled to a first input end and a second input end of a next adjacent differential inverting amplifier. For example, when the at least three inverting amplifiers include three differential inverting amplifiers, the at least three differential inverting amplifiers may further include a second differential inverting amplifier 51 and a third differential inverting amplifier 52. The first differential inverting amplifier 50 is coupled between the second differential inverting amplifier 51 and the third differential inverting amplifier 52, a first output end and a second output end of the second differential inverting amplifier 51 are respectively coupled to the first input end and the second input end of the first differential inverting amplifier 50, the first output end and the second output end of the first differential inverting amplifier 50 are coupled to a first input end and a second input end of the third differential inverting amplifier 52, and a first output end and a second output end of the third differential inverting amplifier 52 are coupled to a first input end and a second input end of the second differential inverting amplifier 51.

In a possible embodiment, if only one differential inverting amplifier in the at least three differential inverting amplifiers is in-phase coupled to an adjacent differential inverting amplifier, all other differential inverting amplifiers other than the differential inverting amplifier in the at least three differential inverting amplifiers are reversely coupled to adjacent differential inverting amplifiers. For example, as shown in FIG. 5, the third differential inverting amplifier 52 and the second differential inverting amplifier 51 are in-phase coupled, that is, the first output end (positive electrode) of the third differential inverting amplifier 52 is coupled to the first input end (positive electrode) of the second differential inverting amplifier 51, and the second output end (negative electrode) of the third differential inverting amplifier 52 is coupled to the second input end (negative electrode) of the second differential inverting amplifier 51. The second differential inverting amplifier 51 is reversely coupled to the first differential inverting amplifier 50, and the first differential inverting amplifier 50 is also reversely coupled to the third differential inverting amplifier 52, that is, the first output end (negative electrode) of the second differential inverting amplifier 51 is coupled to the first input end 501 (positive electrode) of the first differential inverting amplifier 50, the second output end (positive electrode) of the second differential inverting amplifier 51 is coupled to the second input end 503 (negative electrode) of the first differential inverting amplifier 50, the second output end 504 (negative electrode) of the first differential inverting amplifier 50 is coupled to the first input end (positive electrode) of the third differential inverting amplifier 52, and the first output end 502 (positive electrode) of the first differential inverting amplifier 50 is coupled to the second input end (negative electrode) of the third differential inverting amplifier 52. In FIG. 5, an example in which the third differential inverting amplifier 52 is in-phase coupled to the second differential inverting amplifier 51 is used.

In another possible embodiment, if only one differential inverting amplifier in the at least three differential inverting amplifiers is reversely coupled to an adjacent differential inverting amplifier, all other differential inverting amplifiers other than the differential inverting amplifier in the at least three differential inverting amplifiers are in-phase coupled to adjacent differential inverting amplifiers. For example, FIG. 6 is a diagram of a structure of another ring oscillator according to an embodiment of this application. The ring oscillator may include a first differential inverting amplifier 50, a second differential inverting amplifier 51, and a third differential inverting amplifier 52 that are coupled in a ring. The third differential inverting amplifier 52 is reversely coupled to the second differential inverting amplifier 51, that is, a first output end (positive electrode) of the third differential inverting amplifier 52 is coupled to a second input end (negative electrode) of the second differential inverting amplifier 51, and a second output end (negative electrode) of the third differential inverting amplifier 52 is coupled to a first input end (positive electrode) of the second differential inverting amplifier 51. The second differential inverting amplifier 51 is in-phase coupled to the first differential inverting amplifier 50, and the first differential inverting amplifier 50 is also in-phase coupled to the third differential inverting amplifier 52, that is, a first output end (negative electrode) of the second differential inverting amplifier 51 is coupled to a first input end 501 (negative electrode) of the first differential inverting amplifier 50, a second output end (positive electrode) of the second differential inverting amplifier 51 is coupled to a second input end 503 (positive electrode) of the first differential inverting amplifier 50, a second output end 504 (positive electrode) of the first differential inverting amplifier 50 is coupled to a first input end (positive electrode) of the third differential inverting amplifier 52, and a first output end 502 (negative electrode) of the first differential inverting amplifier 50 is coupled to a second input end (negative electrode) of the third differential inverting amplifier 52. In FIG. 6, an example in which the third differential inverting amplifier 52 is reversely coupled to the second differential inverting amplifier 51, a first polarity is negative electrode, and a second polarity is positive is used.

In embodiments of this application, for each differential inverting amplifier, because a signal at the first input end and a signal at the second input end have equal magnitudes and opposite polarities, the signal at the first input end and the signal at the second input end may be referred to as differential signals. In actual application, a difference between the signal at the first input end and the signal at the second input end is used as an input signal, so that interference caused by external common mode noise to the input signal can be completely offset, thereby improving anti-interference performance of the ring oscillator.

FIG. 7 is a diagram of circuit simulation according to an embodiment of this application. (a) in FIG. 7 is a diagram of a differential oscillation waveform of the differential oscillator shown in FIG. 2, and (b) in FIG. 7 is a diagram of a differential oscillation waveform of the ring oscillator shown in FIG. 5. A horizontal coordinate indicates time (nanosecond/ns), and a vertical coordinate indicates a voltage (millivolt/mV). As shown in (a) in FIG. 7, a curve S1 and a curve S2 are differential oscillation waveforms of the differential oscillator in one time period, and a waveform conversion rate is approximately 0.7 ns in one oscillation cycle. As shown in (b) in FIG. 7, a curve S3 and a curve S4 are differential oscillation waveforms of the ring oscillator in one time period, and a waveform conversion rate is approximately 0.6 ns in one oscillation cycle. It can be learned from FIG. 7 that, compared with the differential oscillator shown in FIG. 2, the ring oscillator shown in FIG. 5 has a higher conversion rate of a differential oscillation waveform and better symmetry of the differential oscillation waveform.

FIG. 8 is a diagram of phase noise simulation according to an embodiment of this application. A horizontal coordinate indicates a frequency (hertz/Hz), and a vertical coordinate indicates phase noise (decibel/dB). S801 is a change trend of phase noise of the differential oscillator shown in FIG. 2 at different frequencies, and S802 is a change trend of phase noise of the ring oscillator shown in FIG. 5 at different frequencies. At a frequency of 104 Hz, phase noise of the differential oscillator shown in FIG. 2 is-38 decibels, and phase noise of the ring oscillator shown in FIG. 5 is −43 decibels. In other words, the phase noise of the ring oscillator shown in FIG. 5 is −5 decibels less than the phase noise of the differential oscillator shown in FIG. 2. It can be seen from FIG. 8 that the phase noise of the ring oscillator shown in FIG. 5 is less than the phase noise of the differential oscillator shown in FIG. 2. In other words, compared with the differential oscillator shown in FIG. 2, the ring oscillator provided in embodiments of this application has lower phase noise and better performance.

In a possible embodiment, as shown in FIG. 9, the ring oscillator may further include a first switch Q1 and a second switch Q2. The first switch Q1 is coupled between the first input end 501 of the first differential inverting amplifier 50 and the first output end 502 of the first differential inverting amplifier 50, and the second switch Q2 is coupled between the second input end 503 of the first differential inverting amplifier 50 and the second output end 504 of the first differential inverting amplifier 50. The first switch Q1 and the second switch Q2 are switched, for example, the first switch Q1 and the second switch Q2 are simultaneously turned on or off, to control the ring oscillator to operate in a low phase noise mode or an anti-interference mode.

FIG. 9 is a diagram of a structure of a ring oscillator according to an embodiment of this application. The ring oscillator may include the first differential inverting amplifier 50, the second differential inverting amplifier 51, the third differential inverting amplifier 52, the first switch Q1, and the second switch Q2 that are coupled in a ring. The first input end 501 of the first differential inverting amplifier 50 is coupled to the first output end 502 of the first differential inverting amplifier 50 through the first switch Q1, and the second input end 503 of the first differential inverting amplifier 50 is coupled to the second output end 504 of the first differential inverting amplifier 50 through the second switch Q2. In an operating process of the ring oscillator, if the ring oscillator needs to operate in a low phase noise mode, the ring oscillator may be controlled to operate in the low phase noise mode by simultaneously turning on the first switch Q1 and the second switch Q2. In this case, a structure of the ring oscillator is the same as the structure of the ring oscillator shown in FIG. 5. If the ring oscillator needs to operate in an anti-interference mode, the ring oscillator may be controlled to operate in the anti-interference mode by simultaneously turning off the first switch Q1 and the second switch Q2. In this embodiment, the ring oscillator can be controlled to adapt to more operating modes by switching the first switch and the second switch, thereby improving utilization of the ring oscillator. In FIG. 9, an example in which a first polarity is positive and a second polarity is negative is used.

In a possible embodiment, the at least three differential inverting amplifiers may further include at least one fourth differential inverting amplifier 53, the at least one fourth differential inverting amplifier 53 is coupled between the second differential inverting amplifier 51 and the third differential inverting amplifier 52, a first input end 531 of the at least one fourth differential inverting amplifier 53 is coupled to a first output end 532 of the at least one fourth differential inverting amplifier 53, a second input end 533 of the at least one fourth differential inverting amplifier 53 is coupled to a second output end 534 of the at least one fourth differential inverting amplifier 53, a polarity of the first input end 531 of the at least one fourth differential inverting amplifier 53 and a polarity of the first output end 532 of the at least one fourth differential inverting amplifier 53 are the first polarity, a polarity of the second input end 533 of the at least one fourth differential inverting amplifier 53 and a polarity of the second output end 534 of the at least one fourth differential inverting amplifier 53 are the second polarity, and the first polarity is opposite to the second polarity.

The at least one fourth differential inverting amplifier 53 may include one fourth differential inverting amplifier 53, or may include a plurality of fourth differential inverting amplifiers 53. For example, when the at least one fourth differential inverting amplifier 53 includes a plurality of fourth differential inverting amplifiers 53, the at least one fourth differential inverting amplifier 53 may include two, eight, or 10 fourth differential inverting amplifiers. This is not specifically limited in embodiments of this application. For ease of understanding, in FIG. 10 and the following embodiments, an example in which the at least one fourth differential inverting amplifier 53 includes one fourth differential inverting amplifier 53 is used.

In a possible embodiment, when the at least one fourth differential inverting amplifier 53 includes one fourth differential inverting amplifier 53, in a first possible implementation, the first polarity is positive, and the second polarity is negative, that is, the first input end 531 of the fourth differential inverting amplifier 53 and the first output end 532 of the fourth differential inverting amplifier 53 are positive electrodes, and the second input end 533 of the fourth differential inverting amplifier 53 and the second output end 534 of the fourth differential inverting amplifier 53 are negative electrodes. In a second possible implementation, the first polarity is negative, and the second polarity is positive, that is, the first input end 531 of the fourth differential inverting amplifier 53 and the first output end 532 of the fourth differential inverting amplifier 53 are positive electrodes, and the second input end 533 of the fourth differential inverting amplifier 53 and the second output end 534 of the fourth differential inverting amplifier 53 are negative electrodes.

The fourth differential inverting amplifier 53 is coupled between the second differential inverting amplifier 51 and the third differential inverting amplifier 52. For example, in a possible implementation, the fourth differential inverting amplifier 53 may be coupled between the second differential inverting amplifier 51 and the first differential inverting amplifier 50. In this case, a first output end and a second output end of the second differential inverting amplifier 51 are coupled to the first input end and the second input end of the fourth differential inverting amplifier 53, and the first output end and the second output end of the fourth differential inverting amplifier 53 are coupled to a first input end and a second input end of the first differential inverting amplifier 50. In another possible implementation, the fourth differential inverting amplifier 53 may be alternatively coupled between the first differential inverting amplifier 50 and the third differential inverting amplifier 52. In this case, a first output end and a second output end of the first differential inverting amplifier 50 are coupled to the first input end and the second input end of the fourth differential inverting amplifier 53, and the first output end and the second output end of the fourth differential inverting amplifier 53 are coupled to a first input end and a second input end of the third differential inverting amplifier 52. In the following embodiments, an example in which the fourth differential inverting amplifier 53 is coupled between the first differential inverting amplifier 50 and the third differential inverting amplifier 52 is used for description.

For example, FIG. 10 is a diagram of a structure of a ring oscillator according to an embodiment of this application. The ring oscillator may include a first differential inverting amplifier 50, a second differential inverting amplifier 51, a third differential inverting amplifier 52, a fourth differential inverting amplifier 53, a first switch Q1, and a second switch Q2 that are coupled in a ring. The third differential inverting amplifier 52 is in-phase coupled to the second differential inverting amplifier 51, and other adjacent differential inverting amplifiers are reversely coupled to each other, that is, a first output end (positive electrode) of the third differential inverting amplifier 52 is coupled to a first input end (positive electrode) of the second differential inverting amplifier 51, a second output end (negative electrode) of the third differential inverting amplifier 52 is coupled to an input end (negative electrode) of the second differential inverting amplifier 51, a first output end (positive electrode) of the second differential inverting amplifier 51 is coupled to a second input end 503 (negative electrode) of the first differential inverting amplifier 50, a second output end (negative electrode) of the second differential inverting amplifier 51 is coupled to a first input end 501 (positive electrode) of the first differential inverting amplifier 50, a first output end 502 (positive electrode) of the first differential inverting amplifier 50 is coupled to a second input end 533 (negative electrode) of the fourth differential inverting amplifier 53, a second output end 504 (negative electrode) of the first differential inverting amplifier 50 is coupled to a first input end 531 (positive electrode) of the fourth differential inverting amplifier 53, a first output end 532 (positive electrode) of the fourth differential inverting amplifier 53 is coupled to a first input end (negative electrode) of the third differential inverting amplifier 52, and a second output end 534 (negative electrode) of the fourth differential inverting amplifier 53 is coupled to a second input end (positive electrode) of the third differential inverting amplifier 52. The first input end 501 of the first differential inverting amplifier 50 is coupled to the first output end 502 of the first differential inverting amplifier 50 through the first switch Q1, and the second input end 503 of the first differential inverting amplifier 50