212 may be divided into channel regions 212C underlying the dummy gate stacks 220 and source/drain regions 212SD that do not underlie the dummy gate stacks 220. The channel regions 212C are adjacent the source/drain regions 212SD. As shown in FIG. 7, the channel region 212C is disposed between two source/drain regions 212SD along the X direction.

The formation of the dummy gate stack 220 may include deposition of layers in the dummy gate stack 220 and patterning of these layers. Referring to FIG. 6, a dummy dielectric layer 216, a dummy electrode layer 218, and a gate-top hard mask layer 222 may be blanketly deposited over the WIP structure 200. The dummy dielectric layer 216 may be formed on the fin-shaped structure 212 using a chemical vapor deposition (CVD) process, an ALD process, an oxygen plasma oxidation process, or other suitable processes. In the depicted embodiment, the dummy dielectric layer 216 is formed using an oxygen plasma oxidation process that substantially oxidize the silicon liner 207 to form the dummy dielectric layer 216. In some instances, the dummy dielectric layer 216 may include silicon oxide. Thereafter, the dummy electrode layer 218 may be deposited over the dummy dielectric layer 216 using a CVD process, an ALD process, or other suitable processes. In some instances, the dummy electrode layer 218 may include polysilicon. For patterning purposes, the gate-top hard mask layer 222 may be deposited on the dummy electrode layer 218 using a CVD process, an ALD process, or other suitable processes. The gate-top hard mask layer 222, the dummy electrode layer 218 and the dummy dielectric layer 216 may then be patterned to form the dummy gate stack 220, as shown in FIG. 7. For example, the patterning process may include a lithography process (e.g., photolithography or e-beam lithography) and an etching process. The lithography process may further include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, and/or combinations thereof. The photolithography process forms a patterned photoresist layer. The patterned photoresist layer is then applied as an etch mask in the etching process to pattern the gate-top hard mask layer 222, the dummy electrode layer 218 and the dummy dielectric layer 216. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and/or other etching methods. In some embodiments, the gate-top hard mask layer 222 may include a silicon oxide layer 223 and a silicon nitride layer 224 over the silicon oxide layer 223. As shown in FIG. 7, the dummy gate stack 220 is patterned such that it is only disposed over the channel region 212C, not disposed over the source/drain region 212SD.

Referring to FIGS. 1 and 8, method 100 includes a block 112 where a gate spacer layer 226 is deposited over the WIP structure 200, including over the dummy gate stack 220. In some embodiments, the gate spacer layer 226 is deposited conformally over the WIP structure 200, including over top surfaces and sidewalls of the dummy gate stack 220. The term “conformally” may be used herein for case of description of a layer having substantially uniform thickness over various regions. The gate spacer layer 226 may be a single layer or a multi-layer. The at least one layer in the gate spacer layer 226 may include silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or silicon nitride. The gate spacer layer 226 may be deposited over the dummy gate stack 220 using processes such as, a CVD process, a subatmospheric CVD (SACVD) process, an ALD process, or other suitable process.

Referring to FIGS. 1, 9 and 10, method 100 includes a block 114 where a source/drain region 212SD of the fin-shaped structure 212 is anisotropically recessed to form a source/drain trench 228. The anisotropic etch may include a dry etch or a suitable etch process that etches the source/drain regions 212SD and a portion of the substrate 202 below the source/drain regions 212SD. The resulting source/drain trench 228 extends vertically through the depth of the stack 204 and partially into the substrate 202. An example dry etch process for block 110 may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF₄, SF₆, CH₂F₂, CHF₃, and/or C₂F₆), a chlorine-containing gas (e.g., Cl₂, CHCl₃, CCl₄, and/or BCl₃), a bromine-containing gas (e.g., HBr and/or CHBr₃), an iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof. As illustrated in FIG. 9, the source/drain regions 212SD of the fin-shaped structure 212 are recessed to expose sidewalls of the sacrificial layers 206 and the channel layers 208. Because the source/drain trenches 228 extend below the stack 204 into the substrate 202, the source/drain trenches 228 include bottom surfaces and lower sidewalls defined in the substrate 202. Reference is made to FIG. 10, which includes a fragmentary cross-sectional view across two adjacent source/drain regions 212SD. As shown in FIG. 10, over the source/drain regions 212SD, the majority of the fin-shaped structure 212 is etched away and a top surface of the base fin structure 212B is exposed in the source/drain region 212SD. Because the gate spacer layer 226 etches at a slower rate than the fin-shaped structure 212, the gate spacer layer 226 in the source/drain region 212SD rises above the top surface of the base fin structure 212B. In some instances, a top surface of the protection layer 215 under the gate spacer layer 226 may also be higher than the top surface of the base fin structure 212B in the source/drain region 212SD.

Referring to FIGS. 1, 11 and 12, method 100 includes a block 116 where the plurality of channel layers 208 in the channel regions are released as channel members 2080. After the formation of the source/drain trench 228, the sacrificial layers 206 interleaving the channel layers 208 in the channel region 212C are selectively removed. The selective removal of the sacrificial layers 206 releases the channel layers 208 (shown in FIG. 9) to form channel members 2080 shown in FIG. 11. The selective removal of the sacrificial layers 206 forms spaces between and around adjacent channel members 2080. The selective removal of the sacrificial layers 206 may be implemented by selective dry etch, selective wet etch, or other selective etch processes. An example selective dry etching process may include use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. An example selective wet etching process may include an APM etch (e.g., ammonia hydroxide-hydrogen peroxide-water mixture). At block, the source/drain regions 212SD, shown in FIG. 12, are not substantially etched.

Referring to FIGS. 1, 13 and 14, method 100 incudes a block 118 where a dummy layer 230 is deposited around the channel members 2080 and over the source/drain trenches 228. The dummy layer 230 may include silicon oxide and may be deposited using one or more deposition methods that are performed under low temperature (i.e., lower than about 100° C.). In an example process depicted in FIGS. 13 and 14, a first dummy layer 230-1 is first deposited using atomic layer deposition (ALD) at a temperature between about 10° C. and about 30° C. to reach a thickness between about 10 Å and about 20 Å. The ALD deposition of the first dummy layer 230-1 is conformal and functions to reduce loading effect caused by width variation in the active region. Then a second dummy layer 230-2 is deposited using flowable chemical vapor deposition (FCVD) at a temperature between about 20° C. and about 100° C. to reach a thickness between about 70 Å and about 120 Å. In some instances, reactants used in the FCVD process may include trisilylamine (TSA), ammonia, oxygen, or a combination thereof. The presence of the amine or ammonia improves bonding and prevents void and seam. To replace nitrogen atoms in the deposited second dummy layer 230-2, ozone may be used in an oxidation process at a temperature between about 8° C. and about 40° C. To improve quality of the second dummy layer 230-2 and to remove silicon-hydrogen bond, an ultraviolet (UV) curing process may also be performed after the oxidation process. The UV curing process may be performed at a temperature between about 8° C. and about 40° C. The first dummy layer 230-1 and the second dummy layer 230-2 shown in FIGS. 13 and 14 may be collectively referred to as the dummy layer 230. In some alternative embodiments, the dummy layer 230 may be formed using ALD only. For case of illustration, the dummy layer 230 is show as a single layer in FIGS. 15-18. The low-temperature deposition process prevents damages to the channel members 2080 and still ensures consistency for uniform etching characteristics. As shown in FIG. 13, the dummy layer 230 fills the space among the channel members 2080 and covers end sidewalls of the channel members 2080. Additionally, the dummy layer 230 is in direct contact with a sidewall of the gate spacer layer 226, a sidewall of the protection layer 215, and a top surface of the substrate 202. Reference is made to FIG. 14, which includes a fragmentary cross-sectional view across two adjacent source/drain regions 212SD. As shown in FIG. 14, the dummy layer 230 extends conformally over the isolation feature 214, sidewalls of the protection layer 215, sidewalls of the gate spacer layer 226, and top surfaces of the gate spacer layer 226. Depending on the design, the channel members 2080 may take form of nanowires, nanosheets, or other nanostructures.

Referring to FIGS. 1, 15, 16, and 17, method 100 includes a block 120 where inner spacer features 234 are formed. While not shown explicitly, operation at block 120 may include selective and partial removal of the dummy layer 230 to form inner spacer recesses 232 (shown in FIG. 15), deposition of inner spacer material over the WIP structure 200, and etching back the inner spacer material to form inner spacer features 234 in the inner spacer recesses 232 (shown in FIG. 16). Referring to FIG. 15, the dummy layers 230 are selectively and partially recessed to form inner spacer recesses 232 while the gate spacer layer 226, the dummy gate stack 220, the exposed portion of the substrate 202, and the channel layers 208 are substantially unetched. In an embodiment where the channel layers 208 consist essentially of silicon (Si) and the dummy layers 230 are formed of silicon oxide, the selective recess of the dummy layer 230 may be performed using a selective wet etch process or a selective dry etch process. An example selective dry etching process may include use of carbon tetrafluoride (CF₄), nitrogen trifluoride (NF₃), hydrogen (H₂), or a mixture thereof. An example selective wet etching process may include use of hydrofluoric acid, ammonium fluoride, or a mixture thereof.

After the inner spacer recesses 232 are formed, an inner spacer material is deposited over the WIP structure 200, including over the inner spacer recesses 232. The inner spacer material may include metal oxides, silicon oxide, silicon oxycarbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbonitride, or a low-k dielectric material. The metal oxides may include aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, or other suitable metal oxide. While not explicitly shown, the inner spacer material may be a single layer or a multilayer. In some implementations, the inner spacer material may be deposited using CVD, PECVD, SACVD, ALD or other suitable methods. The inner spacer material is deposited into the inner spacer recesses 232 as well as over the sidewalls of the channel layers 208 exposed in the source/drain trenches 228. Referring to FIG. 16, the deposited inner spacer material is then etched back to remove the inner spacer material from the sidewalls of the channel members 2080 to form the inner spacer features 234 in the inner spacer recesses 232. Reference is made to FIG. 17, which includes a fragmentary cross-sectional view across two adjacent source/drain regions 212SD. As shown in FIG. 17, the etch back may not completely remove a sidewall portion 2340 of the inner spacer feature 234 along sidewalls of the isolation feature 214.

Referring to FIGS. 1, 18 and 19, method 100 includes a block 122 where a source/drain feature 240 is formed over the source/drain region 212D. While not explicitly shown, before any of the epitaxial layers are formed, method 100 may include a cleaning process to clean surfaces of the WIP structure 200. The cleaning process may include a dry clean, a wet clean, or a combination thereof. In some examples, the wet clean may include use of standard clean 1 (RCA SC-1, a mixture of deionized (DI) water, ammonium hydroxide, and hydrogen peroxide), standard clean 2 (RCA SC-2, a mixture of DI water, hydrochloric acid, and hydrogen peroxide), SPM (a sulfuric peroxide mixture), and or hydrofluoric acid for oxide removal. The dry clean process may include helium (He) and hydrogen (H₂) treatment. The hydrogen treatment may convert silicon on the surface to silane (SiH₄), which may be pumped out for removal.

Reference is made to FIG. 18. The source/drain feature 240 may be an n-type source/drain feature 240N or a p-type source/drain feature 240P. When the source/drain feature 240 is an n-type source/drain feature 240N, it includes a bottom epitaxial feature 236 and at least one n-type doped epitaxial layer 238N over the bottom epitaxial feature 236. The at least one n-type doped epitaxial layer 238N may include an n-type dopant, such as phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. When the source/drain feature 240 is a p-type source/drain feature 240P, it includes a bottom epitaxial feature 236 and at least one p-type doped epitaxial layer 238P over the bottom epitaxial feature 236. The at least one p-type doped epitaxial layer 238P may include a p-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb). In some embodiments, the bottom epitaxial feature 236 may include an undoped semiconductor material, such as undoped silicon (Si) or undoped silicon germanium (SiGe). As used herein, the undoped semiconductor material is regarded as undoped when it is not intentionally doped. In some alternative embodiments, the bottom epitaxial feature 236 may include a counter dopant to reduce leakage into the bulk substrate 202. For example, the bottom epitaxial feature 236 in the n-type source/drain feature 240N may include a p-type dopant, such as boron (B). For another example, the bottom epitaxial feature 236 in the p-type source/drain feature 240P may include an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb). The source/drain feature 240 may be formed using vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), or molecular beam cpitaxy (MBE). Doping of the source/drain features 240 may be achieved with in-situ doping.

Reference is made to FIG. 19, which includes a fragmentary cross-sectional view across two adjacent source/drain regions 212SD. In some embodiments represented in FIG. 19, an n-type source/drain feature 240N may be adjacent a p-type source/drain feature 240P. Each of the n-type source/drain feature 240N and the p-type source/drain feature 240P may be in direct contact with a top surface of the base fin structure 212B, a sidewall of the protection layer 215, and a sidewall of the gate spacer layer 226.

Referring to FIGS. 1 and 20-23, method 100 includes a block 124 where the dummy gate stack 220 and the dummy layer 230 are replaced with a gate structure 250. Operations at block 124 may include deposition of a contact etch stop layer (CESL) 242 over the source/drain features 240 (shown in FIG. 20), deposition of an interlayer dielectric layer 244 over the CESL 242 (shown in FIG. 20), removal of the dummy gate stack 220 and the dummy layer 230 (shown in FIGS. 20 and 21), and deposition of the gate structure 250 to wrap around each of the channel members 2080 (shown in FIGS. 22 and 23). Referring to FIG. 20, the CESL 242 is deposited over the WIP structure 200, including over the source/drain feature 240. The CESL 242 may include silicon nitride or aluminum nitride. In some implementations, the CESL 242 may be deposited using CVD or atomic layer deposition (ALD). The ILD layer 244 is then deposited over the CESL 242. In some embodiments, the ILD layer 244 includes materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. The ILD layer 244 may be deposited using CVD, flowable CVD (FCVD), spin-on coating, or a suitable deposition technique. After the deposition of the ILD layer 244, the WIP structure 200 may be planarized by a planarization process to expose the dummy gate stack 220. For example, the planarization process may include a chemical mechanical planarization (CMP) process. Exposure of the dummy gate stack 220 allows the removal of the dummy gate stack 220. The removal of the dummy gate stack 220 may include one or more etching processes that are selective to the material of the dummy gate stack 220. For example, the removal of the dummy gate stack 220 may be performed using as a selective wet etch, a selective dry etch, or a combination thereof that is selective to the dummy gate stack 220. After the removal of the dummy gate stack 220, the dummy layer 230 in the channel region 212C is exposed. A separate etch process may be performed to selectively remove the dummy layer 230 in the channel region 212C. After the selective removal of the dummy layer 230, the channel members 2080 in the channel region 212C are once again exposed. In some embodiments represented in FIG. 21, while the removal of the dummy gate stack 220 substantially removes the protection layer 215 over top surfaces of the topmost channel members 2080, a bottom protection layer 2150 may remain. To prevent damages to the channel members 2080, the removal of the dummy gate stack 220 is only performed until the topmost channel members 2080 are no longer covered by the protection layer 215. However, the protection layer 215 over the isolation feature 214, especially at the corner of the base fin structure 212B and the isolation feature 214, may undergo slower etching and may remain, forming the bottom protection layer 2150. It is noted that the bottom protection layer 2150 may be thicker around the corner of the base fin structure 212B and the isolation feature 214.

After the release of the channel members 2080, the gate structure 250 is formed to wrap around each of the channel members 2080 as shown in FIGS. 22 and 23. While not explicitly shown, the gate structure 250 includes an interfacial layer interfacing the channel members 2080 and the substrate 202 in the channel region 212C, a gate dielectric layer over the interfacial layer, and a gate electrode layer over the gate dielectric layer. The interfacial layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable method. The gate dielectric layer may include a high-k dielectric material, such as hafnium oxide. Alternatively, the gate dielectric layer may include other high-K dielectric materials, such as titanium oxide (TiO₂), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta₂O₅), hafnium silicon oxide (HfSiO₄), zirconium oxide (ZrO₂), zirconium silicon oxide (ZrSiO₂), lanthanum oxide (La₂O₃), aluminum oxide (Al₂O₃), zirconium oxide (ZrO), yttrium oxide (Y₂O₃), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), combinations thereof, or other suitable material. The gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and/or other suitable methods.

The gate electrode layer of the gate structure 250 may include a multi-layer structure, such as various combinations of a metal layer with a selected work function to enhance the device performance (work function metal layer), a liner layer, a wetting layer, an adhesion layer, a metal alloy or a metal silicide. By way of example, the gate electrode layer may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metal materials or a combination thereof. In various embodiments, the gate electrode layer may be formed by ALD, PVD, CVD, c-beam evaporation, or other suitable process. In various embodiments, a CMP process may be performed to remove excessive metal, thereby providing a substantially planar top surface of the gate structure. The gate structure includes portions that interpose between channel members 2080 in the channel region 212C. In some embodiments, the gate structure 250 may include a p-type gate structure portion and an n-type gate structure portion. The p-type gate structure portion includes p-type work function metal layers disposed closer to the channel members 2080. The n-type gate structure portion includes n-type work function metal layers disposed closer to the channel members 2080. The gate structure 250 in FIG. 23 includes the p-type gate structure portion and the n-type gate structure portion disposed side-by-side. As indicated by a dotted line in FIG. 23, the p-type gate structure portion wraps around a stack of channel members 2080 and the n-type gate structure portion wraps around another stack of channel members 2080. In some embodiments represented in FIG. 23, the gate structure 250 is disposed over and in contact with the bottom protection layer 2150.

In some embodiments represented in FIG. 22, dielectric gate structures 270 may be formed to isolate the semiconductor device 200 from adjacent devices along the gate-length direction (i.e., the Y direction). To form the dielectric gate structures 270, a trench recess is formed to vertically extend into the base fin structure 212B. A dielectric material is deposited over the trench recess and then planarized to for the dielectric gate structures 270. In some instances, the dielectric gate structures 270 may include silicon nitride, silicon oxycarbonitride, or a combination thereof. In some embodiments represented in FIG. 23, dielectric fins 280 may be formed to isolate the gate structure 250 from adjacent devices along the gate-width direction (i.e., the X direction). In some instances, the dielectric fins 280 may include silicon nitride, silicon oxycarbonitride, or a combination thereof.

Referring to FIGS. 1 and 24, method 100 includes a block 126 where further processes are performed. Such further processes may include, for example, formation of a source/drain contact 258 to the source/drain feature 240 (including the n-type source/drain feature 240N and the p-type source/drain feature 240P). To form the source/drain contact 258, a contact opening is formed through the CESL 242 and the ILD 244 to expose the source/drain feature 240. The source/drain contact 258 includes an silicide feature 254 to interface the source/drain feature 240 and a metal fill layer 256 disposed over the silicide feature 254. In an example process, a silicide feature 254 is first formed over the exposed surface of the source/drain feature 240 and then a metal fill layer 256 is deposited over the silicide feature 254. In some implementations, the silicide feature 254 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) and the metal fill layer 256 may include cobalt (Co), tungsten (W), or copper (Cu).

Method 100 includes block 108 to form the protection layer 215 on top surfaces of the isolation feature 214. The protection layer 215 formed in method 100 protects the top surfaces of the isolation feature 214 but may not protect sidewalls of the isolation feature 214. Method 300 in FIG. 25 includes operations that replace block 108 such that the protection layer 215 includes a sidewall protection layer 215S to partially cover sidewalls of the isolation feature 214.

Referring to FIGS. 25 and 26, method 300 includes a block 302 where a sacrificial liner 211 is deposited over the fin-shaped structure 212 and the isolation feature 214. The sacrificial liner 211 is formed of a dielectric material different from that of the isolation feature 214 and a mask layer 213 to be deposited over the sacrificial liner 211. In one embodiment, the sacrificial liner 211 includes aluminum oxide. At block 302, the sacrificial liner 211 may be conformally deposited over the isolation feature 214 and surfaces of the fin-shaped structures 212 using CVD or ALD. In one embodiment, the sacrificial liner 211 is deposited using ALD.

Referring to FIGS. 25 and 26, method 300 includes a block 304 where a mask layer 213 is deposited over top facing surfaces of the sacrificial liner 211. In some embodiments, the mask layer 213 includes silicon nitride. In some embodiments represented in FIG. 26, the mask layer 213 may be deposited on top facing surfaces of the sacrificial liner 211 using a combination of a deposition process and an etch back process, similar to what is used to deposit the protection layer 215 at block 108 of method 100. In some instances, the mask layer 213 may be deposited using sputtering. That is, the mask layer 213 does not cover the sacrificial liner 211 disposed along sidewalls of the fin-shaped structures 212.

Referring to FIGS. 25, 27 and 28, method 300 includes a block 306 where the WIP structure 200 is etched to form a crevice 2140 between the base fin structure 212B and the isolation feature 214. Operations at block 306 may include selective etching of the sacrificial liner 211 to expose a portion of the isolation feature 214 (shown in FIG. 27) and anisotropic etching of the isolation feature 214 to form the crevice 2140 (shown in FIG. 28). Referring to FIG. 27, the sacrificial liner 211 may be subject to a selective etch process such that portions of the sacrificial liner 211 not covered by the mask layer 213 are selectively removed. An example selective etch process may include use of plasma of boron trichloride (BCl₃) and chlorine (Cl₂), an ammonium hydroxide (NH₄OH) solution, or a mixture of ammonium hydroxide, hydrogen peroxide and water. When the ammonium hydroxide solution or a mixture containing it is used, the process temperature may be greater than room temperature but lower than a boiling point of water, such as between 45° C. and about 70° C. As shown in FIG. 27, the removal of the sacrificial liner 211 along sidewalls of the fin-shaped structures 212 exposes a portion of the isolation feature 214 near the base fin structures 212B. Referring to FIG. 28, with the portions of the isolation feature 214 exposed, an anisotropic etch process is performed to etch the isolation feature 214 until the crevices 2140 are formed. The anisotropic etch process may include a dry etch process that implements an oxygen-containing gas, a fluorine-containing gas (e.g., CF₄, SF₆, CH₂F₂, CHF₃, and/or C₂F₆), a chlorine-containing gas (e.g., Cl₂, CHCl₃, CCl₄, and/or BCl₃), a bromine-containing gas (e.g., HBr and/or CHBr₃), an iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof.

Referring to FIGS. 25 and 29, method 300 includes a block 308 where the sacrificial liner 211 and the mask layer 213 are selectively removed. In some embodiments, a wet etch process may be used to remove both the sacrificial liner 211 and the mask layer 213 over the sacrificial liner 211. In some instances, the wet etch process may include use of an ammonium hydroxide (NH₄OH) solution or a mixture of ammonium hydroxide, hydrogen peroxide and water at a process temperature greater than room temperature but lower than a boiling point of water, such as between 45° C. and about 70° C.

Referring to FIGS. 25, 29 and 30, method 300 includes a block 310 where the protection layer 215 is deposited over the fin-shaped structure 212 and the isolation feature 214. After the removal of the sacrificial liner 211 and the mask layer 213, the protection layer 215 may be deposited on top facing surfaces of the fin-shaped structures 212 and the isolation feature 214. As shown in FIG. 29, the protection layer 215 is also deposited into the crevices 2140 (shown in FIG. 28), thereby forming a sidewall protection layer 215S. The formation and the composition of the protection layer 215 is similar to the protection layer 215 described above in block 108. Detailed description of the protection layer 215 is omitted here for brevity.

Reference is made to FIG. 30, which includes a fragmentary cross-sectional view across two adjacent source/drain regions 212SD. As shown in FIG. 30, the sidewall protection layer 215S extends along the base fin structure 212B is present and visible in the source/drain regions 212SD.

FIGS. 31-34 illustrates fragmentary cross-sectional views of the WIP structure 200 undergoing operations at blocks 124 and 126 when the sidewall protection layer 215S is present. Referring to FIG. 31, after the dummy gate stack 220 and the dummy layer 230 over the channel regions 212C are removed, the channel members 2080 are released again. The sidewall protection layer 215S extends along a top portion of the base fin structure 212B to protect the isolation feature 214 from undesirable damages. Referring to FIGS. 32 and 33, the sidewall protection layer 215S remain present in in the source/drain region 212SD and the channel region 212C to protect the sidewall of the isolation feature 214 after formation of the source/drain feature 240 and the gate structure 250. The protection layer 215 may be largely removed during the removal of the dummy layer 230 at block 124, leaving behind only the bottom protection layer 2150. FIG. 34 illustrates absence of the sidewall protection layer 215S along a cross-section along a lengthwise direction of the fin-shaped structure 212.

Method 100 includes block 108 to form the protection layer 215 on top surfaces of the isolation feature 214. The protection layer 215 formed in method 100 protects the top surfaces of the isolation feature 214 but does not protect any part of the sidewalls of the isolation feature 214. Method 400 in FIG. 35 includes operations that replace block 108 such that the protection layer 215 works in synergy with a liner 209 to protect the isolation feature 214.

Referring to FIGS. 35 and 36, method 400 includes a block 402 where a liner 209 is deposited over the fin-shaped structure 212. After formation of the fin-shaped structures 212 and before formation of the isolation feature, the liner 209 is deposited over the WIP structure 200, including along top surfaces and sidewalls of the fin-shaped structure 212, sidewalls of the base fin structures 212B, and a top surface of the substrate 202. In some embodiments, the liner 209 may include silicon nitride and may be deposited over the WIP structure 200 using CVD or ALD.

Referring to FIGS. 35 and 37, method 400 includes a block 404 where an isolation feature 214 is formed over the liner 209 to surround the base portion of the fin-shaped structure 212. With the exception that the isolation feature 214 is formed after the formation of the liner 209, operations at block 404 are substantially similar to those described above with respect to block 106. Detailed description of the isolation feature 214 is omitted here for brevity. As shown in FIG. 36, the isolation feature 214 is spaced apart from the substrate 202 and the base fin structures 212B by the liner 209.

Referring to FIGS. 35 and 38, method 400 includes a block 406 where the liner 209 not covered by the isolation feature 214 is trimmed. The trimming of the liner 209 may be achieved using a selective dry etch process or a selective wet etch process. An example selective dry etch process may include carbon tetrafluoride (CF₄), nitrogen trifluoride (NF₃), oxygen (O₂), nitrogen (N₂), or a combination thereof. An example selective wet etch process may include use of warm phosphoric acid (H₃PO₄). As shown in FIG. 37, the trimming at block 404 removes the liner 209 from the top surfaces and sidewalls of the fin-shaped structures 212.

Referring to FIGS. 35 and 39, method 400 includes a block 408 where the protection layer 215 is deposited over the fin-shaped structure 212 and the isolation feature 214. After the trimming of the liner 209, the protection layer 215 may be deposited on top facing surfaces of the fin-shaped structures 212, the liner 209, and the isolation feature 214. As shown in FIG. 38, the protection layer 215 may overlap with or contact the liner 209 to substantially wrap around the isolation feature 214. The formation and the composition of the protection layer 215 is similar to the protection layer 215 described above in block 108. Detailed description of the protection layer 215 is omitted here for brevity.

FIGS. 40-43 illustrates fragmentary cross-sectional views of the WIP structure 200 undergoing operations at blocks 124 and 126 when the liner 209 is present. Referring to FIG. 40, after the dummy gate stack 220 and the dummy layer 230 over the channel regions 212C are removed, the channel members 2080 are released again. The liner 209 extends along sidewalls of the base fin structure 212B and merge with the protection layer 215 on the top surface of the isolation feature 214. The liner 209 and the protection layer 215 work in synergy to protect the isolation feature 214 from undesirable damages. The protection layer 215 over the top surface of the topmost channel member 2080 is removed before the formation of the gate structure 250. FIG. 41 illustrates that the liner 209 extends along sidewalls of the base fin structures 212B in the source/drain regions 212SD. In FIG. 41, a portion of the protection layer 215 is sandwiched between the isolation feature 214 and the gate spacer layer 226. FIG. 42 illustrates that the liner 209 extends along sidewalls of the base fin structures 212B in the channel regions 212C. Besides the liner 209, incomplete removal of the protection layer 215 over the isolation feature 214 results in the bottom protection layer 2150. FIG. 43 illustrates absence of the liner 209 along a cross-section along a lengthwise direction of the fin-shaped structure 212.

Method 100 includes block 108 to form the protection layer 215 directly on top surfaces of the isolation feature 214. Method 500 in FIG. 44 includes operations that replace block 108 such that the protection layer 215 is spaced apart from the isolation feature 214 by an interface layer 217. Method 500 is useful if unwanted charges and traps at an interface of the protection layer 215 and the channel layers 208 are a concern. The interface layer 217 spaces the protection layer 215 away from the fin-shaped structure 212.

Referring to FIGS. 44, 45 and 46, method 500 includes a block 502 where an interface layer 217 is deposited over the fin-shaped structure 212 and the isolation feature 214. A composition of the interface layer 217 is different from that of the protection layer 215. In some embodiments, the interface layer 217 may include silicon oxide and may be conformally deposited over the fin-shaped structures 212 and the isolation feature 214 using ALD or CVD.

Referring to FIGS. 44 and 47, method 500 includes a block 504 where a protection layer 215 is deposited over the interface layer 217. In some embodiments, the protection layer 215 includes silicon nitride, silicon oxycarbonitride, aluminum oxide, or a combination thereof. In one embodiment, the protection layer 215 includes silicon nitride. Different from the protection layer 215 deposited at block 108 of method 100, the protection layer 215 is deposited over the top surface of the isolation feature 214, sidewalls of the fin-shaped structures 212, and top surfaces of the fin-shaped structures 212 using CVD or PVD without the subsequent etch back process. Because the top-facing surfaces are more in the line of sight, the protection layer 215 over the top-facing surfaces is thicker than the protection layer 215 disposed along sidewalls of the fin-shaped structures 212.

Referring to FIGS. 44 and 48, method 500 includes a block 506 where a bottom antireflective coating (BARC) layer 219 is deposited over the protection layer 215. In some implementations, the BARC layer 219 may include silicon oxynitride (SiON), silicon oxycarbide, a polymer, or other suitable materials. In some implementations, the BARC layer 219 may be deposited over the protection layer 215 using CVD, spin-on processes, or other suitable processes.

Referring to FIGS. 44 and 48, method 500 includes a block 508 wherein the BARC layer 219 is etched back. After the deposition of the BARC layer 219, it is etched back to expose a portion of the protection layer 215. The etching back at block 506 may include use of a dry etch process. The dry etch process may include use of plasma of argon (Ar), oxygen (O₂), nitrogen (N₂), hydrogen (H₂), or a combination thereof.

Referring to FIGS. 44 and 49, method 500 includes a block 510 wherein the protection layer 215 not covered by the BARC layer 219 is trimmed. In some embodiments represented in FIG. 48, the trimming of the protection layer 215 also etches the interface layer 217. In some embodiments, the trimming may include use of an oxygen-containing gas, a fluorine-containing gas (e.g., CF₄, SF₆, CH₂F₂, CHF₃, and/or C₂F₆), a chlorine-containing gas (e.g., Cl₂, CHCl₃, CCl₄, and/or BCl₃), a bromine-containing gas (e.g., HBr and/or CHBr₃), an iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof. As illustrated in FIG. 48, the trimming exposes at least a portion of the topmost channel layers 208.

Referring to FIGS. 44 and 50, method 500 includes a block 512 wherein the BARC layer 219 is removed. At block 512, the rest of the BARC layer 219 may be removed using an ashing process or a dry etch process that includes use of plasma of argon (Ar), oxygen (O₂), nitrogen (N₂), hydrogen (H₂), or a combination thereof.

Referring to FIGS. 44 and 51, method 500 includes a block 514 wherein the protection layer 215 over sidewalls of the fin-shaped structure 212 is removed. In some embodiments, an isotropic process, such as a wet etch process, is used at block 514. An example wet etch process may include use of a warm phosphoric acid (H₃PO₄