Operation of the adaptive SMPS circuit with a duty cycle greater than 50% is similar in the first and third phases, with the same transistor configurations. However, in the second phase (called a “holding phase”) following the first phase, transistor Q4 is deactivated, and transistor Q3 is activated, such that the VSW node is coupled to the MID node, the flying capacitive element Cfly is disconnected, and the inductive element L1 is energized. Similarly in the fourth phase (also referred to as a “holding phase”) with a duty cycle greater than 50%, transistor Q2 is activated, and transistor Q5 is deactivated, such that the flying capacitive element Cfly is disconnected and the inductive element L1 is energized.

Furthermore, the control logic 201 may have a control signal (not shown in FIG. 2) configured to control operation of switch S1 and selectively enable divide-by-two (Div2) charge pump operation. For certain aspects, when this control signal is logic low, switch S1 is open, and the power supply circuit 200 operates as a three-level buck converter using the inductive element L1. When this control signal is logic high for certain aspects, switch S1 is closed, thereby shorting across the inductive element L1 and effectively removing the inductive element L1 from the circuit, such that the adaptive SMPS circuit operates as a Div2 charge pump. The control logic 201 may be configured to automatically control operation of switch S1 (e.g., through the logic level of the control signal) based on an output current (also referred to as a “load current”) and/or an input current for the adaptive SMPS circuit.

Example Power Supply Circuit

FIG. 3A is a circuit diagram of an example power supply circuit 300A, in accordance with certain aspects of the present disclosure. The power supply circuit 300A may include a switching regulator (e.g., the SMPS circuit 214), a first power supply node (labeled “VPH1”), a load 306 (e.g., labeled “VPH Load”), a first switch (e.g., implemented by one or more transistors QBAT1), and a first battery 302.

For certain aspects, the battery 302 may be external to an integrated circuit (IC) (e.g., a PMIC), whereas at least a portion of the SMPS circuit 214 and the first switch (implemented by transistor(s) QBAT1) may be internal to the IC. The battery 302 may represent a single-cell (1S) battery, a two-cell-in-series (2S) battery, or more than two stacked cells in a battery (e.g., a multi-cell-in series battery). The load 306 may be analogous to the load 210 of FIG. 2. The load 306 may represent one or more circuits of a device (e.g., the device 100 of FIG. 1) that are powered internally by the SMPS circuit 214 (e.g., with power supply node VPH1=VOUT) (e.g., when an external power source is provided to the power multiplexer 212) or by the battery 302 (e.g., when no external power source is available). The load 306 may be coupled (in shunt) to the reference potential node 218.

In certain aspects, the output voltage node 216 of the SMPS circuit 214 may be coupled to transistor(s) QBAT1 and the load 306. In certain aspects, transistor(s) QBAT1 may be a bidirectional switch implemented with one or more transistors. In some cases, transistor(s) QBAT1 may be implemented by back-to-back transistors or a body-switchable transistor, for example. The gate(s) of transistor(s) QBAT1 may be driven by logic circuitry (e.g., the control logic 201 of FIG. 2 or other logic not shown in FIG. 3A). Transistor(s) QBAT1 may be coupled to the battery 302 via a first battery node 330 (labeled “VBAT1”).

When the battery 302 is external to an IC with other circuitry of the power supply circuit 300A, the IC may include a positive first battery port (e.g., a pin) coupled to the battery node 330 and to the positive terminal of the battery 302. In some cases, the IC may include a negative first battery port coupled to another battery node 332 and to the negative terminal of the battery 302. The other battery node 332 may be coupled to the reference potential node 218.

According to certain aspects, the power supply circuit 300A may perform charging (via the SMPS circuit 214) of the battery 302. Electrical power received from a wall adapter or wireless charger, for example, at the power multiplexer 212 (illustrated in FIG. 2) may be converted by the SMPS circuit 214 and used to independently charge the battery 302. For example, current from the output voltage node 216 may be routed to the battery node 330 via transistor(s) QBAT1 for charging the battery 302.

In power supply circuits, the term “soft start” generally refers to an initial bring-up of a voltage in a slow and controlled manner, for example, to avoid an initial in-rush current to the bypass capacitors when turning on a device, switching power sources, etc. As used herein, a soft start may refer to a phase during which one or more associated transistors (e.g., transistor(s) QBAT1 for the battery 302) are biased in a linear region of operation before the transistors are fully turned on (e.g., biased in saturation). Soft start may be performed to charge a capacitive element (e.g., the bypass capacitor(s) on a power supply rail) to a voltage that is within a certain threshold of the battery voltage before the associated transistor for the battery is fully turned on, as described in more detail herein.

Many power supply circuits used in portable devices may utilize short circuit protection. For example, a power supply circuit (e.g., power supply circuit 300A) may provide short circuit protection during the initial power up of a power supply rail (e.g., the power supply node VPH1) by a SMPS circuit (e.g., SMPS circuit 214), which may involve turning off or disabling the SMPS circuit when a voltage at the power supply rail is less than a certain threshold (e.g., 2 V). In another example, short circuit protection may be provided during the initial power up of the power supply rail by a battery (e.g., battery 302) and may involve entering an automatic fault protection (AFP) mode when a voltage of the power supply rail does not reach a voltage at the battery. However, power supply circuits often lack any short circuit protection after the completion of a soft start of the voltage of the power supply rail. Any occurrence of a short circuit after the completion of a soft start may result in damage to the power supply circuit.

Accordingly, certain aspects of the present disclosure provide techniques and apparatus for selectively triggering an AFP mode after completion of a soft start of a voltage on a power supply node included in a power supply circuit. For example, after completion of a soft start of a voltage of a power supply node, an AFP mode may be triggered when the voltage of the power supply node is less than a threshold voltage (Vth) of a transistor. Certain aspects described herein for providing short circuit protection may consume minimal current and may function even when the power supply circuit is in a shutdown (e.g., low power) mode.

Example Power Supply Circuit with Short Circuit Protection

FIG. 3B is a circuit diagram of an example power supply circuit 300B that includes short circuit protection, in accordance with certain aspects of the present disclosure. The power supply circuit 300B may be similar to the power supply circuit 300A of FIG. 3A, but also includes a logic circuit 350. For example, and as shown in FIG. 3B, the logic circuit 350 may include a transistor Q6, a first current source 360 (labeled “I1”), a debounce circuit 370, and automatic fault protection (AFP) logic 380.

The output voltage node 216 may be coupled to a gate of transistor Q6. Transistor Q6 may include a source coupled to the reference potential node 218 and a drain coupled to a first terminal of the current source 360 and the debounce circuit 370. The debounce circuit 370 may also be coupled to the AFP logic 380 and may be configured to debounce signals (e.g., ringing or bouncing signals due to a sudden voltage level transition) from transistor Q6. The debounce may last, for example, about 10 microseconds (μs). Transistor Q6 may be implemented as an n-type field-effect transistor. In certain aspects, the current source 360 may be replaced by a resistive element (e.g., a relatively high resistance resistor, not shown). In some cases, the current source 360 may generate 0.5 microamperes (μA) of current.

The logic circuit 350 may be configured to detect a short circuit on the power supply node VPH1 (e.g., using a signal labeled “vph1_lt_vt” at the drain of transistor Q6), after completion of a soft start of a voltage on the power supply node VPH1. With the topology of the logic circuit 350 illustrated in FIG. 3B, a short circuit is detected when the voltage of the power supply node VPH1 is less than a threshold voltage (Vth) of transistor Q6. In response to the detection of the short circuit on the power supply node, the logic circuit 350 may be configured to trigger an AFP mode. In some case, in response to the AFP mode being triggered, the logic circuit 350 may be configured to cause transistor(s) QBAT1 to open. In this manner, the AFP mode may prevent damage to transistor(s) QBAT1. The logic circuit 350 may be configured to ignore the voltage of the power supply node VPH1 being less than the threshold voltage of transistor Q6 (e.g., to ignore the vph1_lt_vt signal) before and during the soft start of the voltage of the power supply node VPH1.

The power supply circuit 300B may also be configured to provide short circuit protection as described herein when the battery 302 is dead or when electrical power is received from a wall adapter or wireless charger, for example, and provided through SMPS circuit 214, as well as when a short circuit occurs on the battery node 330 and transistor(s) QBAT1 are turned on.

Example Power Supply Circuit with Multiple Batteries

Although FIGS. 3A and 3B illustrate power supply circuits supporting a single battery, other power supply circuits may support multiple independent batteries (e.g., any number m of cells in series per battery and any number n of batteries in parallel (mSnP), such as one cell per battery and any multiple number n of batteries in parallel (1SnP), regardless whether the batteries have different capacities and/or cells in series).

FIG. 4A is a circuit diagram of an example power supply circuit 400A capable of supporting two (or more) batteries, in accordance with certain aspects of the present disclosure. The power supply circuit 400A may be similar to the power supply circuit 300A of FIG. 3A, but also includes a second power supply node (labeled “VPH2”), a second switch (e.g., implemented by one or more transistors QBAT2), a second battery 304, and a charge pump (CP) 410.

For certain aspects, the second battery 304 may be external to an integrated circuit (IC) (e.g., a PMIC), whereas at least a portion of the SMPS circuit 214, the CP 410, and the second switch (implemented by transistor(s) QBAT2) may be internal to the IC.

In certain aspects, each of the first battery 302 and/or the second battery 304 may represent a single-cell (1S) battery, a two-cell-in-series (2S) battery, or more than two stacked cells in a battery (e.g., a multi-cell-in series battery). The example architecture illustrated in FIG. 4A represents a 2P configuration, with two batteries in parallel, where the first battery 302 is a lower-cell battery (e.g., a 1S battery) and the second battery 304 is a higher-cell battery (e.g., a 2S, 3S, or 4S battery). In other words, the first battery 302 and the second battery 304 may be asymmetrical batteries, each with a different capacity (and size). For example, the power supply circuit 400A may be included in a device that is foldable, which may include a first portion coupled to a second portion by a hinge. In this example, the first portion of the foldable device may include the first battery 302, and the second portion of the foldable device may include the second battery 304.

In certain aspects, the output voltage node 216 of the SMPS circuit 214 may be coupled to transistor(s) QBAT2, in addition to transistor(s) QBAT1 and the load 306. In certain aspects, transistor(s) QBAT2 may be a bidirectional switch, implemented with one or more transistors. In some cases, transistor QBAT2 may be implemented by back-to-back transistors or a body-switchable transistor, for example. The gate(s) of transistor(s) QBAT2 may be driven by logic circuitry (e.g., the control logic 201 of FIG. 2 or other logic not shown in FIG. 4A). In certain aspects, transistor(s) QBAT2 may be coupled to the second battery 304 via a second battery node 340 (labeled “VBAT2”).

When the second battery 304 is external to an IC with other circuitry of the power supply circuit 400A, the IC may include a positive second battery port (e.g., a pin) coupled to the battery node 340 and to the positive terminal of the second battery 304. In some cases, the IC may include a negative second battery port coupled to another second battery voltage node 342 and to the negative terminal of the second battery 304. The second battery voltage node 342 may be coupled to the reference potential node 218, as shown.

The CP 410 may have a first terminal coupled to the power supply node VPH1 and a second terminal coupled to the power supply node VPH2. The CP 410 may be implemented as an ×2 charge pump, a multiply-by-four (×4) charge pump, a Div2 charge pump, a Div4 charge pump, or a charge pump with any other suitable voltage conversion. In a first direction, the CP 410 may be configured to generate the voltage at the power supply node VPH2 from the voltage at the power supply node VPH1 (e.g., to charge the second battery 304 and/or provide power to the power supply node VPH2). In a second direction, the CP 410 may be configured to generate the voltage at the power supply node VPH1 from the voltage at the power supply node VPH2 and supply the load 306. For example, the CP 410 may multiply voltage in the first direction (e.g., operate as an ×2, ×4, or other charge pump when being powered from a wall adapter or wireless charger through the SMPS circuit 214), and may divide voltage in the second direction (e.g., operate as a Div2, Div4, or other charge pump when being powered by the second battery 304), or vice versa for power supply circuits with other battery configurations. In some aspects, the power supply node VPH2 has a higher voltage than the power supply node VPH1. For example, the CP 410 may double the voltage at the power supply node VPH1 to generate the voltage at the power supply node VPH2, to enable the power supply circuit 400A to supply both a power supply rail in a relatively low voltage domain (e.g., associated with the power supply node VPH1) and a power supply rail in a relatively high voltage domain (e.g., associated with the power supply node VPH2).

Example Power Supply Circuit with Multiple Batteries and Short Circuit Protection

The aspects described herein for providing short circuit protection may be used in power supply circuits with multiple power supply nodes, as described below.

FIG. 4B is a circuit diagram of an example power supply circuit 400B capable of supporting two (or more) batteries that includes short circuit protection, in accordance with certain aspects of the present disclosure.

The power supply circuit 400B may be similar to the power supply circuit 400A of FIG. 3A, but also includes a logic circuit 450. The logic circuit 450 may be similar to the logic circuit 350, but also includes a transistor Q7 and a second current source 460 (labeled “I2”). In some cases, the current source 460 may generate, for example, about 0.5 microamperes (μA) of current. In certain aspects, the current source 460 may generate the same amount of current as the current source 360.

The power supply node VPH2 may be coupled to a gate of transistor Q7. Transistor Q7 may include a source coupled to the reference potential node 218 and a drain coupled to a first terminal of the current source 460 and the debounce circuit 370. As described above, the debounce circuit 370 may also be coupled to the AFP logic 380, and may be configured to debounce signals from transistor Q6 and/or transistor Q7. The debounce may last, for example, about 10 μs. Transistor Q7 may be implemented as an n-type field-effect transistor. In certain aspects, the current source 460 may be replaced by a resistive element (e.g., a relatively high resistance resistor, not shown).

The logic circuit 450 may be configured to detect a short circuit on the power supply node VPH1 or the power supply node VPH2 (e.g., using the vph1_lt_vt signal and the signal labeled “vph2_lt_vt” from the drain of transistor Q7), after completion of a soft start of both a voltage on the power supply node VPH1 and a voltage on the power supply node VPH2. A short circuit is detected when the voltage of the power supply node VPH1 is less than a Vth of transistor Q6 or when the voltage at the power supply node VPH2 is less than a Vth of transistor Q7.

After completion of a soft start of a voltage at the power supply node VPH1 and a voltage of the power supply node VPH2, an AFP mode is configured to be triggered (e.g., by the AFP logic 380) when the voltage at the power supply node VPH1 is less than a Vth of transistor Q6 or when the voltage at the power supply node VPH2 is less than a Vth of transistor Q7. In response to the AFP mode being triggered, the logic circuit 450 may be configured to cause at least one of transistor(s) QBAT1 or transistor(s) QBAT2 to open. In this manner, the AFP mode may prevent damage to transistor(s) QBAT1 and/or transistor(s) QBAT2. The logic circuit 450 may be configured to ignore the voltage of the power supply node VPH1 being less than the Vth of transistor Q6 and the voltage of the power supply node VPH2 being less than the Vth of transistor Q7 before and during the soft start of the voltage of the power supply node VPH1 and the soft start of the voltage of the power supply node VPH2.

The power supply circuit 400B may also be configured to provide short circuit protection as described herein when the batteries 302, 304 are dead or when electrical power is received from a wall adapter or wireless charger, for example, and provided through the SMPS circuit 214 (and the CP 410), as well as when a short circuit occurs on the battery node 330 or the battery node 340 and the first switch (implemented by transistor(s) QBAT1) or the second switch (implemented by transistor(s) QBAT2), respectively, is turned on.

Example Operations for Supplying Power with Short Circuit Protection

FIG. 5 is a flow diagram of example operations 500 for supplying power, in accordance with certain aspects of the present disclosure. The operations 500 may be performed by a power supply circuit (e.g., the power supply circuit 300B, 400B of FIGS. 3B and 4B, respectively).

The operations 500 may include, at block 502, enabling a detection mode. The detection mode may be enabled after completion of a soft start of a voltage of a first power supply node (e.g., power supply node VPH1 or power supply node VPH2) coupled to an output (e.g., output voltage node 216) of a switching regulator (e.g., the SMPS circuit 214) and coupled to a battery node (e.g., battery node 330 or battery node 340) via a switch (e.g., transistor QBAT1 or transistor QBAT2). In certain aspects, enabling the detection mode may include enabling the detection mode after the completion of the soft start of the voltage of the first power supply node and after completion of a soft start of a voltage of a second power supply node (e.g., power supply node VPH2 or power supply node VPH1). In these aspects, a charge pump (e.g., CP 410) may be coupled between the second power supply node and the first power supply node, and the switch may be coupled between the second power supply node and the battery node.

At block 504, the operations 500 may involve triggering an AFP mode. The AFP mode may be triggered when, during the enabled detection mode, the voltage of the first power supply node is less than a Vth of a first transistor (e.g., transistor Q6 or transistor Q7) including a gate coupled to the first power supply node. In certain aspects, triggering the AFP mode may include triggering the AFP mode when, during the detection mode, the voltage at the first power supply node is less than the Vth of the first transistor or when the voltage at the second power supply node is less than a Vth of a second transistor (e.g., transistor Q7 or transistor Q6) including a gate coupled to the second power supply node.

According to certain aspects, the operations 500 may further include performing debouncing of a transition of the first transistor before the triggering of the AFP mode. The debouncing may be performed by a debounce circuit (e.g., debounce circuit