100ik, and a positive voltage VW is applied to the source bit line SL[k] coupled to the SOT-MRAM cell 100ik, whereby a current is induced flowing from the source bit line SL[k] to the write bit line WBL[k]. To write the binary value “1” into the SOT-MRAM cell 100im, a positive voltage VW is applied to the write bit line WBL[m] coupled to the SOT-MRAM cell 100im, and a ground voltage VGND is applied to the source bit line SL[m] coupled to the SOT-MRAM cell 100im, whereby a current is induced flowing from the write bit line WBL[m] to the source bit line SL[m].

In FIG. 1A, the required voltages applied various write bit lines and various source bit line SL are provided by a writing circuit 85. The current generated from the writing circuit 85 includes the current flowing from the source bit line SL[k] to the write bit line WBL[k], and the current flowing from the write bit line WBL[m] to the source bit line SL[m].

The read operation on the matrix of SOT-MRAM cells in FIG. 1A is performed row by row by selecting one row of SOT-MRAM cells for reading at a time. Assuming the integer N is the number of rows in the matrix, for a positive integer n≤N, the n'th row of SOT-MRAM cells is selected for reading by setting the SOT-MRAM cells in the n'th row to the reading mode, whereby the n'th row becomes the selected row subjected to the read operation. In some embodiments, in addition to setting the SOT-MRAM cells in the n'th row to the reading mode, the SOT-MRAM cells in all the remaining N−1 rows are set to the detached mode. In some alternative embodiments, in addition to setting the SOT-MRAM cells in the n'th row to the reading mode, the SOT-MRAM cells in another row is set to the writing mode, the SOT-MRAM cells in all the remaining N−2 rows are set to the detached mode. In the example as shown in FIG. 1A, as the SOT-MRAM cells in the j'th row (i.e., n=j) is set to the reading mode and the SOT-MRAM cells in the i'th row is set to the writing mode, the SOT-MRAM cells in all the remaining N−2 rows are set to the detached mode.

During the read operation performed on a selected row of SOT-MRAM cells, the read operation on each individual SOT-MRAM cell in the selected row is carried out by detecting the voltage changes on the read bit line RBL that are coupled to the individual SOT-MRAM cell, and detecting the voltage changes is carried out with a sense amplifier SA coupled to the read bit line RBL. In one example as shown in as shown in FIG. 1A, the selected row for the read operation is the j'th row, and examples of the SOT-MRAM cells in the selected row for the read operation include the SOT-MRAM cell 100jk in the k'th column and the SOT-MRAM cell 100jm in the m'th column. The read operation on the SOT-MRAM cell 100jk is carried out by detecting the voltage changes on the read bit line RBL[k] with a sense amplifier SA[k], as shown schematically in FIG. 2A. The read operation on the SOT-MRAM cell 100jm is carried out by detecting the voltage changes on the read bit line RBL[m] with a sense amplifier SA[m], as shown schematically in FIG. 2B.

FIGS. 2A-2B are circuit diagrams of sense amplifiers coupled to SOT-MRAM cells and reference cells, in accordance with some embodiments. Each of the sense amplifier (e.g., SA[k] in FIG. 2A, or SA[m] in FIG. 2B) includes PMOS transistors TP1 and TP2, NMOS transistors TN1 and TN2, and a differential amplifier LSA. The gates of the PMOS transistors TP1 and TP2 are connected together and configured to receive a pre-charge enabling signal PRE. The gates of the NMOS transistors TN1 and TN2 are connected together and configured to receive a pre-charge enabling signal PRE0. The channels of the PMOS transistor TP1 and the NMOS transistor TN1 are connected together at a connection node INP which is further connected to a first input of differential amplifier LSA. The channel of the PMOS transistor TP2 is connected to the channel of the NMOS transistor TN2 at a connection node INN which is further connected to a second input of differential amplifier LSA.

The connection node INP is coupled to a read bit line (e.g., RBL[k] in FIG. 2A, or RBL[m] in FIG. 2B) through the channel of a coupling transistor TC1. The connection node INN is coupled to a reference bit line RBL[Ref] through the channel of a coupling transistor TC2. The channel of coupling transistor TR1, the reference cell Ref_Cell, and the channel of coupling transistor TR2 are serially connected between the channel of coupling transistors TC2 and a constant voltage node (which is held at the voltage VW in FIG. 2A and at the voltage VGND in FIG. 2B). In some embodiments, the reference cell Ref_Cell is a SOT-MRAM cell implemented with the same cell structure as the SOT-MRAM cell 100 in FIG. 1A.

In FIG. 2A, during the read operation on the SOT-MRAM cell 100jk, each of the coupling transistor TC1 and the read switching transistor S2 is in the conducting state, and the bit line capacitance (not shown in the figure) associated with the read bit line RBL[k] is charged with the current that passes through the MTJ structure in the SOT-MRAM cell 100jk, which causes a voltage change at the connection node INP coupled to the first input of differential amplifier LSA. In addition, during the read operation, each of the coupling transistors TC2, TR1, and TR2 is also in the conducting state, and the bit line capacitance (not shown in the figure) associated with reference bit line RBL[Ref] is charged with the current that passes through the MTJ structure in the reference cell Ref_Cell., which causes a voltage change at the connection node INN coupled to the second input of differential amplifier LSA.

The voltage changes at the first input of differential amplifier LSA is related to the value of the electrical resistance of the MTJ structure in the SOT-MRAM cell 100jk: the smaller the value of the electrical resistance, the faster the voltage change at the first input of differential amplifier LSA. The voltage change at the first input of differential amplifier LSA is compared with the voltage change at the second input of differential amplifier LSA, where the voltage change at the second input is related to the value of the electrical resistance of the MTJ structure in the reference cell Ref_Cell. That is, the output voltage at the output SO of differential amplifier LSA is related to a difference between the electrical resistance of the MTJ structure in the SOT-MRAM cell 100jk and the electrical resistance of the MTJ structure in the reference cell Ref_Cell. Based on the output voltage at the output SO of differential amplifier LSA, the binary value stored in the SOT-MRAM cell 100jk is read out.

In FIG. 2B, the read operation on the SOT-MRAM cell 100jm includes two steps. In a first step, the bit line capacitance (not shown in the figure) associated with the read bit line RBL[m] is pre-charged to a pre-determined value. In a second step, the discharge of the voltage on the bit line capacitance (not shown in the figure) associated with the read bit line RBL[m] is detected with the sense amplifier SA[m].

In one example, during the first step of the read operation on the SOT-MRAM cell 100jm, each of the NMOS transistors TN1 and TN2 is driven into the non-conducting state with a pre-charge enabling signal PRE0, and then, each of the PMOS transistors TP1 and TP2 is driven into the conducting state with a pre-charge enabling signal PRE, and the bit line capacitance associated with the read bit line RBL[m] is pre-charged to a voltage that is equal to the first supply voltage VDD.

During the second step of the read operation on the SOT-MRAM cell 100jm, as shown in FIG. 2B, each of the coupling transistor TC1 and the read switching transistor S2 is in the conducting state, and the bit line capacitance (not shown in the figure) associated with the read bit line RBL[m] is discharged with the current that passes through the MTJ structure in the SOT-MRAM cell 100jm, which causes a voltage change at the connection node INP coupled to the first input of differential amplifier LSA. In addition, during the second step of the read operation, each of the coupling transistors TC2, TR1, and TR2 is also in the conducting state, and the bit line capacitance (not shown in the figure) associated with reference bit line RBL[Ref] is charged with the current that passes through the MTJ structure in the reference cell Ref_Cell., which causes a voltage change at the connection node INN coupled to the second input of differential amplifier LSA.

During the second step of the read operation on the SOT-MRAM cell 100jm, the voltage changes at the first input of differential amplifier LSA is related to the value of the electrical resistance of the MTJ structure in the SOT-MRAM cell 100jm: the smaller the value of the electrical resistance, the faster the voltage change at the first input of differential amplifier LSA. The voltage change at the first input of differential amplifier LSA is compared with the voltage change at the second input of differential amplifier LSA, where the voltage change at the second input is related to the value of the electrical resistance of the MTJ structure in the reference cell Ref_Cell. That is, the output voltage at the output SO of differential amplifier LSA is related to a difference between the electrical resistance of the MTJ structure in the SOT-MRAM cell 100jm and the electrical resistance of the MTJ structure in the reference cell Ref_Cell. Based on the output voltage at the output SO of differential amplifier LSA, the binary value stored in the SOT-MRAM cell 100jm is read out.

FIG. 3 is a timing diagram of various signals in the integrated circuit with SOT-MRAM cells, in accordance with some embodiments. The signals depicted in FIG. 3 includes the master clock signal CLK configured to synchronize various components of the integrated circuit, the coupling control signal VCLP configured to control the conducting states of the coupling transistors TC1 and TC2 (as shown in FIGS. 2A-2B), the pre-charging control signal PRE configured to control the conducting states of PMOS transistors TP1 and TP2 (as shown in FIGS. 2A-2B), and the pre-charging control signal PRE0 configured to control the conducting states of NMOS transistors TN1 and TN2 (as shown in FIGS. 2A-2B). The signals depicted in FIG. 3 include the read-on/read-off voltages on the read word line RWL, and the write-on/write-off voltages on the write word line WWL, the voltages applied to the source bit line SL and the write bit line WBL. The lower supply voltage VSS is implemented as the voltage VGND for driving the source bit line SL or the write bit line WBL in FIGS. 2A-2B. The signals depicted in FIG. 3 include the voltages on the read bit line RBL for two different values of the electrical resistance of the MTJ structure, the voltages at the connection node INP corresponding to two different values of the electrical resistance of the MTJ structure, and the voltages at the connection node INN associated with the read bit line RBL[Ref] in FIGS. 2A-2B. The bottom two signals SAEN and SO in FIG. 3 are correspondingly the sense amplifier enabling signal and the voltage at the output SO of the differential amplifier LSA.

In FIG. 3, between time t1 and t2, the read operation on the SOT-MRAM cell 100jk (as shown in FIG. 2A) is performed, the voltage at the output SO of the differential amplifier LSA is detected to determine the voltage change-rate at the rising edge of the voltage at the connection node INP (which is the voltage change-rate at the read bit line RBL[k]) due to the charging of the voltage on the bit line capacitance by the current that passes through the MTJ structure in the SOT-MRAM cell 100jk. Different voltage change-rate at the read bit line RBL[k] is associated with a different binary value stored in the SOT-MRAM cell 100jk. Consequently, the binary value stored in the SOT-MRAM cell 100jk is read out based on the measurement of the voltage at the output SO of the differential amplifier LSA.

In FIG. 3, between time t2 and t3, the read operation on the SOT-MRAM cell 100jm (as shown in FIG. 2B) is performed, the voltage at the output SO of the differential amplifier LSA is detected to determine the voltage change-rate at the falling edge of the voltage at the connection node INP (which is the voltage change-rate at the read bit line RBL[m]) due to the discharging of the voltage on the bit line capacitance by the current that passes through the MTJ structure in the SOT-MRAM cell 100jm. Different discharging rate of the voltage at the read bit line RBL[m] is associated with a different binary value stored in the SOT-MRAM cell 100jm. Consequently, the binary value stored in the SOT-MRAM cell 100jm is read out based on the measurement of the voltage at the output SO of the differential amplifier LSA.

In FIG. 1A, the SOT-MRAM cell 100jk (as shown in FIG. 2A) and the SOT-MRAM cell 100jm (as shown in FIG. 2B) in the j'th row are two example SOT-MRAM cells in the selected row for the read operation. The SOT-MRAM cell 100jk is associated with a corresponding SOT-MRAM cell 100ik in the same k'th column, and the SOT-MRAM cell 100jm is associated with a corresponding SOT-MRAM cell 100im in the same m'th column. Both the SOT-MRAM cell 100ik and the SOT-MRAM cell 100im are in the i'th row which is the selected row for the write operation.

In FIG. 1A, the SOT-MRAM cell 100jk in the j'th row is associated with a corresponding SOT-MRAM cell 100ik (in the same k'th column and in the i'th row) which is configured to receive the binary value “0” while the i'th row is selected for writing. As the binary value “0” is written into the SOT-MRAM cell