63 is connected to the local data line IO, and a second terminal of the sixty-third transistor M63 is connected to the complementary local data line ION. A control terminal of the sixty-first transistor M61, a control terminal of the sixty-second transistor M62, and a control terminal of the sixty-third transistor M63 receive a second complementary equalization control signal EqIO2N. Under control of the second complementary equalization control signal EqIO2N, voltages on the local data line IO and the complementary local data line ION are driven to a third precharge voltage. The third precharge voltage is a voltage of the tenth power signal.

The second amplification circuit 80 further includes a fifty-seventh transistor M57 and a fifty-eighth transistor M58. A first terminal of the fifty-seventh transistor M57 is connected to a global data line YIO, a second terminal of the fifty-seventh transistor M57 is connected to a first terminal of the fifty-eighth transistor M58, a second terminal of the fifty-eighth transistor M58 is grounded, a control terminal of the fifty-eighth transistor M58 receives a read enable signal RdEn, and a control terminal of the fifty-seventh transistor M57 receives the local data line IO. Under control of the read enable signal RdEn, the voltage on the local data line IO is amplified and then output to the global data line YIO.

The second amplification circuit 80 further includes a fifty-ninth transistor M59, a sixtieth transistor M60, and a sixty-fourth transistor M64. A first terminal of the fifty-ninth transistor M59 is connected to the complementary local data line ION, a second terminal of the fifty-ninth transistor M59 is connected to a complementary global data line YION, a control terminal of the sixtieth transistor M60 is connected to the complementary global data line YION, a first terminal of the sixtieth transistor M60 is connected to the local data line IO, a second terminal of the sixtieth transistor M60 is connected to a first terminal of the sixty-fourth transistor M64, a second terminal of the sixty-fourth transistor M64 is grounded, and a control terminal of the sixty-fourth transistor M64 receives a write enable signal WrEn. A control terminal of the fifty-ninth transistor M59 receives a write enable signal WrEn. Under control of the write enable signal WrEn, a voltage on the complementary global data line YION is amplified and then output to the local data line IO, and the voltage on the complementary global data line YION is transmitted to the complementary local data line ION through the fifty-ninth transistor M59.

FIG. 5 shows a layout of a semiconductor memory. As shown in FIG. 5, the semiconductor memory includes a bank, and the bank includes two half-banks 10 and a second control region 20. A row decoding circuit is disposed in the second control region 20, and the row decoding circuit is configured to decode a row address of the bank to generate a word line signal. The word line signal is configured to control memory cells in the two half-banks to read/write data.

When the first amplification circuit 70 and the second amplification circuit 80 are arranged, a partial structure of the second amplification circuit 80 is usually arranged in a region in which the first amplification circuit is located, and the other partial structure of the second amplification circuit 80 is arranged in another region. FIG. 6 shows an example layout of a semiconductor memory. As shown in FIG. 6, there is a first partial region 30 in each of the half-banks, and the first partial region 30 includes a second storage region (MAT) 304, a second amplification region 301, a third control region 302, and a fourth control region 303. The second amplification region 301 is arranged between two second storage regions 304 arranged in a second direction Y, and a first amplification circuit (MSA) is arranged in the second amplification region 301.

A partial circuit of a second amplification circuit (LSA) is further arranged in the second amplification region 301. A third drive circuit (PCS/NCS) is further disposed in the second amplification region 301, and the third drive circuit is configured to provide a power signal to the first amplification circuit 70 and/or the second amplification circuit 80.

The third control region 302 is arranged between two second amplification regions 301 arranged in a first direction X, and a partial circuit of the second amplification circuit (LSA) is disposed in the third control region 302. A first control circuit (SWC) is further arranged in the third control region 302, and the first control circuit (SWC) is configured to control one or a combination of a circuit in the second amplification region 301 or another circuit in the third control region 302.

The fourth control region 303 is arranged between two second storage regions 304 arranged in the first direction X, a second control circuit (SWD) is arranged in the fourth control region 303, and the second control circuit is configured to drive a word line in the second storage region 304.

Because a circuit structure of the first amplification circuit 70 shown in FIG. 1 is different from a circuit structure of the second amplification circuit 80 shown in FIG. 3 and FIG. 4, a layout of the first amplification circuit 70 is different from a layout of the second amplification circuit 80, and different process procedures are utilized, increasing process difficulty of a device.

FIG. 7 is a schematic circuit diagram of a semiconductor memory according to some embodiments of this application. As shown in FIG. 7, some embodiments of this application provide a semiconductor memory, including a first amplification circuit 70, a second amplification circuit 80, a first control transistor T1, and a second control transistor T2.

At least a partial circuit structure of the first amplification circuit 70 is the same as at least a partial circuit structure of the second amplification circuit 80.

The first amplification circuit 70 is connected to a bit line BL and a complementary bit line BLB, and is configured to amplify a voltage difference between the bit line BL and the complementary bit line BLB. The second amplification circuit 80 is connected to a local data line IO and a complementary local data line ION, and is configured to amplify a voltage difference between the local data line IO and the complementary local data line ION.

The local data line IO is connected to the bit line BL through the first control transistor T1, and the complementary local data line ION is connected to the complementary bit line BLB through the second control transistor T2. A control terminal of the first control transistor T1 and a control terminal of the second control transistor T2 receive a column selection signal CSL.

That at least a partial circuit structure of the first amplification circuit 70 is the same as at least a partial circuit structure of the second amplification circuit 80 specifically means that a first local structure formed by replacing some transistors in the first amplification circuit 70 with wires or removing some transistors from the first amplification circuit 70 has the same circuit structure as the second amplification circuit 80; or a first local structure formed by replacing some transistors in the first amplification circuit 70 with wires or removing some transistors from the first amplification circuit 70 has the same circuit structure as a second local structure formed by replacing some transistors in the second amplification circuit 80 with wires or removing some transistors. It should be noted that when it is determined whether circuit structures are the same, attention is paid only to whether types and positions of transistors included in the circuit structures are the same, and no attention is paid to whether signals received by the transistors are the same.

The column selection signal CSL is configured to control the first control transistor T1 to be turned on or off, and the column selection signal CSL is further configured to control the second control transistor T2 to be turned on or off. When the first control transistor T1 and the second control transistor T2 are turned on, data on the local data line IO and the complementary local data line ION may be transmitted to the bit line BL and the complementary bit line BLB, or data on the bit line BL and the complementary bit line BLB may be transmitted to the local data line IO and the complementary local data line ION.

The data on the bit line BL and the complementary bit line BLB is represented by the voltage difference between the bit line BL and the complementary bit line BLB. When a voltage on the bit line BL is greater than a voltage on the complementary bit line BLB, it indicates that the data on the bit line BL and the complementary bit line BLB is 1; or when a voltage on the bit line BL is less than a voltage on the complementary bit line BLB, it indicates that the data on the bit line BL and the complementary bit line BLB is 0.

Similarly, the data on the local data line IO and the complementary local data line ION is represented by the voltage difference between the local data line IO and the complementary local data line ION. When a voltage on the local data line IO is greater than a voltage on the complementary local data line ION, it indicates that the data on the local data line IO and the complementary local data line ION is 1; or when a voltage on the local data line IO is less than a voltage on the complementary local data line ION, it indicates that the data on the local data line IO and the complementary local data line ION is 0.

In the foregoing technical solution, the semiconductor memory includes the first amplification circuit 70, the second amplification circuit 80, the first control transistor T1, and the second control transistor T2. The bit line BL is connected to the local data line IO through the first control transistor T1, and the complementary bit line BLB is connected to the complementary local data line ION through the second control transistor T2. In this way, the data on the bit line BL and the complementary bit line BLB and the data on the local data line IO and the complementary local data line ION are transmitted. The first amplification circuit 70 is configured to amplify the voltage difference between the bit line BL and the complementary bit line BLB, and the second amplification circuit 80 is configured to amplify the voltage difference between the local data line IO and the complementary local data line ION, so that the first amplification circuit 70 and the second amplification circuit 80 are functionally continuous, and further the first amplification circuit 70 and the second amplification circuit 80 can be physically adjacent to each other. It is set that at least a partial circuit structure of the first amplification circuit 70 is the same as at least a partial circuit structure of the second amplification circuit 80, so that a layout structure of the first amplification circuit 70 is similar to a layout structure of the second amplification circuit 80. Therefore, a unified preparation process can be utilized for device preparation, thereby reducing process difficulty.

In some embodiments, FIG. 8 is a schematic circuit diagram of a semiconductor memory according to some embodiments of this application. As shown in FIG. 8, the semiconductor memory further includes a third control transistor T3 and a fourth control transistor T4. The local data line IO is connected to a global data line YIO through the third control transistor T3, and the complementary local data line ION is connected to a complementary global data line YION through the fourth control transistor T4. Both a control terminal of the third control transistor T3 and a control terminal of the fourth control transistor T4 receive a read/write control signal RW. The read/write control signal RW is generated when the semiconductor memory receives a data read instruction or a data write instruction.

Herein, an example in which the third transistor T3 and the fourth transistor T4 are N-type transistors is utilized for description. When the read/write control signal RW is generated when the semiconductor memory receives the data read instruction, and when the read/write control signal RW is at a high level, the third control transistor T3 and the fourth control transistor T4 are turned on, and the data on the local data line IO and the complementary local data line ION is controlled to be transmitted to the global data line YIO and the complementary global data line YION. When the read/write control signal RW is generated when the semiconductor memory receives the data write instruction, and when the read/write control signal RW is at a high level, the third control transistor T3 and the fourth control transistor T4 are turned on, and data on the global data line YIO and the complementary global data line YION is controlled to be transmitted to the local data line IO and the complementary local data line ION. The third control transistor T3 connecting the local data line IO and the global data line YIO and the fourth control transistor T4 connecting the complementary local data line ION and the complementary global data line YION are disposed, so that the data on the local data line IO and the global data line YIO and the data on the complementary local data line ION and the complementary global data line YION are transmitted. That is, the third control transistor T3 and the fourth control transistor T4 are configured to implement transmission between the data on the local data line IO and the complementary local data line ION and the data on the global data line YIO and the complementary global data line YION, and have functions similar to those of the first control transistor T1 and the second control transistor T2, so that a relative position relationship between the third control transistor T3 and the second amplification circuit 80 is similar to a relative position relationship between the first control transistor T1 and the first amplification circuit 70, and a relative position relationship between the fourth control transistor T4 and the second amplification circuit 80 is similar to a relative position relationship between the second control transistor T2 and the first amplification circuit 70, to help improve symmetry between a layout at a position of the first amplification circuit 70 and a layout at a position of the second amplification circuit 80. Therefore, a unified preparation process can be utilized for device preparation, thereby reducing process difficulty.

In some embodiments, the semiconductor memory further includes multiple third control transistors T3 connected in parallel and multiple fourth control transistors T4 connected in parallel. One terminal of each of the multiple third control transistors T3 is connected to the same local data line IO, and the other terminal of each of the multiple third control transistors T3 is connected to the same global data line YIO. One terminal of each of the multiple fourth control transistors T4 is connected to the same complementary local data line ION, and the other terminal of each of the multiple fourth control transistors T4 is connected to the same complementary global data line YION. The transistors are disposed in parallel, so that a drive capability can be improved, and transmission speeds of the data on the local data line IO and the global data line YIO and the data on the complementary local data line ION and the complementary global data line YION can be increased, to improve read/write performance of the semiconductor memory.

In some embodiments, FIG. 9 is a schematic circuit diagram of a semiconductor memory according to some other embodiments of this application. As shown in FIG. 9, the semiconductor memory further includes a third control transistor T3, a fifth control transistor T5, and a sixth control transistor T6. The local data line IO is connected to a global data line YIO through the third control transistor T3, the complementary local data line ION is grounded through the fifth control transistor T5 and the sixth control transistor T6, and the fifth control transistor T5 and the sixth control transistor T6 are connected in series.

A control terminal of the third control transistor T3 receives a read/write control signal RW, a control terminal of the fifth control transistor T5 is connected to the global data line YIO, and a control terminal of the sixth control transistor T6 receives a write enable signal WrEn. The read/write control signal RW is generated when the semiconductor memory receives a data read instruction or a data write instruction, and the write enable signal WrEn is generated when the semiconductor memory receives the data write instruction.

Herein, an example in which the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are N-type transistors is utilized for description. When the read/write control signal RW and the write enable signal WrEn are generated when the semiconductor memory receives the data write instruction, and when both the read/write control signal RW and the write enable signal WrEn are at a high level, the third control transistor T3 and the sixth control transistor T6 are turned on. If a voltage on the global data line YIO is at a high level, the fifth control transistor T5 is turned on, the complementary local data line ION is grounded, and the local data line IO is driven to a high level, so that data is written on the local data line IO and the complementary local data line ION. If a voltage on the global data line YIO is at a low level, the fifth control transistor T5 is turned off, the complementary local data line ION is maintained at a fourth precharge voltage, and the local data line IO is driven to a low level. It is set that the fourth precharge voltage is greater than the low level and meets a voltage difference requirement, so that data can be written on the local data line IO and the complementary local data line ION.

A sequence of connecting the fifth control transistor T5 and the sixth control transistor T6 in series is not limited herein. In an implementable solution, a first terminal of the fifth control transistor T5 is connected to the complementary local data line ION, a second terminal of the fifth control transistor T5 is connected to a first terminal of the sixth control transistor T6, and a second terminal of the sixth control transistor T6 is grounded. In another implementable solution, a first terminal of the sixth control transistor T6 is connected to the complementary local data line ION, a second terminal of the sixth control transistor T6 is connected to a first terminal of the fifth control transistor T5, and a second terminal of the fifth control transistor T5 is grounded.

That is, the third control transistor T3 and the fifth control transistor T5 respectively implement signal transmission between the local data line IO and the global data line YIO and signal transmission between the complementary local data line ION and the global data line YIO, and have functions similar to those of the first control transistor T1 and the second control transistor T2, so that a relative position relationship between the third control transistor T3 and the second amplification circuit 80 is similar to a relative position relationship between the first control transistor T1 and the first amplification circuit 70, and a relative position relationship between the fifth control transistor T5 and the second amplification circuit 80 is similar to a relative position relationship between the second control transistor T2 and the first amplification circuit 70, to help improve symmetry between a layout at a position of the first amplification circuit and a layout at a position of the second amplification circuit. Therefore, a unified preparation process can be utilized for device preparation, thereby reducing process difficulty.

In some embodiments, the semiconductor memory includes multiple second amplification circuits 80. The multiple second amplification circuits 80 are connected to the same local data line IO and the same complementary local data line ION. In this way, the multiple second amplification circuits 80 can simultaneously amplify a voltage difference between the same pair of local data lines IO and complementary local data lines ION, to increase a voltage difference amplification rate and increase a data read/write rate.

In some embodiments, FIG. 10 is a schematic circuit diagram of a semiconductor memory according to some other embodiments of this application. As shown in FIG. 10, each of the second amplification circuits 80 includes a first transistor M1, a second transistor M2, a seventh transistor M7, and an eighth transistor M8.

A first terminal of the first transistor M1 and a first terminal of the second transistor M2 receive a first power signal PCS_L, and a second terminal of the seventh transistor M7 and a second terminal of the eighth transistor M8 receive a second power signal NCS_L.

A second terminal of the first transistor M1 is connected to a first terminal of the seventh transistor M7, a control terminal of the first transistor M1 is connected to a second terminal of the second transistor M2, the second terminal of the second transistor M2 is connected to a first terminal of the eighth transistor M8, a control terminal of the second transistor M2 is connected to the second terminal of the first transistor M1, a control terminal of the seventh transistor M7 is connected to the first terminal of the eighth transistor M8, and a control terminal of the eighth transistor M8 is connected to the first terminal of the seventh transistor M7.

The first amplification circuit 70 may be of the structure shown in FIG. 1. In this way, a local circuit structure of the first amplification circuit 70 is the same as a circuit structure of each of the second amplification circuits 80. That is, each of the second amplification circuits 80 is of a structure obtained after the thirteenth transistor M13 and the fourteenth transistor M14 are replaced with wires and the fifteenth transistor M15 and the sixteenth transistor M16 are removed based on FIG. 1, so that the local circuit structure of the first amplification circuit 70 is the same as the circuit structure of each of the second amplification circuits 80.

In another embodiment, a structure of the first amplification circuit may alternatively be a structure obtained after only the thirteenth transistor M13 and the fourteenth transistor M14 are replaced with wires based on FIG. 1, or a circuit structure obtained after only the fifteenth transistor M15 and the sixteenth transistor M16 are removed based on FIG. 1. In this way, a partial circuit structure of the first amplification circuit 70 can be the same as a circuit structure of each of the second amplification circuits 80.

In another embodiment, a structure of the first amplification circuit may alternatively be a circuit structure obtained after the thirteenth transistor M13 and the fourteenth transistor M14 are replaced with wires and the fifteenth transistor M15 and the sixteenth transistor M16 are removed based on FIG. 1. In this way, a circuit structure of the first amplification circuit 70 can be exactly the same as a circuit structure of each of the second amplification circuits 80.

In some embodiments, FIG. 11 is a schematic circuit diagram of a semiconductor memory according to still some other embodiments of this application. As shown in FIG. 11, FIG. 8, and FIG. 9, each of the second amplification circuits 80 further includes a fifth transistor M5 and a sixth transistor M6. A first terminal of the fifth transistor M5 is connected to the control terminal of the seventh transistor M7, and a second terminal of the fifth transistor M5 is connected to the first terminal of the seventh transistor M7. A first terminal of the sixth transistor M6 is connected to the first terminal of the eighth transistor M8, and a second terminal of the sixth transistor M6 is connected to the control terminal of the eighth transistor M8.

In some embodiments, a control terminal of the fifth transistor M5 receives a first equalization control signal EqIO1, a control terminal of the sixth transistor M6 receives the first equalization control signal EqIO1, and the first equalization control signal EqIO1 is configured to control the fifth transistor M5 and the sixth transistor M6 to be turned on or off. The first equalization control signal EqIO1 is further configured to control an equalization circuit to precharge the local data line IO and the complementary local data line ION.

The first amplification circuit 70 may be of the structure shown in FIG. 1. In this way, a partial circuit structure of the first amplification circuit 70 is the same as a circuit structure of each of the second amplification circuits 80. That is, each of the second amplification circuits 80 is a result of replacing the thirteenth transistor M13 and the fourteenth transistor M14 with wires based on FIG. 1, so that a local circuit structure of the first amplification circuit 70 is the same as the circuit structure of each of the second amplification circuits 80.

In another embodiment, a structure of the first amplification circuit 70 may alternatively be a structure obtained after the thirteenth transistor M13 and the fourteenth transistor M14 are replaced with wires and the fifteenth transistor M15 and the sixteenth transistor M16 are removed based on FIG. 1. In this way, a partial circuit structure of the first amplification circuit 70 is the same as a circuit structure of each of the second amplification circuits 80.

In another embodiment, a structure of the first amplification circuit 70 may alternatively be a structure obtained after the thirteenth transistor M13 and the fourteenth transistor M14 are replaced with wires based on FIG. 1. In this way, a circuit structure of the first amplification circuit 70 is exactly the same as a circuit structure of each of the second amplification circuits 80.

The fifth transistor M5 and the sixth transistor M6 are controlled by utilizing the first equalization control signal EqIO1, to ensure that the fifth transistor M5 and the sixth transistor M6 are in an on state when the equalization circuit performs precharging. This helps precharge the local data line IO and the complementary local data line ION, and can simplify a structure of the equalization circuit.

In some embodiments, as shown in FIG. 8 and FIG. 9, the equalization circuit is connected to the first terminal of the eighth transistor M8, the equalization circuit further receives a third power signal, and the equalization circuit receives the first equalization control signal EqIO1, to control the first terminal of the eighth transistor M8 to receive the third power signal. A voltage of the third power signal falls within [0.5 V, 0.55 V]. In another embodiment, the voltage of the third power signal falls within [1 V, 1.08 V]. When the first equalization control signal EqIO1 enables the first terminal of the eighth transistor M8 to receive the third power signal, the fifth transistor M5 and the sixth transistor M6 are in an on state. This helps precharge the local data line IO and the complementary local data line ION, and simplifies a structure of the equalization circuit.

In some embodiments, the equalization circuit is connected to the first terminal of the seventh transistor M7, the equalization circuit further receives a third power signal, and the equalization circuit receives the first equalization control signal EqIO1, to control the first terminal of the seventh transistor M7 to receive the third power signal. When the first equalization control signal EqIO1 enables the first terminal of the seventh transistor M7 to receive the third power signal, the fifth transistor M5 and the sixth transistor M6 are in an on state. This helps precharge the local data line IO and the complementary local data line ION, and simplifies a structure of the equalization circuit.

In some embodiments, the equalization circuit includes a ninth transistor M9. A first terminal of the ninth transistor M9 is connected to the first terminal of the eighth transistor M8, a second terminal of the ninth transistor M9 receives a third power signal, and a control terminal of the ninth transistor M