having read/write circuits for reading and programming a page of memory cells (e.g., NAND multi-state flash memory) in parallel. Memory device 210 may include one or more memory die or chips 212. Memory die 212 includes an array (two-dimensional or three dimensional) of memory cells 200, control circuitry 220, and read/write circuits 230A and 230B. In one embodiment, access to the memory array 200 by the various peripheral circuits is implemented in a symmetric fashion, on opposite sides of the array, so that the densities of access lines and circuitry on each side are reduced by half. The read/write circuits 230A and 230B include multiple sense blocks 300 which allow a page of memory cells to be read or programmed in parallel. The memory array 200 is addressable by word lines via row decoders 240A and 240B and by bit lines via column decoders 242A and 242B. In a typical embodiment, a controller 244 is included in the same memory device 210 (e.g., a removable storage card or package) as the one or more memory die 212. Commands and data are transferred between the host and controller 244 via lines 232 and between the controller and the one or more memory die 212 via lines 234. Some memory systems may include multiple dies 212 in communication with Controller 244.

Control circuitry 220 cooperates with the read/write circuits 230A and 230B to perform memory operations on the memory array 200. The control circuitry 220 includes a state machine 222, an on-chip address decoder 224 and a power control module 226. The state machine 222 provides chip-level control of memory operations. The on-chip address decoder 224 provides an address interface between that used by the host or a memory controller to the hardware address used by the decoders 240A, 240B, 242A, and 242B. The power control module 226 controls the power and voltages supplied to the word lines and bit lines during memory operations. In one embodiment, power control module 226 includes one or more charge pumps that can create voltages larger than the supply voltage. Control circuitry 220, power control 226, decoder 224, state machine 222, decoders 240A/B & 242A/B, the read/write circuits 230A/B and the controller 244, collectively or separately, can be referred to as one or more managing circuits.

FIG. 4 is a block diagram of an individual sense block 300 partitioned into a core portion, referred to as a sense module 480, and a common portion 490. In one embodiment, there will be a separate sense module 480 for each bit line and one common portion 490 for a set of multiple sense modules 480. In one example, a sense block will include one common portion 490 and eight sense modules 480. Each of the sense modules in a group will communicate with the associated common portion via a data bus 472. For further details, refer to U.S. Patent Application Publication 2006/0140007, which is incorporated herein by reference in its entirety.

Sense module 480 comprises sense circuitry 470 that determines whether a conduction current in a connected bit line is above or below a predetermined level. In some embodiments, sense module 480 includes a circuit commonly referred to as a sense amplifier. Sense module 480 also includes a bit line latch 482 that is used to set a voltage condition on the connected bit line. For example, a predetermined state latched in bit line latch 482 will result in the connected bit line being pulled to a state designating program inhibit (e.g., Vdd).

Common portion 490 comprises a processor 492, a set of data latches 494 and an I/O Interface 496 coupled between the set of data latches 494 and data bus 420. Processor 492 performs computations. For example, one of its functions is to determine the data stored in the sensed memory cell and store the determined data in the set of data latches. The set of data latches 494 is used to store data bits determined by processor 492 during a read operation. It is also used to store data bits imported from the data bus 420 during a program operation. The imported data bits represent write data meant to be programmed into the memory. I/O interface 496 provides an interface between data latches 494 and the data bus 420.

During read or sensing, the operation of the system is under the control of state machine 222 that controls the supply of different control gate voltages to the addressed cell. As it steps through the various predefined control gate voltages (the read reference voltages or the verify reference voltages) corresponding to the various memory states supported by the memory, the sense module 480 may trip at one of these voltages and an output will be provided from sense module 480 to processor 492 via bus 472. At that point, processor 492 determines the resultant memory state by consideration of the tripping event(s) of the sense module and the information about the applied control gate voltage from the state machine via input lines 493. It then computes a binary encoding for the memory state and stores the resultant data bits into data latches 494. In another embodiment of the core portion, bit line latch 482 serves double duty, both as a latch for latching the output of the sense module 480 and also as a bit line latch as described above.

It is anticipated that some implementations will include multiple processors 492. In one embodiment, each processor 492 will include an output line (not depicted in FIG. 4) such that each of the output lines is wired-OR'd together. In some embodiments, the output lines are inverted prior to being connected to the wired-OR line. This configuration enables a quick determination during the program verification process of when the programming process has completed because the state machine receiving the wired-OR line can determine when all bits being programmed have reached the desired level. For example, when each bit has reached its desired level, a logic zero for that bit will be sent to the wired-OR line (or a data one is inverted). When all bits output a data 0 (or a data one inverted), then the state machine knows to terminate the programming process. In embodiments where each processor communicates with eight sense modules, the state machine may (in some embodiments) need to read the wired-OR line eight times, or logic is added to processor 492 to accumulate the results of the associated bit lines such that the state machine need only read the wired-OR line one time. In some embodiments that have many sense modules, the wired-OR lines of the many sense modules can be grouped in sets of N sense modules, and the groups can then be grouped to form a binary tree.

During program or verify, the data to be programmed is stored in the set of data latches 494 from the data bus 420. The program operation, under the control of the state machine, comprises a series of programming voltage pulses (with increasing magnitudes) concurrently applied to the control gates of the addressed memory cells to that the memory cells are programmed at the same time. Each programming pulse is followed by a verify process to determine if the memory cell has been programmed to the desired state. Processor 492 monitors the verified memory state relative to the desired memory state. When the two are in agreement, processor 492 sets the bit line latch 482 so as to cause the bit line to be pulled to a state designating program inhibit. This inhibits the memory cell coupled to the bit line from further programming even if it is subjected to programming pulses on its control gate. In other embodiments the processor initially loads the bit line latch 482 and the sense circuitry sets it to an inhibit value during the verify process.

Data latch stack 494 contains a stack of data latches corresponding to the sense module. In one embodiment, there are three (or four or another number) data latches per sense module 480. In some implementations (but not required), the data latches are implemented as a shift register so that the parallel data stored therein is converted to serial data for data bus 420, and vice versa. In one preferred embodiment, all the data latches corresponding to the read/write block of memory cells can be linked together to form a block shift register so that a block of data can be input or output by serial transfer. In particular, the bank of read/write modules is adapted so that each of its set of data latches will shift data into or out of the data bus in sequence as if they are part of a shift register for the entire read/write block.

Additional information about the structure and/or operations of various embodiments of non-volatile storage devices can be found in (1) United States Patent Application Pub. No. 2004/0057287, “Non-Volatile Memory And Method With Reduced Source Line Bias Errors,” published on Mar. 25, 2004; (2) United States Patent Application Pub No. 2004/0109357, “Non-Volatile Memory And Method with Improved Sensing,” published on Jun. 10, 2004; (3) U.S. Patent Application Pub. No. 20050169082; (4) U.S. Patent Application Pub. 2006/0221692, titled “Compensating for Coupling During Read Operations of Non-Volatile Memory,” Inventor Jian Chen, filed on Apr. 5, 2005; and (5) U.S. Patent Application Pub. 2006/0158947, titled “Reference Sense Amplifier For Non-Volatile Memory, Inventors Siu Lung Chan and Raul-Adrian Cernea, filed on Dec. 28, 2005. All five of the immediately above-listed patent documents are incorporated herein by reference in their entirety.

FIG. 5 depicts an exemplary structure of memory cell array 200. In one embodiment, the array of memory cells is divided into a large number of blocks of memory cells. As is common for flash EEPROM systems, the block is the unit of erase. That is, each block contains the minimum number of memory cells that are erased together. Other embodiments can use different units of erase.

As one example, the NAND flash EEPROM depicted in FIG. 5 is partitioned into 1,024 blocks. However, more or less than 1024 blocks can be used. In each block, in this example, there are 69,624 columns corresponding to bit lines BL0, BL1, . . . . BL69,623. In one embodiment, all of the bit lines of a block can be simultaneously selected during read and program operations. Memory cells along a common word line and connected to any bit line can be programmed (or read) at the same time (e.g., concurrently). In another embodiment, the bit lines are divided into even bit lines and odd bit lines. In an odd/even bit line architecture, memory cells along a common word line and connected to the odd bit lines are programmed at one time, while memory cells along a common word line and connected to even bit lines are programmed at another time.

FIG. 5 shows four memory cells connected in series to form a NAND string. Although four cells are shown to be included in each NAND string, more or less than four can be used (e.g., 16, 32, 64, 128 or another number or memory cells can be on a NAND string). One terminal of the NAND string is connected to a corresponding bit line via a drain select gate (connected to select gate drain line SGD), and another terminal is connected to the source line via a source select gate (connected to select gate source line SGS).

Each block is typically divided into a number of pages. In one embodiment, a page is a unit of programming. One or more pages of data are typically stored in one row of memory cells. A page can store one or more sectors. A sector includes user data and overhead data. Overhead data typically includes an Error Correction Code (ECC) that has been calculated from the user data of the sector. The controller calculates the ECC when data is being programmed into the array, and also checks it when data is being read from the array. In some embodiments, the state machine, controller, or other component can calculate and check the ECC. In some alternatives, the ECCs and/or other overhead data are stored in different pages, or even different blocks, than the user data to which they pertain. A sector of user data is typically 512 bytes, corresponding to the size of a sector in magnetic disk drives. A large number of pages form a block, anywhere from 8 pages, for example, up to 32, 64, 128 or more pages. In one embodiment, each word line of a block is associated with one page. In another embodiment, each word line of a block is associated with 3 pages. In other embodiments, the word lines can be associate with other numbers of pages.

Some memory cells are slower to program or erase than others because of manufacturing variations among those memory cells, because those cells were previously erased to a lower threshold voltage than others, because of uneven wear among the cells within a page, or other reasons. And, of course, some memory cells cannot be programmed or erased whatsoever, because of a defect or other reason. Additionally, some memory cells program fast and can be over programmed, which may also cause an error. As mentioned above, error correction coding provides the capability of tolerating some number of failed cells, while still maintaining the memory as usable. In some applications, a page of data is programmed by repeatedly applying programming pulses until all memory cells on that page verify to the desired programmed state. In some implementation, programming and erasing time is saved by terminating the sequence of programming or erasing pulses when the number of error memory cells that are not yet fully programmed or erased is fewer than the number of bits that are correctable.

FIG. 6 is a flow chart describing one embodiment of a process for programming. In step 520, a request for programming is received from the Host, the Controller or other entity. In step 522, the Controller (or state machine or other entity) will determine which set of one or more blocks to store the data. In step 524, the data received for the request is programmed into one or more blocks of memory cells. In step 526, the data can be read. The dashed line between steps 524 and 526 indicates that there can be an unpredictable amount of time between programming and reading.

FIG. 7 is a flow chart describing a process for programming a block of memory. The process of FIG. 7 is performed one or more times during step 524 of FIG. 6. In one example implementation, memory cells are pre-programmed in order to maintain even wear on the memory cells (step 550). In one embodiment, the memory cells are preprogrammed to the highest data state, a random pattern, or any other pattern. In some implementations, pre-programming need not be performed. Some embodiments do not implement pre-programming.

In step 552, memory cells are erased (in blocks or other units) prior to programming. Memory cells are erased in one embodiment by raising the p-well to an erase voltage (e.g., 20 volts) for a sufficient period of time and grounding the word lines of a selected block while the source and bit lines are floating. In blocks that are not selected to be erased, word lines are floated. Due to capacitive coupling, the unselected word lines, bit lines, select lines, and the common source line are also raised to a significant fraction of the erase voltage thereby impeding erase on blocks that are not selected to be erased. In blocks that are selected to be erased, a strong electric field is applied to the tunnel oxide layers of selected memory cells and the selected memory cells are erased as electrons of the floating gates are emitted to the substrate side, typically by Fowler-Nordheim tunneling mechanism. As electrons are transferred from the floating gate to the p-well region, the threshold voltage of a selected cell is lowered. Erasing can be performed on the entire memory array, on individual blocks, or another unit of memory cells. In one embodiment, after erasing the memory cells, all of the erased memory cells in the block will be in state S0 (discussed below). One implementation of an erase process includes applying several erase pulses to the p-well and verifying between erase pulses whether the NAND strings are properly erased.

In step 554, soft programming is (optionally) performed to narrow the distribution of erased threshold voltages for the erased memory cells. Some memory cells may be in a deeper erased state than necessary as a result of the erase process. Soft programming can apply programming pulses to move the threshold voltage of the deeper erased memory cells to the erase threshold distribution. In step 556, the memory cells of the block are programmed. The programming can be performed in response to a request to program from the host, or in response to an internal process. After programming, the memory cells of the block can be read. Many different read processes known in the art can be used to read data. In some embodiments, the read process includes using ECC to correct errors. The data that is read is output to the hosts that requested the read operation. The ECC process can be performed by the state machine, the controller or another device. The erase-program cycle can happen many times without or independent of reading, the read process can occur many times without or independent of programming and the read process can happen any time after programming. The process of FIG. 7 can be performed at the direction of the state machine using the various circuits described above. In other embodiments, the process of FIG. 7 can be performed at the direction of the Controller using the various circuits described above.

At the end of a successful programming process (with verification), the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate. FIG. 8 illustrates example threshold voltage distributions for the memory cell array when each memory cell stores three bits of data. Other embodiments, however, may use more or less than three bits of data per memory cell (e.g., such as three bits of data per memory cell).

In the example of FIG. 8, each memory cell stores three bits of data; therefore, there are eight valid threshold voltage distributions, also called data states: S0, S1, S2, S3, S4, S5, S6 and S7. In one embodiment, data state S0 is below 0 volts and data states S1-S7 are above 0 volts. In other embodiments, all eight data states are above 0 volts, or other arrangements can be implemented. In one embodiment, the threshold voltage distribution for S0 is wider than for S1-S7. In one embodiment, S0 is for erased memory cells. Data is programmed from S0 to S1-S7.

Each data state corresponds to a unique value for the three data bits stored in the memory cell. In one embodiment, S0=111, S1=110, S2=101, S3=100, S4=011, S5=010, S6=001 and S7=000. Other mapping of data to states S0-S7 can also be used. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. For example, U.S. Pat. No. 6,222,762 and U.S. Patent Application Publication No. 2004/0255090, “Tracking Cells For A Memory System,” filed on Jun. 13, 2003, both of which are incorporated herein by reference in their entirety, describe various data encoding schemes for multi-state flash memory cells. In one embodiment, data values are assigned to the threshold voltage ranges using a Gray code assignment so that if the threshold voltage of a floating gate erroneously shifts to its neighboring threshold voltage distribution, only one bit will be affected. However, in other embodiments, Gray code is not used.

In one embodiment, all of the bits of data stored in a memory cell are stored in the same logical page. In other embodiments, each bit of data stored in a memory cell corresponds to different logical pages. Thus, a memory cell storing three bits of data would include data in a first page, data in a second page and data in a third page. In some embodiments, all of the memory cells connected to the same word line would store data in the same three pages of data. In some embodiments, the memory cells connected to a word line can be grouped into different sets of pages (e.g., by odd and even bit lines, or by other arrangements).

In some devices, the memory cells will be erased to state S0. From state S0, the memory cells can be programmed to any of states S1-S7. In one embodiment, known as full sequence programming, memory cells can be programmed from the erased state S0 directly to any of the programmed states S1-S7. For example, a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased state S0. While some memory cells are being programmed from state S0 to state S1, other memory cells are being programmed from state S0 to state S2, state S0 to state S3, state S0 to state S4, state S0 to state S5, state S0 to state S6, and state S0 to state S7. Full sequence programming is graphically depicted by the seven curved arrows of FIG. 8.

FIG. 8 shows a set of verify target levels Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7. These verify levels are used as comparison levels (also known as target levels) during the programming process. For example, when programming memory cells to state S1, the system will check to see if the threshold voltages of the memory cells have reached Vv1. If the threshold voltage of a memory cell has not reached Vv1, then programming will continue for that memory cell until its threshold voltage is greater than or equal to Vv1. If the threshold voltage of a memory cell has reached Vv1, then programming will stop for that memory cell. Verify target level Vv2 is used for memory cells being programmed to state S2. Verify target level Vv3 is used for memory cells being programmed to state S3. Verify target level Vv4 is used for memory cells being programmed to state S4. Verify target level Vv5 is used for memory cells being programmed to state S5. Verify target level Vv6 is used for memory cells being programmed to state S6. Verify target level Vv7 is used for memory cells being programmed to state S7.

FIG. 8 also shows a set of read compare levels Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7. These read compare levels are used as comparison levels during the read process. By testing whether the memory cells turn on or remain off in response to the read compare levels Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7 being separately applied to the control gates of the memory cells, the system can determine which states that memory cells are storing data for.

In general, during verify operations and read operations, the selected word line is connected to a voltage, a level of which is specified for each read operation (e.g., see read compare levels Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7 of FIG. 8) or verify operation (e.g. see verify target levels Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7 of FIG. 8) in order to determine whether a threshold voltage of the concerned memory cell has reached such level. After applying the word line voltage, the conduction current of the memory cell is measured to determine whether the memory cell turned on in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, then it is assumed that the memory cell turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than the certain value, then it is assumed that the memory cell did not turn on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During a read or verify process, the unselected memory cells are provided with one or more read pass voltages at their control gates so that these memory cells will operate as pass gates (e.g., conducting current regardless of whether they are programmed or erased).

There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured by the rate it discharges or charges a dedicated capacitor in the sense amplifier that is in communication with the bit line. In another example, the conduction current of the selected memory cell allows (or fails to allow) the NAND string that includes the memory cell to discharge a corresponding bit line. The voltage on the bit line is measured after a period of time to see whether it has been discharged or not. Note that the technology described herein can be used with different methods known in the art for verifying/reading. More information about verifying/reading can be found in the following patent documents that are incorporated herein by reference in their entirety: (1) United States Patent Application Pub. No. 2004/0057287; (2) United States Patent Application Pub No. 2004/0109357; (3) U.S. Patent Application Pub. No. 2005/0169082; and (4) U.S. Patent Application Pub. No. 2006/0221692. The read and verify operations described above are performed according to techniques known in the art. Thus, many of the details explained can be varied by one skilled in the art. Other read and verify techniques known in the art can also be used.

In some embodiments, the program voltage applied to the control gate includes a series of pulses that are increased in magnitude with each successive pulse by a predetermined step size (e.g. 0.2 v, 0.3 v, 0.4 v, or others). Between pulses, some memory systems will verify whether the individual memory cells have reached their respective target threshold voltage ranges. For example, FIG. 9 shows a portion of a signal applied to the control gates of a plurality of memory cells connected to a common word line. FIG. 9 shows programming pulses 564, 565 and 566, with a set of verify pulses between the programming pulses. When performing full sequence programming in one embodiment, the verification process between programming pulses will test for each of the threshold voltage distribution (data states) S1-S7. Therefore, FIG. 9 shows seven verify pulses that have magnitudes corresponding to verify target levels Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7. In some embodiments, one or more of the verify operations can be skipped (and, therefore one or more of the verify pulses can be skipped) because the verify operation is not necessary or superfluous. For example, if none of the memory cells being programmed according to FIG. 8 have reached Vv2, there is no reason to verify at Vv7. More information about intelligent verification schemes that skip verification for one or more states can be found in the following patent documents which are incorporated herein by reference in their entirety: U.S. Pat. Nos. 7,073,103; 7,224,614; 7,310,255; 7,301,817; U.S. Patent App. 2004/0109362; and U.S. Patent App. 2009/0147573.

FIG. 8 shows a programming process that includes one phase where all memory cells connected to the same word line are programmed concurrently during that one phase. FIGS. 10A-E illustrates a multi-phase programming approach. In this embodiment, the programming process includes three phases. Prior to programming, the memory cells are erased so that all memory cells connected to a common word line are in an erased threshold voltage distribution E, as depicted in FIG. 10A. During the first phase of programming, those memory cells whose targets (due to the data to be stored in those memory cells) are data states S4, S5, S6 or S7 are programmed to an intermediate state IM. Those memory cells are targeted for data states S0, S1, S2 or S3 and remain in the erased threshold voltage distribution E. The first phase is graphically depicted by FIG. 10B. Memory cells being programmed to intermediate state IM are programmed to a target threshold voltage of VvIM.

During the second phase of the programming process of FIGS. 10A-E, those memory cells that are in the erased threshold voltage distribution E are programmed to their target data states. For example, those memory cells to be programmed to data state S3 are programmed from erased threshold voltage distribution E to data state S3, those memory cells to be programmed to data state S2 are programmed from erased threshold voltage distribution E to data state S2, those memory cells to be programmed to data state S1 are programmed from erase threshold voltage distribution E to data state S1, and those memory cells to be in data state S0 are not programmed during the second phase of the programming process. Thus, erased threshold voltage distribution E becomes data state S0. Also, during the second phase, memory cells are programmed from the intermediate state IM to various data states S4-S7. For example, those memory cells to be programmed to data state S7 are programmed from the intermediate state IM to data state S7, those memory cells targeted to be in data state S6 are programmed from intermediate state IM to data state S6, both memory cells to be programmed to data state S5 are programmed from intermediate state IM to data state S5, and those memory cells to be programmed to data state S4 are programmed from intermediate state IM to data state S4. This second phase of programming is illustrated in FIG. 10C.

As can be seen in FIG. 10C, at the end of the second phase of programming data states S1-S7 overlap with neighboring data states. For example, data state S1 overlaps with data state S2, data state S2 overlaps with data states S1 and S3, data state S3 overlaps with data states S2 and S4, data state S4 overlaps with data states S3 and S5, data state S5 overlaps with data states S4 and S6, and data state S6 overlaps with data states S5 and S7. In some embodiments, all or some of the data states do not overlap.

In the third phase of programming, each of data states S1-S7 are tightened so that they no longer overlap with neighboring states. This is depicted graphically by FIG. 10D. The final result of the three phrase programming process is depicted in step 10E, which shows data states S0-S7. In some embodiments, data state S0 is wider than data states S1-S7.

In some embodiments, those memory cells to be programmed to data state S4 are not programmed during the second phase and, therefore, remain in intermediate state IM. During the third programming phase, the memory cells are programmed from IM to S4. In other embodiments, memory cells destined for other states can also remain in IM or E during the second phase.

FIG. 11 is a flow chart describing one embodiment of a process for performing programming on memory cells connected to a common word line to one or more targets (e.g., data states or threshold voltage ranges). The process of FIG. 11 can be performed one or multiple times during step 556 of FIG. 7. For example, the process of FIG. 11 can be used to program memory cells (e.g., full sequence programming) from state S0 directly to any of states S1-S7. Alternatively, the process of FIG. 11 can be used to perform one or each of the phases of the process of FIG. 10A-E. For example, when performing the process of FIG. 10A, the process of FIG. 11 is used to implement the first phase that includes programming some of the memory cells from state E to state IM. The process of FIG. 11 can then be used again to implement the second phase that includes programming some of the memory cells from state E to states S1-S3 and from state IM to states S4-S7. The process of FIG. 11 can be used again to adjust states S1-S7 in the third phase (see FIG. 10D). The process of FIG. 11 can also be used with other multi-phase programming processes.

Typically, the program voltage applied to the control gate during a program operation is applied as a series of program pulses. Between programming pulses are a set of verify pulses to perform verification. In many implementations, the magnitude of the program pulses is increased with each successive pulse by a predetermined step size. In step 570 of FIG. 11, the programming voltage (Vpgm) is initialized to the starting magnitude (e.g., ˜12-16V or another suitable level) and a program counter PC maintained by state machine 222 is initialized at 1. In step 572, a program pulse of the program signal Vpgm is applied to the selected word line (the word line selected for programming). In one embodiment, the group of memory cells being programmed concurrently are all connected to the same word line (the selected word line). The unselected word lines receive one or more boosting voltages (e.g., ˜7-11 volts) to perform boosting schemes known in the art. If a memory cell should be programmed, then the corresponding bit line is grounded. On the other hand, if the memory cell should remain at its current threshold voltage, then the corresponding bit line is connected to Vdd to inhibit programming. In step 572, the program pulse is concurrently applied to all memory cells connected to the selected word line so that all of the memory cells connected to the selected word line are programmed concurrently. That is, they are programmed at the same time (or during overlapping times). In this manner all of the memory cells connected to the selected word line will concurrently have their threshold voltage change, unless they have been locked out from programming.

In step 574, the appropriate memory cells are verified using the appropriate set of target levels to perform one or more verify operations. In one embodiment, the verification process is performed by applying the testing whether the threshold voltages of the memory cells selected for programming have reached the appropriate verify compare voltage (Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7).

In step 576, it is determined whether all the memory cells have reached their target threshold voltages (pass). If so, the programming process is complete and successful because all selected memory cells were programmed and verified to their target states. A status of “PASS” is reported in step 578. If, in 576, it is determined that not all of the memory cells have reached their target threshold voltages (fail), then the programming process continues to step 580.

In step 580, the system counts the number of memory cells that have not yet reached their respective target threshold voltage distribution. That is, the system counts the number of cells that have failed the verify process. This counting can be done by the state machine, the controller, or other logic. In one implementation, each of the sense block 300 (see FIG. 3) will store the status (pass/fail) of their respective cells. These values can be counted using a digital counter. As described above, many of the sense blocks have an output signal that is wire-Or'd together. Thus, checking one line can indicate that no cells of a large group of cells have failed verify. By appropriately organizing the lines being wired-Or together (e.g., a binary tree-like structure), a binary search method can be used to determine the number of cells that have failed. In such a manner, if a small number of cells failed, the counting is completed rapidly. If a large number of cells failed, the counting takes a longer time. More information can be found in United States Patent Publication 2008/0126676, incorporated herein by reference in its entirety. In another alternative, each of the sense amplifiers can output an analog voltage or current if its corresponding memory cell has failed and an analog voltage or current summing circuit can be used to count the number of memory cells that have failed.

In one embodiment, there is one total count, which reflects the total number of memory cells currently being programmed that have failed the last verify step. In another embodiment, separate counts are kept for each data state.

In step 582, it is determined whether the count from step 580 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by ECC during a read process for the page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, than the programming process can stop and a status of “PASS” is reported in step 578. In this situation, enough memory cells programmed correctly such that the few remaining memory cells that have not been completely programmed can be corrected using ECC during the read process. In some embodiments, step 580 will count the number of failed cells for each sector, each target data state or other unit, and those counts will individually or collectively be compared to a threshold in step 582.

In another embodiment, the predetermined limit can be less than the number of bits that can be corrected by ECC during a read process to allow for future errors. When programming less than all of the memory cells for a page, or comparing a count for only one data state (or less than all states), than the predetermined limit can be a portion (pro-rata or not pro-rata) of the number of bits that can be corrected by ECC during a read process for the page of memory cells. In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors already counted for the page, the number of program-erase cycles performed, temperature or other criteria.

If number of failed memory cells is not less than the predetermined limit, than the programming process continues at step 584 and the program counter PC is checked against the program limit value (PL). Examples of program limit values include 20 and 30; however, other values can be used. If the program counter PC is not less than the program limit value PL, then the program process is considered to have failed and a status of FAIL is reported in step 588. If the program counter PC is less than the program limit value PL, then the process continues at step 586 during which time the Program Counter PC is incremented by 1 and the program voltage Vpgm is stepped up to the next magnitude. For example, the next pulse will have a magnitude greater than the previous pulse by a step size (e.g., a step size of 0.1-0.4 volts). After step 586, the process loops back to step 572 and another program pulse is applied to the selected word line.

FIG. 12 is a flow chart describing one embodiment of a process for reading data. The depicted method reduces the effects of read disturb (described above).

In many memory systems, the end word lines (e.g. word lines at or close to the select gates of a NAND string) are wider than the middle word lines (word lines that are between the end word lines) in a memory array due to process limitations. In other embodiments, other critical dimensions can also vary for the end word lines as compared to the middle word lines. As memory cells scale down to smaller sizes, the difference in width between the end and middle word lines will become even more of a disparity. In NAND flash memory, the wider word lines at the end will provide a stronger coupling between the control gate and floating gate, which results in faster programming and a higher chance of Read Disturb occurring. Although error correction (ECC) can be used to fix errors in the data, if there are too many errors, even ECC will not work.

Previous systems have used dynamic read compare levels to reduce failures. For example, Vr1, Vr2, Vr3, . . . are periodically recomputed. However, this may not be sufficient if the Read Disturb is severe enough on the end word lines.

A memory system could also lower the pass voltage (e.g. Vread—see below) applied to unselected word lines to reduce the overall Read Disturb. However, this would cause a higher NAND string resistance to the downscaling of the pass voltage, thereby reducing the accuracy of the read process.

To reduce the effects of Read Disturb due to the end word lines being wider, the process of FIG. 12 proposes to use a lower pass voltage at the end of the NAND strings as compared to the middle of the NAND strings. Step 600 of FIG. 12 includes applying voltage signals to the source line, source select line SGS and drain select line SGD (see FIGS. 2 and 5). In step 602, a lower read pass voltage, VreadL, is applied to memory cells at the ends of the NAND string. In step 604, the standard read pass voltage, Vread, is applied to the middle memory cells, which are those memory cells between the ends of the NAND string that are not selected for reading. In step 606, a higher read pass voltage, VreadK, is applied to those memory cells of the NAND string that are neighbors to the selected memory cell. In step 608, the read compare voltage, Vcgr, is applied to the selected memory cell. In step 610, the system will sense the current through the selected memory cell in response to the voltages applied in steps 600-608.

In many embodiments, the system will read multiple memory cells at the same time. Therefore, the process of 600-610 will be performed concurrently on multiple NAND strings of the same block such that multiple memory cells will be read concurrently.

FIG. 13 shows three NAND strings 650, 652 and 654 of a block of memory cells implementing the process of FIG. 12. In the example embodiment of FIG. 13, a NAND string will include x+1 memory cells. Therefore, the block of NAND strings will include x+1 word lines (WL0-WLx). In the depicted example, word line WLn is selected for reading; therefore, all the memory cells connected to WLn will be read. As per step 608 of FIG. 12, FIG. 13 shows WLn receiving Vcgr, the read compare voltage. As per step 606 of FIG. 12, FIG. 13 shows neighboring word lines WLn−1 and WLn+1 receiving the higher read pass voltage, VreadK. As per step 604 FIG. 12, FIG. 13 shows the word lines (WL1, WL2. . . . WLN−2, WLN+2, . . . . WLx−3, WLx−2, WLx−1) that are not connected to end memory cells receiving the standard read pass voltage, Vread. As per step 602 of FIG. 12, FIG. 13 shows the end word lines (in the example, the word lines at the extreme end of the NAND string), WL0 and WLx, receiving the lower read pass voltage VreadL. In this embodiment, the various voltages Vread, VreadL and VreadK are provided to the control gates of the respective memory cells by applying the voltages to the word lines, which are connected to the control gates of memory cells. As seen from FIG. 13, each word line is connected to the control gate of multiple memory cells so that the read and programming operations are performed in parallel.

FIG. 14 is a timing diagram depicting the behavior of various signals during one iteration of a read or verify operation (e.g., the process of FIG. 12). For example, if the memory cells are binary memory cells, the process of FIG. 14 may be performed in parallel for each memory cell during a read or verify process. If the memory cells are multi-state memory cells, the process of FIG. 14 may be performed multiple times for each memory cell in parallel during a read or verify process. For example, when reading data from a memory cell with eight states, the read process may be performed once with Vcgr=Vr1, once with Vcgr=Vr2, once with Vcgr=Vr3, once with Vcgr=Vr4, once with Vcgr=Vr5, once with Vcgr=Vr6, and once with Vcgr=Vr7. Other sets of read values can also be used and some embodiments will perform less than all of the read operations based on a need to read only a subset of pages of data or other reasons.

FIG. 14 shows signals SGD, WL_unsel, WL_unsel_neighbor, WL_unsel_end, WLn, SGS, Selected BL, and Source starting at Vss (approximately 0 volts). SGD represents the signal on the drain select line connected to the gate of the drain select gate. SGS represents the signal on the source select line connected to the gate of the source select gate. WLn is the word line selected for reading/verification. WL_unsel_neighbor represents the unselected word lines that are adjacent to the selected word line. WL_unsel_end represents the unselected word lines that are connected to memory cells at the end of the NAND strings. WL_unsel represents the unselected word lines that are not WL_unsel_neighbor and WL_unsel_end. Selected_BL is the bit line selected for reading/verification. Source is the source line for the memory cells.

FIG. 14 describes the behavior of a system that measures the conduction current of a memory cell by determining whether the bit line has appropriately discharged. At time t1 of FIG. 14, SGD is raised to Vdd (e.g., approximately 3.5 volts) or another voltage, typically in the 3-5V range, the unselected word lines (WL_unsel) are raised to Vread (e.g., approximately 7.4 volts), the unselected word lines that are next to the selected word line (WL_unsel_neighbor) are raised to VreadK (e.g., ˜Vread+0.6 volts)), the unselected word lines at the end of the NAND string (WL_unsel_end) are raised to VreadL (e.g., ˜Vread−0.1 v), the selected word line WLn is raised to Vcgr, and the selected bit line Selected BL is precharged to approximately 0.7 volts. The voltages Vread, VreadK and VreadL act as pass voltages because they cause the unselected memory cells to turn on and act as pass gates. At time t2, the source select gate is turned on by raising SGS to Vdd. This provides a path to reduce the charge on the bit line. If the threshold voltage of the memory cell selected for reading is greater than Vcgr, then the selected memory cell will not turn on (or at least will not turn on sufficiently) and the bit line will not discharge (or at least will not discharge sufficiently), as depicted by signal line 690. If the threshold voltage in the memory cell selected for reading is below Vcgr, then the memory cell selected for reading will turn on (conduct) and the bit line voltage will decrease, as depicted by curve 692. At some point after time t2 and prior to time t3 (as determined by the particular implementation), the appropriate sense amplifier will determine whether the bit line voltage has decreased by a sufficient amount. At time t3, the depicted signals will be lowered to Vss (or another value for standby or recovery). Note that in other embodiments, the timing of some of the signals can be changed.

As mentioned above, techniques of detecting of the openness of a block of memory cells are desired, in order to select ideal read parameters used during the read operation thereby reducing current consumption. For FIGS. 1-16, the word lines are discussed or represented are numbered as physical word lines (i.e., actual physical signal lines, numbered with lower numbered word lines disposed vertically lower in a stack of word lines and higher numbered word lines disposed vertically higher in the stack), whereas for FIG. 17 onward, any word line numbers discussed or represented are logical word line numbers (i.e., word lines mapped to physical word lines, numbered with higher numbered word lines disposed vertically lower in a stack of word lines and lower numbered word lines disposed vertically higher in the stack herein, however, other mapping may be used alternatively). FIG. 17 shows plots of current consumption during a read operation for various word lines and for different pages when the block is in various states of openness. As shown, the current consumption is almost the same for different block openness for word lines with memory cells that are programmed. However, for the word lines with memory cells that are erased, the current consumption during the read operation for different block openness varies. FIG. 18 shows plots of current consumption for the read operation of logical word line WL1 and logical word line WL161 when the block is in various states of openness and for various amounts of erase/programming cycles. As shown, for the programmed word line (logical word line WL1), the read current consumption ICC for different block openness is almost consistent. For the erased word line (logical word line WL161), the read current consumption ICC for different block openness varies, especially at and after the fourth time period of the read operation. The peak current consumption during the fourth period of time (i.e. R4 peak) shows a clear difference with different OB ratios, which is good to distinguish between these ratios for different current consumption. This difference is distinctive and consistent, it will also remain consistent after program/erase cycles, as well. If the openness of the block is known, optimum bit line and word line biases can be used to reduce the impact of high Icell (current in the channel of a memory hole) from erased word lines of an open block. Most open block detection solutions typically require reading several word lines and record the last programmed word line at a system level, however, such an approach is time consuming. Thus, effective on-chip open block detection methods are desired.

Consequently, described herein is a memory apparatus (e.g., memory device 210 of FIG. 3) including memory cells (e.g., transistors 100, 102, 104 and 106 of FIGS. 1 and 2) configured to retain a threshold voltage corresponding to one of a plurality of data states (e.g., states S0-S7 of FIG. 8). The memory cells are disposed in memory holes (e.g., NAND string of FIGS. 1 and 2) coupled to a plurality of bit lines (e.g., BL0-BL5 of FIG. 5) and grouped into a plurality of blocks (e.g., block 0-block 1023 of FIG. 5). The memory apparatus also includes a control circuit or means (e.g., one or any combination of controller 244 of FIG. 3, decoders 240A, 240B, 242A, 242B, read/write circuits 230A, 230B, control circuitry 220 of FIG. 3 and so forth) coupled to the plurality of bit lines. The control means is configured to determine an amount of the memory cells of one of the plurality of blocks that are programmed based on an electrical current consumed by the memory apparatus during a fourth period of time R4 of a read operation in which selected ones of the plurality of bit lines are ramped up to a bit line voltage VBLC. The bit line voltage VBLC is applied to the plurality of bit lines while determining whether the memory cells connected thereto are conductive or not. The control means is also configured to adjust at least one read parameter based on the amount of the memory cells of the one of the plurality of blocks that are programmed. The control means is additionally configured to utilize the adjusted at least one read parameter while reading the memory cells to determine if the memory cells have the threshold voltage above one or more of a plurality of read levels associated with each of the plurality of data states in the read operation.

Referring back to FIGS. 1, 2, 5, and 13, for example, the memory cells are each connected to one of a plurality of word lines (e.g., physical WL0-WL3 of FIG. 2). In addition, the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack. The memory holes extend vertically through the stack. The memory cells are connected in series between a drain-side select gate SGD transistor (e.g., SGD of FIG. 2 or 5) on a drain-side of each of the memory holes and a source-side select gate SGS transistor (e.g., SGS of FIG. 2 or 5) on a source-side of each of the memory holes. The drain-side select gate SGD transistor of each of the memory holes is connected to one of the plurality of bit lines (e.g., BL0-BL5 of FIG. 5) and the source-side select gate SGS transistor of each of the memory holes is connected to a source line (e.g., source of FIG. 5). The plurality of word lines includes a bottom word line (e.g., physical WL0 of FIG. 13) vertically disposed adjacent a bottom of the stack and a top word line (e.g., physical WLx of FIG. 13) vertically disposed adjacent a top of the stack. The memory cells connected to the plurality of word lines are programmed in a programming order beginning with one of the bottom word line and the top word line and progressing vertically through the stack. So, according to an aspect, the control means is further configured to determine the amount of the memory cells of the one of the plurality of blocks that are programmed based on the electrical current consumed by the memory apparatus during the fourth period of time R4 of the read operation while reading the memory cells connected to the bottom word line (if the bottom word line is programmed last) or the top word line (if the top word line is programmed last). Referring back to FIG. 17 and according to an aspect, when memory cells of the top word line are programmed first, the bottom word line (logical word line WL161 of FIG. 17) is the last word line that will be programmed and can be used for the open block detection.

According to another aspect, the memory apparatus may further include a power circuit configured to measure an electrical current consumed by the memory apparatus (e.g., power control 226 of FIG. 3). In addition, with reference back to FIGS. 15 and 16, for example, the read operation includes a first period of time R1 in which the plurality of word lines begin ramping up to a read pass voltage VREAD and a second period of time R2 in which the bit line voltage VBLC applied to the plurality of bit lines is ramped up to a cell select voltage VCELSRC and the plurality of word lines reach the read pass voltage VREAD. FIG. 19 shows a plot of current consumption for the read operation of one of the word lines (e.g., logical word line WL161) when the block is in various states of openness and for various amounts of erase/programming cycles along with the open block ratio corresponding to various current consumption values. The first period of time R1, the second period of time R2, and the fourth period of time R4 are also shown. The difference in the current consumption ICC peak for different OB ratios is sufficiently large for sensitive and reliable OB detection.

FIG. 20 is a plot of voltages applied to unselected and selected drain-side select gate transistors, a source-side select gate transistor, the one of the top and the bottom word lines, an unselected one of the plurality of word lines, the source line (CELLSRC), and a bit line (BL) while detecting the openness of the block. So, as shown and according to an aspect, the control means is further configured to ramp up the plurality of word lines to the read pass voltage VREAD during the first period of time R1 and the second period of time R2 of the read operation. The control means is also configured to lower the bottom word line (if the bottom word line is programmed last) or the top word line (if the top word line is programmed last) to a steady state voltage VSS. The control means ramps up the plurality of bit lines to the bit line voltage VBLC and a source line voltage applied to the source line to the cell select voltage VCELSRC. Using the power circuit, the control means is configured to detect the electrical current consumed by the memory apparatus during the fourth period of time R4 of the read operation. In addition, the control means is configured to decide an open block ratio according to the electrical current consumed by the memory apparatus detected by the power circuit, the open block ratio corresponding with the amount of the memory cells of the one of the plurality of blocks that are programmed. The control means is also configured to adjust at least one read parameter based on the open block ratio.

In more detail and according to further aspects, the control means is further configured to lower selected ones of the plurality of word lines to a read compare voltage for the one or more of the plurality of read levels while raising the bottom word line (e.g., logical word line WL161) (if the bottom word line is programmed last) or the top word line (if the top word line is programmed last) to the read pass voltage VREAD. However, if the block is not fully closed (i.e., closed block CB), there is no need to take time raise the one of the top and the bottom word line bias back to the read pass voltage VREAD. The control means is also configured to continue the read operation using the adjusted at least one read parameter while reading the memory cells to determine if the memory cells have the threshold voltage above the one or more of the plurality of read levels associated with each of the plurality of data states.

The technique of detecting openness described herein using the current consumption ICC during the fourth period of time R4 requires only a one time detection and OB ratio judgement for the whole block read. Thus, this technique saves a significant amount of time and also gives accurate results of current consumption ICC for both fresh blocks (those with little or no program/erase cycles) and after numerous program/erase cycles. As discussed, the current consumption ICC during the fourth period of time R4 difference for different OB ratios is sufficiently large for sensitive and reliable OB detection. This technique also does not have much read time tRead penalty, as the read pass voltage VREAD has already ramped up for selected blocks/strings, the control gate CG bias only needs to be lowered on the selected word line to the read level, and continue read operation for the block.

While the current consumption after the fourth period of time R4 of the read operation contributes most to the average current consumption during the read operation, the current consumption during the fourth period of time R4 can also be lowered while maintaining the accuracy of the openness detection. According to an additional aspect, the control means is further configured to adjust at least one of the bit line voltage VBLC and a voltage of the source line to reduce the electrical current consumed during the fourth period of time R4 of the read operation.

FIG. 21 shows plots of average current consumption ICC for various open block ratios at high temperature (HT) and low temperature (LT) for a fast read (FR) and a normal read (NR). As discussed above, when there is an open block (OB) (i.e., none or very few of the memory cells of the block are programmed), it has been observed that depending on an open block ratio (percentage of openness of the block), a current consumption ICC variation is seen. In more detail, there is a current consumption ICC variation for closed block (CB) (i.e., all or significantly all of the memory cells of the block are programmed) vs OB blocks. Also, current consumption ICC variation is very significant from 0% OB compared to 99% OB. In one example, the current consumption ICC increased ˜35%+ going from CB to 99% OB. As a result, there is huge penalty of power consumption, because in some implementations (e.g., iNAND), there may be multiple instances where a partial block is written and read. In such cases, current consumption ICC would increase for OB and will vary depending on the OB percentage.