₁located above is connected to the drain of the power device S₂located below and used as a neutral point to lead out the parallel switching branch current (recorded as branch current i₁, branch current i₂, . . . , branch current in respectively). The gates of the two power devices S₁and S₂included in each parallel switching branch are used to receive control signals to control the led-out branch currents i₁˜i_n. Each parallel switching branch current, after passing through the cascaded coupling network, finally generates the U-phase input current i_Uof a motor. The topology structure and working principle of the control parts of the V-phase and the W-phase are the same as those of the U-phase.

The inverter parallel topology formed by connecting the above-mentioned power devices constructed of multiple SiC MOSFETs in parallel may meet the working conditions of high current, high power, and high switching speed. However, the large number of power devices in the parallel topology will bring greater losses, thereby generating a large amount of heat and causing damage to the power devices. Furthermore, through actual measurement of the switching losses of each parallel switching branch during the entire switching cycle using a simulation machine, it was found that the switching loss of the parallel switching branch composed of two silicon carbide based power devices S₁and S₂connected in series changes significantly depending on the load conditions. Especially under light load operating conditions or even a no-load operating condition, the switching loss of each parallel switching branch increases significantly, resulting in a phenomenon where the load current is small but the system loss is large.

This application uses the H-bridge type parallel multi-level inverter switch module and the inverter using the module provided in the embodiments described below to solve the problem that the switching loss of each parallel switching branch under the above light load operating conditions increases significantly. In order to clearly explain the improvements of the technical solution of the present application compared to the conventional technique, the mechanism behind the above problems will be described in detail first.

[Switching Losses of Parallel Multi-Level Inverters Under Various Operating Conditions]

The analysis of switching losses of parallel multi-level inverters can be achieved by analyzing one of the parallel switching branches. To this end, a double-pulse switching circuit analysis model as shown in FIG. 2 can be built. In FIG. 2, the power device S₁and S₂are respectively shown as their equivalent models. As shown in FIG. 2, from left to right, the power device S₁includes a high-level turn-on channel, a Schottky diode D₁, and a parasitic output capacitor C₁. Similarly, from left to right, the power device S₂includes a high-level turn-on channel, a Schottky diode D₂, and a parasitic output capacitor C₂. V_dcis a bus voltage, and C_dcis a bus capacitor, R and L are inductive loads in the double-pulse circuit. In some embodiments, the two power devices in a parallel switching branch can use the same specifications. Therefore, the parameter values of S₁and S₂are the same.

FIG. 3A is a signal timing diagram for applying pulse signals to the gates of the power devices S₁and S₂to complete a complete switching cycle. With reference to FIG. 2, it can be seen that the entire switching cycle includes two switching processes, where S₁goes from off to on in a switching process 1 and S₂goes from on to off in a switching process 2.

FIG. 3B and FIG. 3C respectively show the direction situation of the current flow of the power device S₂during the turn-on and turn-off processes. The switching process of S₂can be defined as a forward switching process where the parasitic output capacitor of the power device S₂releases electric charges during the turn-on process of S₂, making the current flowing through its channel greater than the drain current, increasing the turn-on loss of the channel (in the present application, it is stipulated that when the current flows from the drain to the source, the lost energy of the power device is positive; when the current flows from the source to the drain, the lost energy of the power device is negative; when the parasitic output capacitor discharges, the lost energy of the power device is positive; when the parasitic output capacitor charges, the lost energy of the power device is negative); and where the parasitic output capacitor of the power device S₂absorb electric charges during the turn-off process of S₂, making the current flowing through the channel less than the drain current, reducing the turn-off loss of the channel. The increased loss and decreased loss are approximately equal, so the energy of the output capacitor will not be considered as a part of the switching loss.

The structure of SiC MOSFET is different from that of S₁IGBT (silicon-insulated gate bipolar transistor). There is a synchronous rectification mode. In this synchronous rectification mode, the current will flow in the opposite direction through the channel and its parallel diode at the same time. At this time, the SiC MOSFET will experience a reverse switching process, the above-mentioned switching process is a process that the power device S₁goes through in a complete switching cycle. Therefore, the switching process of S₁can be defined as a reverse switching process.

In summary, the switching process 1 can be used to simulate a process in which the power device S₁is turned off in reverse and the power device S₂is turned on in forward, and the switching process 2 can be used to simulate a process in which the power device S₁is turned on in reverse and the power device S₂is turned off in forward.

A. Analysis of Switching Losses of Power Devices S₁and S₂in Switching Process 1 Under Heavy Load Operating Condition

FIG. 4A shows changes in the gate signals and the voltage and the current at various locations of the power devices S₁and S₂in the switching process 1, where T_dis the dead time of the power devices S₁and S₂, V_gs1is the gate-source voltage of S₁, V_th+(i_A/g_fs) is the Miller plateau voltage of the power devices S₁and S₂, V_this the threshold voltage of the power devices S₁and S₂, V_ds1is the drain-source voltage of S₁, V_channelis the turn-on voltage drop of the power devices S₁and S₂, V_dcis the bus voltage, V_diodeis the turn-on voltage drop of the Schottky diodes D₁and D₂, i_d1is the drain current of S₁, i_channel1is the channel current of S₁, Q_COSSis the charge stored in the parasitic output capacitor, V_gs2is the gate-source voltage of S₂, V_dS2is the drain-source voltage of S₂, i_d2is the drain current of S₂, i_channel2is the channel current of S₂.

FIG. 5Aa to FIG. 5E respectively show the direction situation of the current flow of the power devices S₁and S₂in each interval of the switching process 1. With reference to FIG. 4A, the switching loss of the power device S₁and S₂in the switching process 1 under heavy load operating conditions can be analyzed.

Interval 1 (t<t₀): as shown in FIG. 5A, S₁is turned on and S₂is turned off. At this time, the flow of the load current is sustained by the channel of S₁and the Schottky diode D₁.

Interval 2 (t₀−t₁): as shown in FIG. 5A, at time to, S₁begins to be turned off, and V_gs1begins to decrease. In interval 2, V_gs1does not decrease to the Miller plateau, and the flow of the load current is still sustained by the channel of S₁and the Schottky diode D₁, and the current path is similar to that of interval 1.

Interval 3 (t₁−t₂): as shown in FIG. 5A, at time t₁, V_gs1drops to the Miller plateau. At this time, the channel of S₁begins to turn off, and the current flowing through the channel begins to decrease, the current in the Schottky diode D₁gradually increases. In interval 3, the channel of S₁is not completely turned off, and the flow of the load current is still sustained by the channel of S₁and the Schottky diode D₁.

Interval 4 (t₂−t₃): as shown in FIG. 5B, at time t₂, V_gs1drops to the threshold voltage V_th, and the channel of S₁is completely turned off. In interval 4, the flow of the load current is completely sustained by the Schottky Diode D₁of S₁.

Interval 5 (t₃−t₄): as shown in FIG. 5B, at time t₃, the dead zone ends and S₂starts to turn on. V_gs2begins to rise, but in interval 5, V_gs2is always less than the threshold voltage V_th, the load current does not flow through S₂, and the flow of the load current is still sustained by the Schottky diode D₁of S₁.

Interval 6 (t₄−t₅): as shown in FIG. 5C, at time t₄, V_gs2rises to V_thand continues to rise, the channel of S₂begins to turn on, and a part of the load current flows through the channel of S₂. In interval 6, as V_gs2rises, the current flowing through the channel of S₂gradually increases, and the current flowing through the Schottky diode D₁decreases, but the diode is always turned on, so V_ds2is always clamped near V_dc.

Interval 7 (t₅−t₆): as shown in FIG. 5D, at time t₅, V_gs2rises to the Miller plateau. At this time, the channel of S₂is fully turned on, the load current completely flows through the channel of S₂, the Schottky diode D₁is turned on, and V_ds2starts to fall. Since the Schottky diode D₁is previously turned on to sustain the current flow, V_ds2is clamped near V_dc, and the charge stored in the parasitic output capacitor C₂cannot be released. At the moment when the channel is fully turned on, the charge Q_cossstored in C₂is released through the channel of S₂. At the same time, the charging current of the DC power supply to the parasitic output capacitor C₁also flows through the channel of S₂, and a charge of 2Q_cosswill flow through the channel and cause loss.

Interval 8 (t>t₆): as shown in FIG. 5E, after the charging and discharging processes of the output capacitors are finished, the load current completely flows through the channel of S₂and returns to the DC power supply, and the circuit enters a steady state.

B. Analysis of Switching Losses of Power Devices S₁and S₂in Switching Process 2 Under Heavy Load Operating Condition

FIG. 4B shows changes in the gate signals and the voltage and the current at various locations of the power devices S₁and S₂in the switching process 2. The direction situation of the current flow of the power devices S₁and S₂in each interval of the switching process 2 can be analyzed similarly to the switching process 1.

By analyzing the current conditions of the power devices S₁and S₂at each stage of a complete switching cycle under heavy load operating conditions, it can be seen that due to the voltage clamping phenomenon of the Schottky diode, the actual loss of the forward turn-on process of the power device S₁is more than the measured loss by the energy stored in output capacitors, while the actual loss of the forward turn-off process is less than the measured loss by the energy of output capacitors. The two cancel each other out, so the loss of the forward switching of the power device S₁in a complete switching cycle is consistent with the loss obtained by the integral method, that is, there is no additional forward switching loss due to any parasitic output capacitor. At the same time, when the power device S₁undergoes a complete switching cycle under heavy load operating conditions, due to the parasitic output capacitor being completely discharged, the loss obtained by the integral method is basically consistent, that is, the additional reverse switching loss is almost zero.

C. Analysis of Switching Losses of Power Devices S₁and S₂in Switching Process 2 Under Light Load Operating Condition

Generally speaking, when the output current is less than or equal to 10% of the rated operating point current, it can be considered to be in a light load operating condition. Compared with heavy load operating conditions, in light load operating conditions, the load current in the circuit will be much smaller because the voltage clamping phenomenon of the Schottky diode will still occur in process 1. Therefore, the forward turn-on process of S₁and the reverse turn-off process of S₂under light load operating conditions are similar to those under heavy load operating conditions. The forward turn-on loss of S₁and the reverse turn-off loss of S₂under light load operating conditions have no difference from those under heavy load operating conditions.

FIG. 6 shows changes in the gate signals and the voltage and the current at various locations of the power devices S₁and S₂in the switching process 2 under light load operating conditions. FIG. 7A and FIG. 7B respectively show the direction situation of the current flow at various locations of the power devices S₁and S₂at time t₃*−t₄* and time t₄*−t₅* of the switching process 2.

From FIG. 6, FIG. 7A, and FIG. 7B, it can be seen that the difference between the switching losses of the power devices S₁and S₂under light load operating conditions and those under heavy load operating conditions is mainly that under heavy load operating conditions, at time t₃which is before the dead time T_dends, the drain-source voltage V_dsof S₁has dropped to zero. However, under light load operating conditions, at time t₄* which is after the dead zone ends, the drain-source voltage V_dsof S₁still has not dropped to zero.

t₃*−t₄*: as shown in FIG. 7A, under light load operating conditions, the load current is small. Although the load current is all used to charge and discharge the parasitic output capacitor during the dead time, at time t₄, there is still part of the charge is stored in the parasitic output capacitor C₁, and the drain-source voltage V_ds1of S₁does not drop to zero.

t₄*−t₅*: as shown in FIG. 7B, at time t₄*, the channel of S₁begins to turn on. At the moment when the channel is turned on, part of the charge Q_coss* stored in the parasitic output capacitor C₁is released through the channel of S₁. At the same time, the charging current of the power supply to the output capacitor C₂of S₂also flows through the channel of S₁, and there will be a loss generated by the charge of 2Q_coss*.

By analyzing the current situation of the power devices S₁and S₂at each stage of a complete switching cycle under light load operating conditions, it can be seen that due to the light load operating condition, at time t₄* which is after the dead zone ends, there is still a part of charge stored in the parasitic output capacitor C₁, so that the drain-source voltage V_dsof S₁still does not drop to zero, causing part of the charge Q_coss* stored in the parasitic output capacitor C₁to be released through the channel of S₁. Therefore, when the power device S₁undergoes a complete switching cycle under light load operating conditions, since the parasitic output capacitor is not fully discharged, the actual reverse switching loss will be larger than the loss obtained by the integral method, that is, the inadequate discharge of the parasitic output capacitor under light load operating conditions is the main reason for the additional reverse switching loss of the power device S₁.

[H-Bridge Type Parallel Multi-Level Inverter Switch Module and Inverter Using the Switch Module]

Aiming at the causes of additional reverse switching loss in the parallel multi-level inverter constructed with silicon carbide based power devices, the present application improves the existing inverter structure. FIG. 8 shows the topology of the U-phase control part of the inverter provided according to some embodiments of the present application. As shown in FIG. 8, the U-phase control part of the inverter includes n H-bridge type parallel multi-voltage inverter switch modules, which are marked as switch module 1, . . . , and switch module n respectively.

As shown in FIG. 8, the switch module 1 includes two switching units 100 connected in parallel, and an H-bridge inductor 200.

Each switching unit 100 is equivalent to a parallel switching branch in FIG. 1 and includes a first power device 101 and a second power device 102 connected in series, where the source of the first power device 101 is connected to the drain of the second power device 102, and this connection point is used as a neutral point 103 of the switching unit. In some embodiments, as shown in FIG. 8, a branch current i₁is led out of the neutral point 103 of the switching unit 100 on the left of the switch module 1 and flows to the cascaded coupling network 300, and a branch current i₂is led out of the neutral point 103 of the switching unit 100 on the right and flows to the cascaded coupling network 300. The branch current i_2n-1is led out of the neutral point 103 of the switching unit 100 on the left of the switch module n and flows to the cascaded coupling network 300, and the branch current i_2nis led out of the neutral point 103 of the switching unit 100 on the right and flows to the cascaded coupling network 300. The remaining branch currents flow to the cascaded coupling network 300 in FIG. 8 in the same way.

The drains of the first power devices 101 of the two switching units 100 are connected to each other, and the sources of the second power devices 102 of the two switching units 100 are connected to each other. During the actual inversion process, the drain of each first power device 101 mentioned above is connected to the positive pole of the DC power supply, and the source of each second power device 102 is connected to the negative pole of the DC power supply, thereby forming a parallel multi-level switching topology similar to FIG. 1. In some embodiments, according to the aforementioned analysis, the switching process performed by the two first power devices 101 is a reverse switching process, and the switching process performed by the two second power devices 102 is a forward switching process.

As shown in FIG. 8, two ends of the H-bridge inductor 200 included in the switch module 1 are connected to the neutral points of the two switching units 100 respectively to suppress the additional reverse switching loss generated by the two first power device 101 in the switch module during the reverse switching process.

The topological structure of the V-phase and W-phase control parts is the same as that of the U-phase control part in FIG. 8, and will not be described again here.

It should be noted that in the embodiment shown in FIG. 8, the control part of each phase includes n H-bridge type parallel multi-level inverter switch modules, where the minimum value of n can be 1, that is, one-phase inverter circuit can be controlled by only one of the above-mentioned H-bridge type parallel multi-level inverter switch modules.

In some preferred embodiments, the first power device 101 and the second power device 102 are both high-level turn-on silicon carbide based power devices, that is, high-level turn-on SiC MOSFETs. In other optional embodiments, the first power device 101 and the second power device 102 can also be other power switching devices with similar characteristics of channel+diode+parasitic output capacitor.

In some preferred embodiments, the first power device 101 and the second power device 102 can use devices with the same specifications. Selecting devices with the same specifications can effectively reduce product manufacturing costs and make it easier to determine the optimal inductance value of the H-bridge inductor 200.

[Suppression of Additional Reverse Switching Loss by H-Bridge Inductor]

The analysis model of the H-bridge type parallel multi-level inverter switch module can be established in a similar way to the analysis model of the previous double-pulse switching circuit to analyze its suppression mechanism of the additional reverse switching loss. In order to more clearly illustrate this analysis model, in FIG. 8, the first power device 101 of the switching unit on the left side of the switch module 1 can be marked as S_h1, the second power device 102 on the left side of the switch module 1 can be marked as S_l1, the first power device 102 of the switching unit on the right side of the switch module 1 can be marked as S_h2, and the second power device 102 on the right side can be marked as S_l2. In some embodiments, each power device includes a high-level turn-on channel and a Schottky diode, and has a parasitic output capacitor.

FIG. 9 shows the changes of the gate signals and the voltage and the current of S_h1, S_h2, S_l1, and S_l2in a complete switching cycle. FIG. 10A to FIG. 10H show the direction situation of the current flow of S_h1, S_h2, S_l1, and S_l2in each interval respectively. T_sand T_din the figure are the phase shift time and the dead time of each power device respectively. The switching losses of S_h1, S_h2, S_l1, and S_l2at each interval can be analyzed in combination with FIG. 9 and FIG. 10A to FIG. 10H.

Interval I (T₀˜T₁): as shown in FIG. 10Aa, at this time, S_h1of the left branch and S_l2of the right branch are turned on. Compared with the DC bus voltage, the voltage drop of S_h1and S_l2is negligible. Therefore, the voltage difference V₁₂at the neutral point of the switch is equal to the DC bus voltage V_dc, causing the inductor current i_Lof the H-bridge inductor to rise linearly.

Interval II (T₁˜T₂): as shown in FIG. 10B, only S_h1is turned on at this time, and the right branch is in the dead zone stage. Since the inductor current i_Lof the H-bridge inductor cannot change suddenly, i_Lreversely charges the parasitic output capacitor C_h2and charges the parasitic output capacitor C_l2at the same time. Under ideal circumstances, at the end of interval II, C_h2and C_i2can achieve complete charge and discharge, so that the voltage of S_h2decreases from V_dcto 0, and S_l2increases from 0 to V_dc, thus realizing the zero-voltage turn-on process of the right branch S_h2. At this time, the voltage across the H-bridge inductor drops from V_dcto 0, and i_Lwill increase.

Interval III (T₂˜T₃): as shown in FIG. 10C S_h1and S_h2are turned on at this time, and the flow of i_Lis sustained by the channel of S_h1. If the parasitic output capacitors C_h2and C_l2have been charged and discharged in interval II, i_Lwill not flow through the parasitic output capacitors. Therefore, in interval III, the voltage across the H-bridge inductor is the voltage drop between D_h2and S_h1, and i_Lwill drop slightly, which can be ignored.

Interval IV (T₃˜T₄): as shown in FIG. 10D, only S_h2is turned on at this time, and the left branch is in the dead zone stage. i_Lcharges C_h1and discharges C_l2. Under ideal circumstances, C_h1and C_l1can be completely charged and discharged, so that the voltage of S_h1increases from 0 to V_dcand the voltage of Su decreases from V_dcto 0, thereby realizing the zero-voltage turn-on process of the left branch Su. At this time, the voltage across the H-bridge inductor reversely increases from 0 to −V_dc, and i_Lwill decrease.

Interval V (T₄˜T₅): as shown in FIG. 10E, at this time, Su of the left branch and S_h2of the right branch are turned on, the bus voltage continues to reversely charge the H-bridge inductor, and i_Ldecreases to 0 and continues to increase in the opposite direction.

Interval VI (T₅˜T₆): as shown in FIG. 10F, at this time, only Su is turned on, and the right branch is in the dead zone stage. i_Lcharges C_h2and discharges C_l2. Under ideal circumstances, C_h2and C_l2can be completely charged and discharged, so that the voltage of S_h2increases from 0 to V_dcand the voltage of S_l2increases decreases from V_dcto 0, thereby realizing the zero-voltage turn-on process of the right branch S_l2. At this time, the voltage across the H-bridge inductor decreases from −V_dcto 0, and i_Lwill decrease.

Interval VII (T₆˜T₇): as shown in FIG. 10G, at this time, Su and S_l2are turned on, and the flow of i_Lis sustained by the channel of Su. If the output capacitors Chi and Cn have been charged and discharged in interval VI, i_Lwill not flow through the output capacitors. In interval VII, the voltage across the H-bridge inductor is the voltage drop between D_l2and S_l1, and i_Lwill drop slightly, which can be ignored.

Interval VIII (T₇˜T₈): as shown in FIG. 10H, only S_l2is turned on at this time, and the left branch is in the dead zone stage. i_Ldischarges C_h1and charges C_l1. Under ideal circumstances, C_h1and C_l1can be completely charged and discharged, so that the voltage of S_h1is reduced from V_dcto 0, and the voltage of Su increases from 0 to V_dc, thereby realizing the zero-voltage turn-on process of the left branch S_h1. At this time, the voltage across the H-bridge inductor increases from 0 to V_dc, and i_Lwill increase from negative current to positive current.

From the above analysis, it can be seen that by connecting the H-bridge resistor at the neutral point of the two parallel branches, each parasitic output capacitor can be charged and discharged symmetrically in each interval of a complete switching cycle. Under ideal circumstances, complete charging and discharging can be achieved. That is, zero-voltage switching (ZVS) of each power device is realized. Therefore, the additional reverse switching loss caused by the inability of the parasitic output capacitor in the power device to discharge in time under light load operating conditions can be effectively suppressed, and overall, the switching loss of parallel multi-level inverters is reduced.

[Parameter Optimization of H-Bridge Inductor]

It can be seen from the above analysis that the purpose of setting up the H-bridge inductor is to reduce the reverse switching loss of the power device under light load operating conditions by charging and discharging the parasitic output capacitor, so as to achieve the purpose of zero-voltage switching (ZVS). To achieve the above purpose, the inductance value of the H-bridge inductor should be optimized to ensure that the parasitic output capacitor of each power device can be fully charged and discharged during a complete switching cycle under light load operating conditions, thereby achieving the purpose of minimizing the reverse switching loss.

To this end, some embodiments of the present application also provide a method for optimizing the above-mentioned H-bridge type parallel multi-level inverter switch module. As shown in FIG. 11, the method for optimizing the above-mentioned H-bridge type parallel multi-level inverter switch module includes the following steps.

Step 1: obtaining the switching loss of the H-bridge type parallel multi-level inverter switching module in a complete switching cycle.

Step 2: optimizing the switching loss of the H-bridge type parallel multi-level inverter switch module in a complete switching cycle based on the zero-voltage switching strategy under light load operating conditions, and determining an optimum inductor value of the H-bridge inductor.

In some embodiments, the specific implementation of step 1 has been explained in the introduction of FIG. 9 and FIG. 10A to FIG. 10H. Through the above analysis, it can be found that the zero-voltage switching process of the switch module 1 under light load operating conditions is a process to charge and discharge the parasitic output capacitors of the two power devices of the left (or right) switching unit respectively through the H-bridge inductor in intervals II, IV, VI, and VIII, thereby reducing additional reverse switching loss. Therefore, in order to achieve an ideal loss reduction effect, it is necessary to match the inductance value of the H-bridge inductor with the parameters of the power devices to ensure that when the inverter circuit reaches a steady state under light load operating conditions, the H-bridge type parallel multi-level inverter switch module satisfies the following constraints.

The first constraint is that the inductor current at the beginning of a complete switching cycle is equal to the inductor current at the end of the switching cycle.

The second constraint is that the voltage at two ends of the H-bridge inductor changes symmetrically within a complete switching cycle;

The third constraint is that the reverse switching loss of the first power device of each switching unit is minimal within a complete switching cycle.

FIG. 12 shows the changes in the gate signal and the voltage and the current of the H-bridge type parallel multi-level inverter switching module in interval II. FIG. 13A to FIG. 13F respectively show the direction situation of the current flow of the switching module in stage I to stage VI of interval II. The specific process of H-bridge inductor optimization based on the above zero-voltage switching strategy in step 2 will be illustrated below in combination with the attached figures by taking interval II as an example.

Stage I (t<T₂₀): at this time, interval II has not yet started, the switch module is in the state in FIG. 13A, the voltage difference V₁₂across the H-bridge inductor is equal to the DC bus voltage V_dc, which makes the inductor current i_Lincrease linearly. The inductor current at time T₂₀can be solved by the following formula:

$\begin{matrix} i_{L T_{2 0}} = \frac{1}{2} \cdot \frac{V_{d c}}{L} \cdot T_{0} & (1) \end{matrix}$

$T_{0} = T_{s} - T_{d} .$

Stage II (T₂₀˜T₂₁): as shown in FIG. 13B, at this time, the gate drive voltage of S_l2changes from high to low, and the gate voltage V_gsl2drops from V_gsmaxto the Miller plateau voltage V_th+(i_A/g_fs). Similar to stage I, the inductor current i_Lin stage II still increases linearly. Therefore, the analysis of stage II is described as follows:

$\begin{matrix} i_{L T_{2 1}} = i_{L T_{2 0}} + \frac{V_{d c}}{L} \cdot (T_{2 1} - T_{2 0}) & (2) \end{matrix}$

$T_{2 1} - T_{2 0} = R_{g} C_{iss} \ln (\frac{V_{gsmax}}{V_{t h} + i_{A} / g_{fs}}),$

- Where R_gand C_issare the gate drive resistance and the input capacitance of the power device respectively.

Stage III (T₂₁˜T₂₂): as shown in FIG. 13C, at this time, the gate voltage V_gsl2of S_l2drops from V_th+ (i_A/g_fs) to the Miller plateau and then to the threshold voltage V_th. At this time, i_Lbegins to discharge the parasitic output capacitor C_h2and charge C_l2, causing the drain-source voltage V_dsh2of S_h2to decrease and the drain-source voltage V_dsl2of S_l2to increase. However, in this stage, i_Lmainly flows through the channel of S_l2, thus the caused voltage change can be ignored. Therefore, the description of stage III is as follows:

$\begin{matrix} i_{L T_{2 2}} = i_{L T_{2 1}} + \frac{V_{d c}}{L} \cdot (T_{2 2} - T_{2 1}) & (3) \end{matrix}$

$T_{2 2} - T_{2 1} = R_{g} C_{i s s} \ln (\frac{V_{t h} + i_{A} / g_{fs}}{V_{t h}}) .$

Stage IV (T₂₂˜T₂₃): as shown in FIG. 13D, at this time, the gate voltage V_gsl2of S_l2drops below the threshold voltage V_th, and the channel of S_l2is completely turned off. At this time, i_Lis completely used to discharge the parasitic output capacitor C_h2and charge C_l2, causing V_dsh2to drop quickly and V_dsl2to rise quickly.

Stage V (T₂₃˜T₂₄): as shown in FIG. 13E, the dead zone ends at T₂₃, the gate drive signal of S_h2changes from low to high, the gate voltage V_gsh2of S_h2starts to rise from 0. But in stage V, the gate voltage V_gsh2of S_h2is below the threshold voltage V_th, and the channel is not turned on. At this time, i_Lis still used to discharge the parasitic output capacitor C_h2and charge C_l2, causing V_dsh2to drop to 0 and V_dsl2to rise to V_dcat time T₂₄.

The analysis of Stage IV and Stage V is described below:

$\begin{matrix} i_{L T_{24}} = i_{L T_{22}} + \frac{U_{d c}}{L} \cdot (T_{24} - T_{22}) & (4) \end{matrix}$

T
24

-

T
23

=

R
g

⁢

C

i
⁢
s
⁢
s

⁢

ln
⁡
(

V
gs

V
gsmax

-

V
th

)

.