110 (described later) to output the drive signals ho, lo (described later) in so-called soft start and soft end.

The level shifter circuit (LS) 104 shifts the level of the voltage Vvw.

The comparator circuit (CMP) 105 compares the magnitude between the level-shifted voltage Vvw with threshold values Thvw_h and Thyw_l according to the voltage Vbo, to thereby output pulse signals LOvwth and HOvwth. Specifically, the comparator circuit 105 outputs the pulse signal HOvwth to turn off the NMOS transistor 24, in response to the level-shifted voltage Vvw dropping below the threshold value Thvw_h. Meanwhile, the comparator circuit 105 outputs the pulse signal LOvwth to turn off the NMOS transistor 25, in response to the level-shifted voltage Vvw exceeding the threshold value Thvw_l. Note that the pulse signals HOvwth, LOvwth correspond to a “comparison result”.

The level shifter circuit (LS) 106 shifts the level of the voltage Vis.

The comparator 107 detects the polarity of the resonant current Icr by comparing the level-shifted voltage Vis with the reference voltage Vref1, to thereby output a signal Szero. Note that the reference voltage Vref1 is equal to the voltage obtained by shifting the level of the voltage Vis at the time when the resonant current Icr reaches zero. Further, the comparator 107 detects the timing at which the resonant current Icr reaches zero, and the timing at which the logic level of the signal Szero changes is the same as the timing at which the resonant current Icr reaches zero. Note that the comparator 107 corresponds to a “detection circuit”, and the signal Szero corresponds to a “detection result”.

The analog-to-digital converter circuit (ADC) 108 converts the voltage Vca at the terminal CA into a digital value to be outputted. The voltage Vca converted into a digital value is used for the drive signal output circuit 110 (described later) to switch the mode between the “normal mode” and the “burst mode.

The load detection circuit 109 detects whether the load 11 is in a light load state or a heavy load state, based on the voltage that is applied to the terminal IS and that corresponds to the power consumption of the load 11 (in other words, the voltage Vis corresponding to the resonant current flowing through the resonant circuit). Here, the power consumption of the load 11 is larger when the load 11 is in the heavy load state than when the load 11 is in the light load state. Accordingly, the voltage Vis applied to the terminal IS indicates the voltage corresponding to the power consumption of the load 11, and thus when the voltage Vis is lower than a predetermined value, the load detection circuit 109 outputs the voltage Vca indicating that the load 11 is in the light load state.

Meanwhile, when the voltage Vis is higher than the predetermined value, the load detection circuit 109 outputs the voltage Vca indicating that the load 11 is in the heavy load state. Note that the heavier the state of the load 11 becomes, the higher the voltage Vca rises.

Note that the phrase “the load 11 is in the heavy load state” indicates the case in which the current value of the load current Iout flowing through the load 11 is equal to or larger than a predetermined value (e.g., 1 A), for example. Further, “the load 11 is in the light load” indicates the case in which the current value of the load current Iout flowing through the load 11 is smaller than the predetermined value (e.g., 1 A), for example. Furthermore, the phrase “the load 11 is in no load state” indicates the case in which the current value of the load current Iout flowing through the load 11 is extremely small or 0 (zero) A. Although it is described that the current value of the load current Iout to determine whether the load 11 is in the heavy load state or the light load state is 1 A, for example, however, this current value may be set to various values.

The drive signal output circuit 110 outputs the drive signals ho, lo, based on multiple signals, such as the signal Sfb, and digital values. Specifically, the drive signal output circuit 110 outputs the drive signals ho, lo to operate the switching power supply circuit 10 in the “burst mode”, when the load 11 is in the light load, as will be described later in detail. Meanwhile, the drive signal output circuit 110 outputs the drive signals ho, lo to operate the switching power supply circuit 10 in the “normal mode”, when the load 11 is in the heavy load state.

The driver circuit (DRV) 111 outputs the driving voltages Vdr1 and Vdr2 to drive the NMOS transistors 24, 25 in FIG. 1, respectively. Specifically, in response to the drive signal output circuit 110 outputting the high drive signal ho, the driver circuit 111 outputs the driving voltage Vdr1 to turn on the NMOS transistor 24. In response to the drive signal output circuit 110 outputting the low drive signal ho, the driver circuit 111 outputs the driving voltage Vdr1 to turn off the NMOS transistor 24. Further, in response to the drive signal output circuit 110 outputting the high drive signal lo, the driver circuit 111 outputs the driving voltage Vdr2 to turn on the NMOS transistor 25. In response to the drive signal output circuit 110 outputting the low drive signal lo, the driver circuit 111 outputs the driving voltage Vdr2 to turn off the NMOS transistor 25.

===State Transitions of Drive Signal Output Circuit 110===

FIG. 3 illustrates the state transitions of the drive signal output circuit 110. Note that FIG. 3 illustrates how the state of the drive signal output circuit 110 transitions, and thus how the drive signal output circuit 110 outputs the drive signals ho, lo in each state will be described later. Further, a “state 1” to a “state 4” indicate the states of the drive signal output circuit 110 when the switching power supply circuit 10 operates in the “burst mode”. First, it is assumed that the control IC 40 operates the switching power supply circuit 10 in the “normal mode”.

In the “normal mode,” when the load 11 enters the light load state; the voltage Vca drops below the threshold value Vca_l; and a predetermined period Ta has elapsed, the state of the drive signal output circuit 110 changes from the “normal mode” to the “state 1”, which is a state in the “burst mode” (process S10).

The “state 1” is a state in which the drive signal output circuit 110 outputs the drive signals ho, lo, based on the voltage Vvw (i.e., peak power control is performed), which will be described later in detail. Further, immediately after the operation of the switching power supply circuit 10 is shifted from the “normal mode” to the “burst mode”, the state of the drive signal output circuit 110 changes from the “state 1” to the “state 3” (described later) without going through the “state 2” (described later).

Meanwhile, when the switching power supply circuit 10 operates in the “burst mode” except immediately after the switching power supply circuit 10 starts operating in the “burst mode,” the state of the drive signal output circuit 110 repeatedly changes from the “state 3”, through the “state 4” (described later) and the “state 1”, to the “state 2.

As such, with the state transition path of from the “state 1” to the “state 4” being made different between the path immediately after the transition from the “normal mode” to the “state 1” and the path in cases other than that, the output voltage Vout can be restrained from reaching an overvoltage during a time period before the drive signal output circuit 110 enters the “state 3”.

Returning to FIG. 3, in the “state 1”, immediately after the transition from the “normal mode”, the load 11 enters the light load state, and in response to the output voltage Vout rising and the feedback voltage Vfb dropping below the reference voltage Vref0_l, the state of the drive signal output circuit 110 changes from the “state 1” to the “state 3” without going through the “state 2” (describe later) (process S20).

The “state 3” is a state in which the driving of the NMOS transistors 24, 25 in FIG. 1 is stopped. Then, in the “state 3”, the load 11 enters the heavy load state, and in response to the output voltage Vout dropping and the feedback voltage Vfb exceeding the reference voltage Vref0_h, which is higher than the reference voltage Vref0_l, the state of the drive signal output circuit 110 changes from the “state 3” to the “state 4” (process S21). In an embodiment of the present disclosure, in order to suppress the rise in the output voltage Vout, the state of the switching output circuit 110 changes from the “state 1” to the “state 3” immediately after the operation of the switching power supply circuit 10 is shifted to the “burst mode”, and a soft-end operation is not performed, which will be described later in detail.

The “state 4” is a state in which the drive signals ho, lo to gradually increase ON period of NMOS transistors 24, 25 are outputted (so-called soft-start operation is performed). Then, in response to the soft-start period being completed in the “state 4”, the state of the drive signal output circuit 110 changes from the “state 4” to the “state 1” (process S22).

The operation immediately after the transition from the “normal mode” to the “burst mode” has been described. Meanwhile, the switching power supply circuit 10 enters the “state 3” immediately after starting the operation in the “burst mode”, and thereafter the state of the drive signal output circuit 110 repeats from the “state 1” to the “state 4” in order to drive the NMOS transistors 24, 25 intermittently.

When the drive signal output circuit 110 is in the “state 1” in a time period except immediately after the transition to the “burst mode,” the state of the drive signal output circuit 110 changes from the “state 1” to the “state 2” in response to the output voltage Vout rising and the feedback voltage Vfb dropping below the reference voltage Vref0_l (process S23).

The “state 2” is a state in which the drive signals ho, lo to gradually reduce the ON period of NMOS transistors 24, 25 are outputted (so-called soft-end operation is performed). Then, in response to the soft end period being completed in the “state 2”, the drive signal output circuit 110 changes from the “state 2” to the “state 3” (process S24).

As such, when the switching power supply circuit 10 is continuously operated in the “burst mode,” the drive signal output circuit 110 repeats changes from the “state 3”, through the “state 4” and the “state 1,” to the “state 2. This suppresses the noise in the transformer 26 in FIG. 1 when the NMOS transistors 24, 25 of FIG. 1 are driven in the “burst mode”.

Further, in the “state 1”, in response to the load 11 entering the heavy load state and the voltage Vca exceeding the threshold value Vca_h, the state of the drive signal output circuit 110 changes from the “state 1” in the “burst mode” to the “normal mode” such that the switching power supply circuit 10 is operated in the “normal mode” (process S11). Note that the “state 1” corresponds to a “first state”, the “state 2” corresponds to a “second state”, the “state 3” corresponds to a “third state 3”, and the “state 4” corresponds to a “fourth state”.

===Output System of Drive Signals ho, lo in “Normal Mode”===

FIG. 4 is diagram illustrating a drive pattern in the “normal mode. When the switching power supply circuit 10 is operated in the “normal mode”, the drive signal output circuit 110 outputs the drive signals ho, lo to drive the NMOS transistors 24, 25 continuously, without intermittently stopping the switching operation, as illustrated in FIG. 4.

===Drive System in “Normal Mode”===

FIG. 5 is a diagram illustrating the drive system in the “normal mode”. When the switching power supply circuit 10 is operated in the “normal mode”, the drive signal output circuit 110 outputs the drive signals ho, lo by a drive system that is so-called phase ratio control. Note that “phase ratio control” refers to the drive system to control the switching of the NMOS transistors 24, 25, based on the direction (i.e., polarity) of the resonant current Icr and the feedback voltage Vfb.

The following describes a specific drive system of the phase ratio control with reference to FIG. 5. In FIG. 5, the drive signal output circuit 110 outputs a high drive signal ho after the dead time Td has elapsed since a low drive signal lo is outputted, as illustrated in FIG. 6. Similarly, the drive signal output circuit 110 outputs a high drive signal lo after the dead time Td has elapsed since a low drive signal ho is outputted, as illustrated in FIG. 6. Note that “the dead time” refers to the time period during which both the NMOS transistors 24, 25 are off so that through current does not flow between the node that receives the input voltage Vin and the node that receives the ground voltage with the NMOS transistors 24, 25 being turned on simultaneously.

At time to, the drive signal output circuit 110 outputs the low drive signal lo. Then, the drive signal output circuit 110 starts measuring a time period Tbh from time to. Further, the drive signal output circuit 110 obtains the feedback voltage Vfb at time to. Note that time to indicates the start of a half cycle.

At time t1, the resonant current Icr reaches zero, and the comparator 107 in FIG. 2 outputs the high signal Szero. In this event, the drive signal output circuit 110 finishes measuring the time period Tbh, and calculates the time period Tah until the end of the half cycle, based on the previously obtained the feedback voltage Vfb and the time period Tbh.

At time t2 at which the time period Tah has elapsed since time t1, the drive signal output circuit 110 outputs the low drive signal ho, as illustrated in FIG. 6. Then, the drive signal output circuit 110 starts measuring the time period Tbl from time t2, and also obtains the feedback voltage Vfb at time t2. Note that time t2 indicates the start of the half cycle.

At time t3, the resonant current Icr reaches zero, and the comparator 107 outputs the low signal Szero. In this event, the drive signal output circuit 110 finishes measuring the time period Tbl, and calculates a time period Tal until the end of the half cycle, based on the previously obtained feedback voltage Vfb and the time period Tbl.

At time t4, at which the time period Tal has elapsed since time t3, the drive signal output circuit 110 outputs the low drive signal lo, as illustrated in FIG. 6. From then, the same operations are repeated.

As has been described above, the drive signal output circuit 110 calculates the end time of the half cycle, for example, based on the time period Tbh measured from the time point at which the low drive signal lo is outputted and the feedback voltage Vfb at the time when the low drive signal lo is outputted. That is, the drive signal output circuit 110 controls, for example, the ratio between the time period Tbh and the time period Tah (i.e., the phase ratio) by the feedback voltage Vfb. By controlling in this manner using the feedback voltage Vfb and the time period Tbh changing depending on the state of the load 11, the drive signal output circuit 110 can maintain the output voltage Vout at the target level while following the changes in the state of the load 11. Note that the drive signals ho, lo outputted by the drive signal output circuit 110 in accordance with the phase ratio control correspond to a “first drive signal”.

===Output System of Drive Signals ho, lo in “Burst Mode”===

FIG. 7 is a diagram illustrating a drive pattern in the “burst mode”. When the switching power supply circuit 10 is operated in the “burst mode”, the drive signal output circuit 110 outputs the drive signals ho, lo to drive the NMOS transistors 24a and 25 intermittently (i.e., during the switching operation period) with a stop operation period being provided, as illustrated in FIG. 7. Further, the state of the drive signal output circuit 110 transitions in the order of the “state 4”, the “state 1”, and the “state 2” during the switching operation period, and is in the “state 3” during the stop operation period, during which the driving of the NMOS transistors 24, 25 is stopped. Note that the drive signals ho, lo outputted by the drive signal output circuit 110 in the “state 3” correspond to a “fourth drive signal”.

===Drive System in “State 4” in “Burst Mode”===

FIG. 8 is a diagram illustrating the drive system in the “state 4”. When the switching power supply circuit 10 is operated in the “burst mode”, the drive signal output circuit 110 outputs the drive signals ho and lo by the drive system that is so-called soft start, in response to the drive signal output circuit 110 entering the “state 4”. Note that the “soft start” refers to an operation of outputting the drive signals ho and lo with the ON periods that gradually increase according to the amount of change ΔONW every predetermined number of times N (e.g., N=2) as illustrated in an enlarged view in FIG. 8. The following describes the soft start operation with reference to FIG. 8.

At time t10, the drive signal output circuit 110 enters the “state 4”. Then, the drive signal output circuit 110 outputs the high drive signal lo.

At time t11, at which the predetermined ON period has elapsed since time t10, the drive signal output circuit 110 outputs the low drive signal lo. After time t11, the drive signal output circuit 110 outputs the drive signal lo with the ON period that gradually increases according to the amount of change ΔONW every predetermined number of times N. Further, the drive signal output circuit 110 outputs the drive signal ho and the drive signal lo alternately, the drive signal ho having the ON period equal to that of the drive signal lo.

From time t12, at which the drive signal output circuit 110 outputs the drive signal lo the predetermined number of times N from time t11, the drive signal output circuit 110 outputs the drive signal lo with the ON period increased by the amount of change ΔONW every predetermined number of times N.

The same or similar operations are repeated from time t12, thereby causing the drive signal output circuit 110 to output the drive signals ho and lo having the ON periods that gradually increase, in the soft start. Further, the predetermined number of times N is set so as to increase as the voltage Vbo rises, as given with the solid line in FIG. 9, and the amount of change ΔONW is set so as to decrease as the voltage Vbo rises, as given by the dashed line in FIG. 9. This causes the drive signal output circuit 110 to operate so as to increase the ON periods of the drive signals ho and lo little by little, as the voltage Vbo indicating the input voltage Vin rises, thereby reducing the effect of the input voltage Vin on the output voltage Vout. Note that the drive signals ho, lo outputted by the drive signal output circuit 110 in accordance with the soft start operation correspond to a “fifth drive signal”.

===Drive System in “State 1” in “Burst Mode”===

FIG. 10 is a diagram illustrating the drive system in the “state 1”. When the switching power supply circuit 10 is operated in the “burst mode”, the drive signal output circuit 110 outputs the drive signals ho, lo by a drive system that is so-called peak power control, in response to the drive signal output circuit 110 entering the “state 1”. Note that the “peak power control” refers to a drive system for controlling the switching of NMOS transistors 24, 25, based on a result of comparison between the voltage Vvw and the high/low threshold, and the dead time Td.

The following describes the specific drive system of peak power control with reference to FIG. 10. It is assumed that before time t20, the drive signal output circuit 110 outputs the low drive signal ho and the high drive signal lo.

At time t20, at which the voltage Vvw exceeds the threshold value Thvw_l, the comparator circuit 105 outputs a pulse signal LOvwth. As illustrated in FIG. 11, the drive signal output circuit 110 outputs the low drive signal lo, upon receipt of the pulse signal LOvwth.

At time t21, at which the dead time Td has elapsed since time t20, the drive signal output circuit 110 outputs the high drive signal ho, as illustrated in FIG. 11.

At time t22, at which the voltage Vvw drops below the threshold value Thvw_h, the comparator circuit 105 outputs the pulse signal HOvwth. As illustrated in FIG. 11, the drive signal output circuit 110 outputs the low drive signal ho, upon receipt of the pulse signal HOvwth.

At time t23, at which the dead time Td has elapsed since time t22, the drive signal output circuit 110 outputs the high drive signal lo, as illustrated in FIG. 11.

At time t24, at which the voltage Vvw exceeds the threshold value Thvw_l, the comparator circuit 105 outputs the pulse signal LOvwth. As illustrated in FIG. 11, the drive signal output circuit 110 outputs the low drive signal lo, upon receipt of the pulse signal LOvwth. From then, the same operations are repeated.

Further, the threshold value Thvw_h is set to so as to increase as the voltage Vbo rises, as given by the solid line in FIG. 12. Meanwhile, the threshold value Thvw_l is set so as to decrease as the voltage Vbo rises, as given by the dashed line in FIG. 12. Thus, when the voltage Vbo rises, the drive signal output circuit 110 reduces the ON periods of the drive signals ho and lo, thereby reducing the effect of the input voltage Vin on the output voltage Vout. Note that the pulse signal HOvwth, LOvwth corresponds to a “predetermined condition”. Further, the drive signals ho, lo, which is outputted by the drive signal output circuit 110 in accordance with the peak power control, correspond to a “second drive signal”.

===Drive System in “State 2” during “Burst Mode”===

FIG. 13 is a diagram illustrating the drive system in the “state 2”. When the switching power supply circuit 10 is operated in the “burst mode”, the drive signal output circuit 110 outputs the drive signals ho, lo by a drive system that is so-called soft end, in response to the drive signal output circuit 110 entering the “state 2”. Note that the “soft end” refers to an operation of outputting the drive signals ho and lo with the ON periods that gradually decrease according to the amount of change ΔONW every predetermined number of times N (e.g., N=2), as illustrated in an enlarged view in FIG. 13. The following describes the soft end operation with reference to FIG. 11.

At time t30, at which the drive signal output circuit 110 outputs the low drive signal ho, the drive signal output circuit 110 enters the “state 2”.

At time t31, at which the dead time Td has elapsed since time t30, the drive signal output circuit 110 outputs the high drive signal lo. Thereafter, the drive signal output circuit 110 outputs the drive signal lo with the ON periods that gradually decrease according to the amount of change ΔONW every predetermined number of times N (e.g., twice). Further, the drive signal output circuit 110 outputs the drive signal ho and the drive signal lo, alternately, the drive signal ho having the ON period equal to that of the drive signal lo.

Thus, in the soft end, the drive signal output circuit 110 outputs the drive signals ho and lo whose ON periods gradually decrease. Further, as in the case of the soft start, the predetermined number of times N is set so as to increase as the voltage Vbo rises, as given by the solid line in FIG. 9, and the amount of change ΔONW is set so as to decrease as the voltage Vbo rises, as given by the dashed line in FIG. 9. This causes the drive signal output circuit 110 to operate so as to gradually reduce the ON periods of the drive signals ho and lo as the voltage Vbo indicating the input voltage Vin rises, thereby reducing the effect of the input voltage Vin on the output voltage Vout. Note that the drive signals ho, lo outputted by the drive signal output circuit 110 in accordance with the soft end operation correspond to a “third drive signal”, and the state transition of the drive signal output circuit 110 in the “burst mode” corresponds to a “second pattern”.

===Operation Immediately after Transition from “Normal Mode” to “Burst Mode”===

FIG. 14 is a diagram illustrating an operation waveform immediately after shifting from the “normal mode” to the “burst mode”.

At time t40, at which the load 11 enters the light load state; the voltage Vca drops below the threshold value Vca_l; and the predetermined time period Ta has elapsed, the state of the drive signal output circuit 110 changes from the “normal mode” to the “state 1” in the “burst mode”.

At time t41 at which the output voltage Vout rises and the feedback voltage Vfb drops below the reference voltage Vref0_l, the hysteresis comparator 101 outputs the low signal Sfb. The drive signal output circuit 110 that receives the low signal Sfb enters the “state 3”. Thus, as a final process, the drive signal output circuit 110 outputs the drive signals ho and lo, having the predetermined ON periods, and then stops driving the NMOS transistors 24, 25. Note that the drive signals ho, lo outputted in the final process correspond to a “sixth drive signal”.

Accordingly, the drive signal output circuit 110 stops driving the NMOS transistors 24, 25 after the output voltage Vout rises to some extent and the feedback voltage Vfb drops below the reference voltage Vref0_l. As a result, the drive signal output circuit 110 does not perform the soft end, thereby being able to restrain the output voltage Vout from reaching an overvoltage. Note that the state transition of the drive signal output circuit 110 immediately after shifting from the “normal mode” to the “burst mode” corresponds to a “first pattern”.

===Drive Pattern in Switching Operation Period during “Burst Mode”===