Reference Voltage Generator 126:

The reference voltage generator 126 may be coupled to the voltage supply 114. The reference voltage generator 126 may be configured to generate the threshold signal TS based on a supply voltage VDD milli-Volts (mV) received from the voltage supply 114. The reference voltage generator 126 may be further configured to provide the threshold signal TS that may be indicative of the SEL, to the inverting terminal of the comparator 124. In an embodiment, when the plurality of wells 106a-106d are p-wells, the voltage level of the threshold signal TS is in a range of 250 mV-300 mV. Thus, when the voltage level of the input signal IN provided to the comparator 124 exceeds the voltage level of the threshold signal TS, the fault signal FL may be generated at the first state. Further, when the voltage level of the input signal IN is below the voltage level of the threshold signal TS, the fault signal FL may be generated at the second state.

Clock Generator 112:

The clock generator 112 may be coupled to the counter 122, the address register 118, and the fault collection and control management circuit 116. The clock generator 112 may be configured to generate the clock signal CLK and provide the clock signal CLK to the counter 122, the address register 118, and the fault collection and control management circuit 116. In an embodiment, a frequency of the clock signal CLK is approximately 10 Mega-Hertz (MHz).

Address Register 118:

The address register 118 may be coupled to the counter 122, the comparison circuit 110 (e.g., the output terminal of the comparator 124), and the fault collection and control management circuit 116. The address register 118 may be configured to receive the clock signal CLK and the select signal SS from the counter 122 as and when the select signal SS is generated by the counter 122. Upon receipt of the select signal SS, the address register 118 may overwrite a previous location indicated by the select signal SS at a previous clock pulse, that is stored in the counter 122. In an example, at the first clock pulse of the clock signal CLK, a first location “00” (e.g., the location of the first well 106a) is stored in the address register 118 whereas at a second clock pulse of the clock signal CLK, a second location “01” (e.g., the location of the second well 106b) is stored in the address register 118. The address register 118 may be further configured to receive the fault signal FL, and generate an address signal ADD when the fault signal FL is at the first state. The address signal ADD is indicative of the location of the well that is associated with the select signal SS based on the first state of the fault signal FL. In an example, when the select signal SS is indicative of the first well 106a and the fault signal FL is at the first state, the address signal ADD is indicative of the first location of the first well 106a. The address register 118 may be configured to provide the address signal ADD to the fault collection and control management circuit 116. When the fault signal FL is at the second state, the address register 118 may be further configured to disable the generation of the address signal ADD.

Fault Collection and Control Management Circuit 116:

The fault collection and control management circuit 116 may be coupled to the clock generator 112, the comparison circuit 110 (e.g., the output terminal of the comparator 124), and the address register 118. The fault collection and control management circuit 116 may include suitable circuitry configured to perform one or more operations. For example, the fault collection and control management circuit 116 may be configured to receive the fault signal FL from the comparator 124, the address signal ADD from the address register 118, and the clock signal CLK from the clock generator 112. The address signal ADD may be indicative of the location of one of the plurality of wells 106a-106d when the fault signal FL is at the first state. The fault collection and control management circuit 116 may be further configured to detect, based on the first state of the fault signal FL, the SEL in one of the plurality of wells 106a-106d. The fault collection and control management circuit 116 may be further configured to determine a set of actions based on the receipt of the address signal ADD and the fault signal FL at the first state. In an example, at the first clock pulse of the clock signal CLK, the address signal ADD indicates the first location of the first well 106a and the fault signal FL is at the first state. Thus, the fault collection and control management circuit 116 detects that SEL has occurred in the first well 106a and thereupon determines the set of actions. The set of actions is directed to ensuring safety of the IC 100 from damages due to the SEL. The set of actions may include at least one of resetting the IC 100, switching-off the IC 100, and disabling a system clock signal (not shown) provided to the IC 100.

In Operation:

The plurality of wells 106a-106d may be a plurality of p-wells that are configured to generate the plurality of input signals I1-I4 and provide the plurality of input signals I1-I4 to the scanning multiplexer 120. Thus, the plurality of p-wells may include a first p-well that corresponds to the first well 106a, a second p-well that corresponds to the second well 106b, a third p-well that corresponds to the third well 106c, and a fourth p-well that corresponds to the fourth well 106d. The scanning multiplexer 120 may be configured to receive the select signal SS from the counter 122 and periodically scan the plurality of wells 106a-106d and select the input signal IN of the plurality of input signals I1-I4 based on the select signal SS. For example, at start of a first scan cycle, the select signal SS may indicate the first location of the first well 106a. The first scan cycle is indicative of a total number of clock pulses to execute the scanning of each well of the plurality of wells 106a-106d. The scanning multiplexer 120 may thus select the first input signal I1 generated by the first well 106a. Subsequently, as described above, the select signal SS is updated periodically based on the clock signal CLK to indicate locations of the remaining wells (e.g., the second through fourth wells 106b-106d). Consequently, the scanning multiplexer 120 may select each of the second through fourth input signals I2-I4. Thus, the scanning multiplexer 120 scans each of the plurality of wells 106a-106d in the first scan cycle. Subsequent to completion of the first scan cycle, the counter 122 may be reset and a second scan cycle is initiated. The scanning of the plurality of wells 106a-106d in the second scan cycle is similar to the scanning in the first scan cycle. In a scenario, when the SEL is detected, the fault collection and control management circuit 116 may determine a corrective action causing the IC 100 to be either switched-OFF or reset. Thus, it will be understood by a person skilled in the art that the periodic scanning of the plurality of wells 106a-106d may be discontinued in such a scenario, and the scanning of the plurality of wells 106a-106d may resume after the IC 100 is switched ON. It may be further understood by a person skilled in the art that a time duration of a scan cycle (e.g., the first scan cycle and the second scan cycle) of the periodic scanning is based on the frequency of the clock signal CLK and the count of wells in the memory circuit 102. In an embodiment, the first scan cycle of the clock signal CLK includes four clock pulses as the plurality of wells 106a-106d include four wells.

The scanning multiplexer 120 may be configured to provide the first input signal I1 (selected based on the select signal SS indicating the first location) to the non-inverting terminal of the comparator 124. The comparator 124 may be configured to compare the first input signal I1 with the threshold signal TS to determine whether the voltage level or the current level of the first input signal I1 exceeds the voltage level or the current level of the threshold signal TS. In an embodiment, the plurality of wells 106a-106d are p-wells that operate at ground potential (e.g., 0 Volts) in absence of SEL. Upon the occurrence of the SEL, the voltage level of the plurality of wells 106a-106d may increase to a value in the range of 250 mV-300 mV. Thus, to detect the occurrence of SEL in the plurality of wells 106a-106d, the threshold signal TS generated by the reference voltage generator 126 may have the voltage level in the range of 250 mV-300 mV.

The comparator 124 may be configured to generate the fault signal FL at the first state when the voltage or the current level of the first input signal I1 exceeds the voltage or the current level of the threshold signal TS thereby indicating the occurrence of SEL in the first well 106a. The comparator 124 may be configured to provide the fault signal FL to the address register 118 and the fault collection and control management circuit 116. The address register 118 may be configured to generate the address signal ADD and provide the address signal ADD to the fault collection and control management circuit 116. The address signal ADD is indicative of the first location of the first well 106a to indicate the occurrence of the SEL in the first well 106a. Upon receipt of the address signal ADD, the fault collection and control management circuit 116 may determine the set of actions to ensure safety of the IC 100.

FIG. 1B illustrates a schematic block diagram of the IC 100 of FIG. 1A in accordance with another embodiment of the present disclosure. The plurality of wells 106a-106d of the IC 100 of FIG. 1B may be a plurality of n-wells. Thus, the plurality of n-wells may include a first n-well that corresponds to the first well 106a, a second n-well that corresponds to the second well 106b, a third n-well that corresponds to the third well 106c, and a fourth n-well that corresponds to the fourth well 106d.

Comparator 124:

The inverting terminal (−) of the comparator 124 may be coupled to the output terminal of the scanning multiplexer 120 and the non-inverting terminal (+) of the comparator 124 may be coupled to the reference voltage generator 126. The comparator 124 may be configured to receive the input signal IN of the plurality of input signals I1-I4 from the scanning multiplexer 120 and the threshold signal TS from the reference voltage generator 126. When the plurality of wells 106a-106d are n-wells, the voltage level of the at least one of the plurality of input signals I1-I4 is below the voltage level of the threshold signal TS or the current level of the at least one of the plurality of input signals I1-I4 is above the current level of the threshold signal TS upon the occurrence of the SEL. The functionalities of remaining components of FIG. 1B are similar to the corresponding components described in FIG. 1A.

In Operation:

The comparator 124 may be configured to receive the first input signal I1 as the input signal IN from the scanning multiplexer 120. The comparator 124 may be further configured to generate the fault signal FL at the first state when the voltage level of the first input signal I1 is below the voltage level of the threshold signal TS or the current level of the first input signal I1 is above the current level of the threshold signal TS indicating the occurrence of SEL in the first well 106a. Further, the comparator 124 may be further configured to generate the fault signal FL at the second state when the voltage level of the first input signal I1 is above the voltage level of the threshold signal TS or the current level of the first input signal I1 is below the current level of the threshold signal TS indicating the absence of SEL in the first well 106a. In an embodiment, the plurality of wells 106a-106d are n-wells that have a normal operating voltage equivalent to the supply voltage VDD mV. Upon the occurrence of SEL, the operating voltage of the plurality of wells 106a-106d is reduced by more than 300 mV from the normal operating voltage. Thus, to detect the occurrence of SEL in the plurality of wells 106a-106d, the threshold signal TS is equivalent to 300 mV or more below the supply voltage VDD mV (e.g., VDD mV-300 mV). The comparator 124 may be further configured to provide the fault signal FL to the address register 118 and the fault collection and control management circuit 116. The address register 118 may be configured to generate the address signal ADD and provide the address signal ADD to the fault collection and control management circuit 116 when the fault signal FL is at the first state. The address signal ADD is indicative of the first location. Upon receipt of the address signal ADD, the fault collection and control management circuit 116 may determine the set of actions to protect the IC 100.

FIG. 1C illustrates a schematic block diagram of the IC 100 of FIG. 1A in accordance with yet another embodiment of the present disclosure. In addition to the components depicted in FIG. 1A, FIG. 1C includes an inverter 128, a reference current generator 130, and an operational amplifier 132 in place of the comparator 124.

Operational Amplifier 132:

The operational amplifier 132 may include (i) an inverting terminal (−) and (ii) a non-inverting terminal (+). The operational amplifier 132 may be connected in a negative feedback loop configuration such that the inverting terminal of the operational amplifier 132 may be coupled to a first output terminal of the operational amplifier 132 and the non-inverting terminal of the operational amplifier 132 may be coupled to a ground terminal GND. The operational amplifier 132 may include a second output terminal that may be configured to replicate an output generated at the first output terminal of the operational amplifier 132.

Inverter 128:

An input terminal of the inverter 128 may be coupled to the second output terminal of the operational amplifier 132, and an output terminal of the inverter 128 may be coupled to the address register 118 and the fault collection and control management circuit 116. The inverter 128 may be configured to invert an output signal generated at the second output terminal of the operational amplifier 132. Although not shown, the inverter 128 receives supply voltages at supply terminals thereof for performing the corresponding inversion operation.

Reference Current Generator 130:

The reference current generator 130 may have a first end and a second end. The first end of the reference current generator 130 may be coupled to the second output terminal of the operational amplifier 132 and the input terminal of the inverter 128, and the second end of the reference current generator 130 may be coupled to the voltage supply 114. The reference current generator 130 may be configured to receive the supply voltage VDD mV from the voltage supply 114 and generate the threshold signal TS that is indicative of the SEL. In an embodiment, the plurality of wells 106a-106d are p-wells that operate at ground potential (e.g., 0 Volts) in absence of SEL and therefore have zero current level. Upon the occurrence of SEL, the current level of the plurality of wells 106a-106d may increase. Thus, to detect the occurrence of SEL in the plurality of wells 106a-106d, a current level of the threshold signal TS generated by the reference current generator 130 is in the range 10 micro-Amperes (μA)-50 μA.

In Operation:

The operational amplifier 132 may be connected in the negative feedback loop configuration. The operational amplifier 132 may be configured to equate a voltage level at the inverting terminal of the operational amplifier 132 to a voltage level at the non-inverting terminal of the operational amplifier 132 that is coupled to the ground terminal GND. Thus, the voltage level at the non-inverting terminal of the operational amplifier 132 is at 0 volts. The operational amplifier 132 may be configured to generate a first current signal C1 at the first output terminal of the operational amplifier 132 such that the first current signal C1 reduces the voltage level at the inverting terminal of the operational amplifier 132 to 0 volts. The second output terminal of the operational amplifier 132 may be configured to replicate the first current signal C1 generated at the first output terminal of the operational amplifier 132.

In absence of SEL, the current level of the threshold signal TS may exceed a current level of the first current signal C1 such that a voltage level at the input terminal of the inverter 128 may remain equivalent to the supply voltage VDD mV (e.g., asserted). In an embodiment, in the absence of SEL, the current level of the first current signal C1 is approximately equivalent to 0 μA. Therefore, the inverter 128 may be configured to generate the fault signal FL at the second state (e.g., de-asserted) indicating the absence of SEL. In an example, a threshold voltage level for an analog signal to be logically asserted may be 5 mV, therefore, when the voltage level at the input terminal of the inverter 128 is above 5 mV, the voltage level at the input terminal of the inverter 128 remains asserted.

When the voltage level at the inverting terminal of the operational amplifier 132 increases (e.g., exceeds 300 mV) due to the occurrence of the SEL, the current level of the first current signal C1 may exceed the current level of the threshold signal TS. Thus, the voltage level at the input terminal of the inverter 128 may become equivalent to 0 volts (e.g., de-asserted). Therefore, the inverter 128 may be configured to generate the fault signal FL that is at the first state (e.g., asserted) indicating the SEL. The inverter 128 may be configured to provide the fault signal FL to the address register 118 and the fault collection and control management circuit 116. In an example, when the voltage level at the input terminal of the inverter 128 is below 5 mV, the voltage level at the input terminal of the inverter 128 remains de-asserted.

The functionalities of remaining components of FIG. 1C are similar to the corresponding components described in FIG. 1A.

FIG. 1D illustrates a schematic block diagram of the IC 100 of FIG. 1A in accordance with yet another embodiment of the present disclosure. In addition to the components depicted in FIG. 1C, the IC 100 of FIG. 1D includes a buffer 134 in place of the inverter 128.

Operational Amplifier 132:

The operational amplifier 132 may be connected in the negative feedback loop configuration such that the inverting terminal (−) of the operational amplifier 132 may be coupled to the first output terminal of the operational amplifier 132 and the non-inverting terminal (+) of the operational amplifier 132 may be coupled to the voltage supply 114 and configured to receive the supply voltage VDD mV. The second output terminal of the operational amplifier 132 may be configured to replicate the output generated at the first output terminal of the operational amplifier 132.

Buffer 134:

An input terminal of the buffer 134 may be coupled to the second output terminal of the operational amplifier 132 and an output terminal of the buffer 134 may be coupled to the address register 118 and the fault collection and control management circuit 116. The buffer 134 may be configured to receive an input, such as the first current signal C1, and generate an asserted output signal, such as the fault signal FL, when the input has a non-zero value.

Reference Current Generator 130:

The first end of the reference current generator 130 may be coupled to the second output terminal of the operational amplifier 132 and the second end of the reference current generator 130 may be coupled to the ground terminal GND. The reference current generator 130 may be configured to generate the threshold signal TS that is indicative of the SEL. In an embodiment, the plurality of wells 106a-106d are n-wells that have the normal operating voltage equivalent to the supply voltage VDD mV and have normal current level approximately equivalent to 0 μA. Upon the occurrence of SEL, the current level of the plurality of wells 106a-106d may increase to a value in the range of 10 μA-50 μA. Thus, to detect the occurrence of SEL in the plurality of wells 106a-106d, a current level of the threshold signal TS generated by the reference current generator 130 is in the range of 10 μA-50 μA.

In Operation:

The operational amplifier 132 may be connected in the negative loop configuration. The operational amplifier 132 may be configured to generate the first current signal C1 to maintain the voltage level at the inverting terminal of the operational amplifier 132 equivalent to the supply voltage VDD mV (e.g., same as the voltage at the non-inverting terminal of the operational amplifier 132). Thus, when the voltage level at the inverting terminal of the operational amplifier 132 reduces due to a voltage level of the first input signal I1 provided by the scanning multiplexer 120, the first current signal C1 increases the voltage level at the inverting terminal to the supply voltage VDD mV. The second output terminal of the operational amplifier 132 may be configured to replicate the output at the first output terminal (e.g., the first current signal C1) and generate the first current signal C1. In absence of the SEL, the first current signal C1 may remain approximately equivalent to 0 μA and hence a voltage level at the input terminal of the buffer 134 may remain equivalent to the ground terminal GND. Therefore, the buffer 134 may generate the fault signal FL that is at the second state indicating absence of the SEL.

When the voltage level at the inverting terminal of the operational amplifier 132 decreases due to the occurrence of the SEL, the current level of the first current signal C1 may exceed the current level of the threshold signal TS generated by the reference current generator 130. This may cause the voltage level at the input terminal of the buffer 134 to increase to the supply voltage VDD mV. Therefore, the buffer 134 may generate the fault signal FL at the first state indicating the occurrence of the SEL. The buffer 134 may be configured to provide the fault signal FL to the address register 118 and the fault collection and control management circuit 116. In an example, when the voltage level at the input terminal of the buffer 134 is above 5 mV, the voltage level at the input terminal of the buffer 134 remains asserted.

The functionalities of remaining components of FIG. 1D are similar to the corresponding components described in FIG. 1C.

In various embodiments, the count of wells in the memory circuit 102 is depicted as four. However, it will be understood by a person skilled in the art that the count of wells may be more or less than 4. Similarly, the scanning multiplexer 120 is depicted to be a 4×1 multiplexer (e.g., having four input terminals based on the count of wells), however, it will be understood by a person skilled in the art that the scanning multiplexer 120 may have greater or less than four input terminals based on the count of wells.

Although FIGS. 1A, 1B, 1C, and 1D illustrate that all of the circuits are implemented on the IC 100, in other embodiments, some of the circuitry may be located external to the IC 100. For example, in some embodiments, the voltage supply 114 may be external to the IC 100. In some other embodiments, the clock generator 112 may be external to the IC 100.

Although FIGS. 1A, 1B, 1C, and 1D illustrate usage of the detection circuit 104 in conjunction with the memory circuit 102, it will be understood by a person skilled in the art that detection circuit 104 may be used to detect the SEL in other electronic circuits formed using different configurations of the p-channel and n-channel transistors. Further, it will be understood by a person skilled in the art that the plurality of wells 106a-106d may be located in various circuits of the IC 100 or within a single circuit of the IC 100.

FIG. 2A illustrates a schematic block diagram of the scanning multiplexer 120 of the IC 100 of FIGS. 1A and 1C in accordance with an embodiment of the present disclosure. The scanning multiplexer 120 may include a plurality of n-channel transistors 202a-202f. In an embodiment, the plurality of n-channel transistors 202a-202f may include a first n-channel transistor 202a, a second n-channel transistor 202b, a third n-channel transistor 202c, a fourth n-channel transistor 202d, a fifth n-channel transistor 202e, and a sixth n-channel transistor 202f.

Each of the plurality of n-channel transistors 202a-202f may include a first terminal, a second terminal, and a gate terminal. The first and second terminals of the plurality of n-channel transistors 202a-202f may be one of source or drain terminals. The first terminals of the first through fourth n-channel transistor 202a-202d may be coupled to the plurality of wells 106a-106d, and configured to receive the plurality of input signals I1-I4 that may be generated by the plurality of wells 106a-106d, respectively. In an embodiment, the plurality of wells 106a-106d are p-wells.

The first terminal of the first n-channel transistor 202a may be coupled to the first well 106a and may be configured to receive the first input signal IT. The gate terminal of the first n-channel transistor 202a may be coupled to the counter 122 and may be configured to receive an inverted version of a first address bit S0 (e.g., S0′) of a set of address bits associated with the select signal SS. Further, the first terminal of the second n-channel transistor 202b may be coupled to the second well 106b and may be configured to receive the second input signal I2 of the plurality of input signals I1-I4. The gate terminal of the second n-channel transistor 202b may be coupled to the counter 122 and configured to receive the first address bit S0. The first terminal of the third n-channel transistor 202c may be coupled to the third well 106c and configured to receive the third input signal I3 of the plurality of input signals I1-I4. The gate terminal of the third n-channel transistor 202c may be coupled to the counter 122 and configured to receive the inverted version of the first address bit S0 (e.g., S0′). The first terminal of the fourth n-channel transistor 202d may be coupled to the fourth well 106d and may be configured to receive the fourth input signal I4 of the plurality of input signals I1-I4. The gate terminal of the fourth n-channel transistor 202d may be coupled to the counter 122 and configured to receive the first address bit S0.

The first terminal of the fifth n-channel transistor 202e may be coupled to the second terminal of the first n-channel transistor 202a and the second terminal of the second n-channel transistor 202b. The gate terminal of the fifth n-channel transistor 202e may be coupled to the counter 122 and configured to receive an inverted version of a second address bit S1 (e.g., S1′) of the set of address bits associated with the select signal SS. The first terminal of the sixth n-channel transistor 202f may be coupled to the second terminal of the third n-channel transistor 202c and the second terminal of the fourth n-channel transistor 202d. The gate terminal of the sixth n-channel transistor 202f may be coupled to the counter 122 and configured to receive the second address bit S1. The second terminal of the sixth n-channel transistor 202f may be coupled to the second terminal of the fifth n-channel transistor 202e to output at least one of a group consisting of the first input signal I1, the second input signal I2, the third input signal I3, and the fourth input signal I4, as the input signal IN.

In Operation:

The address bits S0 and S1 of the select signal SS provided to the plurality of n-channel transistors 202a-202f may control a conductive state of the plurality of n-channel transistors 202a-202f. When an address bit provided to the gate terminal of each of the plurality of n-channel transistors 202a-202f is asserted, the plurality of n-channel transistors 202a-202f may switch ON. In an example, when the first address bit S0 is ‘0’ and the second address bit S1 is ‘0’, the inverted first address bit S0′ is ‘1’ and the inverted second address bit S1′ is ‘1’. Thus, the first n-channel transistor 202a and the third n-channel transistor 202c are switched ON.

When the address bit provided to the gate terminal of each of the plurality of n-channel transistors 202a-202f is de-asserted, the plurality of n-channel transistors 202a-202f may switch OFF. Thus, the second n-channel transistor 202b and the fourth n-channel transistor 202d are switched OFF due to the first address bit S0 being ‘0’. Furthermore, the fifth n-channel transistor 202e is switched ON and the sixth n-channel transistor 202f is switched OFF due to the inverted second address bit S1′ being ‘1’ and the second address bit S1 being ‘0’. Thus, the address bit combination of S0=0 and S1=0 enables selection of the first input signal I1 as the input signal IN that is provided to the comparison circuit 110. Similarly, other combinations of the address bits S0 and S1 may enable selection of the remaining second through fourth input signals I2-I4. Therefore, based on the assertion of different address bits of the select signal SS, each of the plurality of n-channel transistors 202a-202f either switch ON or switch OFF, thereby enabling the scanning multiplexer 120 to select one of the plurality of input signals I1-I4.

FIG. 2B illustrates a schematic block diagram of the scanning multiplexer 120 of the IC 100 of FIGS. 1B and 1D in accordance with another embodiment of the present disclosure. The scanning multiplexer 120 includes a plurality of p-channel transistors 204a-204f. In an embodiment, the plurality of p-channel transistors 204a-204f may include a first p-channel transistor 204a, a second p-channel transistor 204b, a third p-channel transistor 204c, a fourth p-channel transistor 204d, a fifth p-channel transistor 204e, and a sixth p-channel transistor 204f.

Each of the plurality of p-channel transistors 204a-204f may include a first terminal, a second terminal, and a gate terminal. The first and second terminals of the plurality of p-channel transistors 204a-204f may be one of source or drain terminals. The first terminals of the first through fourth p-channel transistors 204a-204d may be coupled to the plurality of wells 106a-106d, and configured to receive the plurality of input signals I1-I4 that may be generated by the plurality of wells 106a-106d, respectively. In an embodiment, the plurality of wells 106a-106d are n-wells.

The first terminal of the first p-channel transistor 204a may be coupled to the first well 106a and may be configured to receive the first input signal I1. The gate terminal of the first p-channel transistor 204a may be coupled to the counter 122 and may be configured to receive the inverted version of the first address bit S0 (e.g., S0′) of the set of address bits associated with the select signal SS. Further, the first terminal of the second p-channel transistor 204b may be coupled to the second well 106b and may be configured to receive the second input signal I2 of the plurality of input signals I1-I4. The gate terminal of the second p-channel transistor 204b may be coupled to the counter 122 and configured to receive the first address bit S0. The first terminal of the third p-channel transistor 204c may be coupled to the third well 106c and configured to receive the third input signal I3 of the plurality of input signals I1-I4. The gate terminal of the third p-channel transistor 204c may be coupled to the counter 122 and configured to receive the inverted version of the first address bit S0 (e.g., S0′). The first terminal of the fourth p-channel transistor 204d may be coupled to the fourth well 106d and may be configured to receive the fourth input signal I4 of the plurality of input signals I1-I4. The gate terminal of the fourth p-channel transistor 204d may be coupled to the counter 122 and configured to receive the first address bit S0.

The first terminal of the fifth p-channel transistor 204e may be coupled to the second terminal of the first p-channel transistor 204a and the second terminal of the second p-channel transistor 204b. The gate terminal of the fifth p-channel transistor 204e may be coupled to the counter 122 and configured to receive the inverted version of the second address bit S1 (e.g., S1′) of the set of address bits associated with the select signal SS. The first terminal of the sixth p-channel transistor 204f may be coupled to the second terminal of the third p-channel transistor 204c and the second terminal of the fourth p-channel transistor 204d. The gate terminal of the sixth p-channel transistor 204f may be coupled to the counter 122 and configured to receive the second address bit S1. The second terminal of the sixth p-channel transistor 204f may be coupled to the second terminal of the fifth p-channel transistor 204e to output at least one of the group consisting of the first input signal I1, the second input signal I2, the third input signal I3, and the fourth input signal I4 as the input signal IN.

In Operation:

The address bits S0 and S1 of the select signal SS provided to the plurality of p-channel transistors 204a-204f may control a conductive state of the plurality of p-channel transistors 204a-204f. When an address bit provided to the gate terminal of each of the plurality of p-channel transistors 204a-204f is asserted, the plurality of p-channel transistors 204a-204f may switch OFF. In an example, the first address bit S0 is ‘0’, the second address bit S1 is ‘0’, the inverted first address bit S0′ is ‘1’, and the inverted second address bit S1′ is ‘1’. Thus, the first p-channel transistor 204a and the third p-channel transistor 204c are switched OFF.

When the address bit provided to the gate terminal of each of the plurality of p-channel transistors 204a-204f is de-asserted, the plurality of p-channel transistors 204a-204f may switch ON. Thus, the second n-channel transistor 202b and the fourth n-channel transistor 202d are switched ON due to the first address bit S0 being ‘0’. Furthermore, the fifth p-channel transistor 204e is switched OFF and the sixth p-channel transistor 204f is switched ON due to the inverted second address bit S1 being ‘1’ and the second address bit S1 being ‘0’. Thus, the address bit combination of S0=0 and S1=0 enables selection of the fourth input signal I4 as the input signal IN. Similarly, other combinations of the address bits S0 and S1 may enable selection of the remaining first through third input signals I1-I3. Therefore, based on the assertion of different address bits of the select signal SS, various p-channel transistors of the plurality of p-channel transistors 204a-204f either switch ON or switch OFF, thereby enabling the scanning multiplexer 120 to select one of the input signals I1-I4.

FIG. 3A illustrates a schematic block diagram of the reference voltage generator 126 of the IC 100 of FIGS. 1A and 1B in accordance with an embodiment of the present disclosure. The reference voltage generator 126 may include a first resistor 302a and a second resistor 302b. Each of the first resistor 302a and the second resistor 302b may have a first terminal and a second terminal.

The first terminal of the first resistor 302a may be coupled to the ground terminal GND. The first terminal of the second resistor 302b may be coupled to the second terminal of the first resistor 302a and the second terminal of the second resistor 302b may be configured to receive the supply voltage VDD mV. The threshold signal TS may be generated at a junction of the second terminal of the first resistor 302a and the first terminal of the second resistor 302b. The threshold signal TS may have different voltage levels based on the occurrence of SEL in a p-well or an n-well of the plurality of wells 106a-106d. In an embodiment, when the plurality of wells 106a-106d are p-wells, the voltage level of the threshold signal TS is in the range 250 mV-300 mV. In another embodiment, when the plurality of wells 106a-106d are n-wells, the voltage level of the threshold signal TS is 300 mV below the supply voltage VDD mV (e.g., VDD mV-300 mV). The values of the first resistor 302a and the second resistor 302b are selected such that a desired voltage level of the threshold signal TS may be achieved.

FIG. 3B illustrates a schematic block diagram of the reference voltage generator 126 of the IC 100 of FIG. 1A in accordance with another embodiment of the present disclosure. The reference voltage generator 126 may include a third resistor 302c and a first current generator 304a. The third resistor 302c may have a first terminal and a second terminal. Further, the first current generator 304a may have a first end and a second end.

The first end of the first current generator 304a may be configured to receive the supply voltage VDD mV and generate a second current signal C2. The first terminal of the third resistor 302c may be coupled to the second end of the first current generator 304a and the second terminal of the third resistor 302c may be coupled to the ground terminal GND. The threshold signal TS may be generated at a junction of the first terminal of the third resistor 302c and the second end of the first current generator 304a. The threshold signal TS may have a voltage level to detect occurrence of SEL in a p-well of the plurality of wells 106a-106d. The values of the second current signal C2 and the third resistor 302c are selected such that a desired voltage level of the threshold signal TS may be achieved.

FIG. 3C illustrates a schematic block diagram of the reference voltage generator 126 of the IC 100 of FIG. 1B in accordance with another embodiment of the present disclosure. The reference voltage generator 126 may include a fourth resistor 302d and a second current generator 304b. The fourth resistor 302d may have a first terminal and a second terminal. Further, the second current generator 304b may have a first end and a second end.

The first end of the second current generator 304b may be coupled to the ground terminal GND and configured to generate a third current signal C3. The first terminal of the fourth resistor 302d may be coupled to the second end of the second current generator 304b and the second terminal of the fourth resistor 302d may be configured to receive the supply voltage VDD mV. The threshold signal TS may be generated at a junction of the first terminal of the fourth resistor 302d and the second end of the second current generator 304b. The threshold signal TS may have a voltage level to detect the occurrence of SEL in an n-well of the plurality of wells 106a-106d. The values of the third current signal C3 and the fourth resistor 302d are selected such that a desired voltage level of the threshold signal TS may be achieved.

FIG. 4A illustrates a schematic block diagram of the memory circuit 102 and the detection circuit 104 of the IC 100 of FIGS. 1A, 1B, 1C, and 1D in accordance with an embodiment of the present disclosure. The memory circuit 102 may further include a plurality of isolated tap connections 402a-402d and a plurality of well-ties 404a-404d. The plurality of isolated tap connections 402a-402d may include a first isolated tap connection 402a, a second isolated tap connection 402b, a third isolated tap connection 402c, and a fourth isolated tap connection 402d. The plurality of well-ties 404a-404d may include a first well-tie 404a, a second well-tie 404b, a third well-tie 404c, and a fourth well-tie 404d.

The plurality of isolated tap connections 402a-402d may be coupled to the plurality of wells 106a-106d by way of the plurality of well-ties 404a-404d. In an example, the first isolated tap connection 402a may be coupled to the first well 106a by way of the first well-tie 404a. The plurality of isolated tap connections 402a-402d serve as carriers of the plurality of input signals I1-I4 and enable transmission of the plurality of input signals I1-I4 to the detection circuit 104. Since each well of the plurality of wells 106a-106d is separately tapped by way of a corresponding isolated tap connection of the plurality of isolated tap connections 402a-402d, specific addresses are utilized to scan each well of the plurality of wells 106a-106d.

FIG. 4B illustrates a schematic block diagram of the memory circuit 102 and the detection circuit 104 of FIG. 4A in accordance with another embodiment of the present disclosure. The memory circuit 102 may further include a first shared tap connection 406a and a second shared tap connection 406b in place of the plurality of isolated tap connections 402a-402d.

The first shared tap connection 406a and the second shared tap connection 406b may be coupled to the plurality of wells 106a-106d by way of the plurality of well-ties 404a-404d. In an example, the first shared tap connection 406a may be coupled to the first well 106a by way of the first well-tie 404a. The first shared tap connection 406a serves as a shared carrier of the first input signal I1 and the second input signal I2 and enables transmission of the first input signal I1 and the second input signal I2 to the detection circuit 104. The second shared tap connection 406b serves as a shared carrier of the third input signal I3 and the fourth input signal I4 and enables transmission of the third input signal I3 and the fourth input signal I4 to the detection circuit 104. Since, the first well 106a and the second well 106b share the first shared tap connection 406a, the first well 106a and the second well 106b may share an address during scanning of the first well 106a and the second well 106b. Similarly, the third well 106c and the fourth well 106d share the second shared tap connection 406b, the third well 106c and the fourth well 106d may share an address during scanning of the third well 106c and the fourth well 106d. Thus, when the select signal SS indicates an address corresponding to the first well 106a and the second well 106b, a combination of the first input signal I1 and the second input signal I2 are selected as the input signal IN. Similarly, when the select signal SS indicates an address corresponding to the first well 106a and the second well 106b, a combination of the first input signal I3 and the second input signal I4 are selected as the input signal IN.

FIG. 5 represents a flowchart that illustrates a method (e.g., a latch-up detection method) for detecting SEL in the IC 100 of FIGS. 1A, 1B, 1C, and 1D in accordance with an embodiment of the present disclosure.

At step 502, the plurality of wells 106a-106d of the memory circuit 102 may generate the plurality of input signals I1-I4. The plurality of input signals I1-I4 may be generated due to the occurrence of SEL in the plurality of wells 106a-106d, respectively. In an embodiment, the plurality of wells 106a-106d are p-wells. In another embodiment, the plurality of wells 106a-106d are n-wells. Steps 504-516 are executed by the detection circuit 104.

At step 504, the scanning multiplexer 120 may periodically scan the plurality of wells 106a-106d based on the select signal SS that may be generated by the counter 122 based on the clock signal CLK. The select signal SS may be indicative of the first location of the first well 106a of the plurality of wells 106a-106d and with each clock pulse of the clock signal CLK, the select signal SS may be updated to indicate locations of the second through fourth wells 106b-106d. In an embodiment, the select signal SS is a sequence of 2 address bits indicative of the locations of the plurality of wells 106a-106d. Subsequent to the select signal SS indicating the location of the fourth well 106d, the counter 122 may be reset to begin generating the select signal SS indicative of the first location of the first well 106a and continuing thereafter with locations of the remaining second through fourth wells 106b-106d.

At step 506, the scanning multiplexer 120 may select the first input signal I1 when the select signal SS indicates the first location of the first well 106a, and provide the first input signal I1 to the comparator 124. At step 508, the comparator 124 may compare the first input signal I1 with the threshold signal TS to determine whether a level of the first input signal I1 exceeds a level of the threshold signal TS (e.g., when the plurality of wells 106a-106d are p-wells) or whether the level of the first input signal I1 remains below the level of the threshold signal TS (e.g., when the plurality of wells 106a-106d are n-wells). The threshold signal TS is indicative of the SEL. When the plurality of wells 106a-106d are p-wells and if it is determined that the level of the first input signal I1 exceeds the level of the threshold signal TS, step 510 is performed. When the plurality of wells 106a-106d are p-wells and if it is determined that the level of the first input signal I1 remains below the level of the threshold signal TS, step 504 is repeated. Additionally, the fault signal FL may be generated at the second state. When the plurality of wells 106a-106d are n-wells and if it is determined that the level of the first input signal I1 remains below the level of the threshold signal TS, step 510 is performed. When the plurality of wells 106a-106d are n-wells and if it is determined that the level of the first input signal I1 is above the level of the threshold signal TS, step 504 is repeated. In another embodiment, the fault signal FL may be generated at the second state.

At step 510, the comparator 124 may generate the fault signal FL at the first state to indicate the occurrence of SEL. The fault signal FL at the first state may be provided to the address register 118 and the fault collection and control management circuit 116. At step 512, the address register 118 may detect the occurrence of SEL in the first well 106a based on receipt of the asserted fault signal FL (e.g., on receiving the fault signal FL at the first state). The occurrence of SEL in the first well 106a may be indicative of a fault in the memory circuit 102. At step 514, the address register 118 may generate the address signal ADD based on the select signal SS, the clock signal CLK, and the asserted fault signal FL. The address ADD is indicative of the first location where the occurrence of SEL is detected. The address signal ADD may be provided to the fault collection and control management circuit 116. At step 516, the fault collection and control management circuit 116 may determine the set of actions based on the receipt of the address signal ADD and the fault signal FL at the first state indicating the SEL in the first well 106a. The set of actions are intended to protect the IC 100 from any damage or attack due to the SEL which may lead to malfunction of the device in which the IC 100 is implemented.

Thus, in the present disclosure, the detection circuit 104 is able to detect the occurrence of SEL in the memory circuit 102 and generate the fault signal FL at the first state indicating the occurrence of SEL (e.g., the fault in the memory circuit 102). The detection of the SEL is performed by sensing the voltage or current associated with the plurality of input signals I1-I4 that are generated by the plurality of wells 106a-106d of the memory circuit 102. The sensed voltage or current is compared with the level of the threshold signal TS to determine the occurrence of SEL. Thus, SEL is detected based on sensing of a voltage or a current as compared to multiple signature vector components utilized by the conventional circuits, thereby reducing the usage of electronic components on the IC 100 and in turn reducing an area and power overhead of the IC 100 as compared to conventional circuits.

The detection circuit 104 identifies the location of the SEL in the memory circuit 102 thereby enabling the fault collection and control management circuit 116 to determine one or more actions associated with the location of the SEL in the memory circuit 102. In an example, the fault collection and control management circuit 116 may flag data originating from the location of the SEL and other locations of the IC 100 that are in the vicinity of the location of the SEL as the flipping of bits may occur in such locations due to the vicinity. In another example, the fault collection and control management circuit 116 may switch off or reset an area of the memory circuit 102 that is associated with the location of SEL to protect the IC 100 from malfunctioning and thereby improving security and robustness of the IC. Further, the threshold signal TS is set to the current or voltage level at which SEL occurs. When the level of the input signal IN exceeds or remains below the level of the threshold signal TS based on the type of the plurality of wells 106a-106d being p-wells or n-wells, the fault signal FL is generated at the first state to indicate that the SEL has occurred. Thus, the IC 100 is able to accurately detect the root cause of the flipping of bits that may be due to the SEL. Further, since the IC 100 is capable of detecting the SEL, the IC 100 may be utilized to avoid security hacks by the use of laser on at least one of critical memory circuits, flip-flops, Intellectual Property (IP) in secured IP-crypto cores, and hardware security engine. In addition, timely detection of the SEL may reduce a defect rate of the memory circuit 102 and improve the safety of the IC 100. Further, the detection circuit 104 may be placed at different locations in the IC 100 to sense a voltage difference due to the SEL and simultaneously detect the location of the SEL.

In an embodiment, an integrated circuit (IC) may comprise a plurality of wells of a memory circuit configured to generate a plurality of input signals, wherein a first well of the plurality of wells may be configured to generate a first input signal of the plurality of input signals. The IC may further comprise a detection circuit that may be coupled to the plurality of wells, wherein the detection circuit may be configured to periodically scan, based on a select signal, the plurality of wells. The select signal may be indicative of a location of each well of the plurality of wells. The detection circuit may be further configured to select the first input signal when the select signal indicates a first location of the first well, and compare, the first input signal with a threshold signal to generate a fault signal, wherein the threshold signal is indicative of a Single Event Latch-up (SEL). The detection circuit may be further configured to detect, based on a first state of the fault signal, the SEL in the first well indicative of a fault in the memory circuit.

In some embodiments, the detection circuit may comprise a selection circuit, wherein the selection circuit may comprise a counter that may be configured to receive a clock signal and generate the select signal based on the clock signal. The periodic scanning may be based on a frequency of the clock signal and a count of wells in the plurality of wells. A scanning multiplexer of the detection circuit may be coupled to the counter and the plurality of wells, wherein the scanning multiplexer may be configured to, periodically scan, based on the select signal, the plurality of wells, and select the first input signal when the select signal indicates the first location.

In some embodiments, the select signal may comprise a set of address bits, wherein when the set of address bits may be indicative of the first location, the first input signal may be selected.

In some embodiments, the plurality of wells may comprise a plurality of p-wells, wherein the plurality of p-wells may comprise a first p-well, a second p-well, a third p-well, and a fourth p-well. The first p-well corresponds to the first well. The scanning multiplexer may comprise a plurality of n-channel transistors that may be coupled to the plurality of p-wells, wherein the plurality of n-channel transistors comprise a first n-channel transistor, a second n-channel transistor, a third n-channel transistor, a fourth n-channel transistor, a fifth n-channel transistor, and a sixth n-channel transistor. Each of the plurality of n-channel transistors comprises a first terminal, a gate terminal, and a second terminal. The first terminal of the first n-channel transistor may be coupled to the first p-well and configured to receive the first input signal, and the gate terminal of the first n-channel transistor may be coupled to the counter and configured to receive an inverted version of a first address bit of the set of address bits. The first terminal of the second n-channel transistor may be coupled to the second p-well and configured to receive a second input signal of the plurality of input signals, and the gate terminal of the second n-channel transistor may be coupled to the counter and configured to receive the first address bit of the set of address bits. The first terminal of the third n-channel transistor may be coupled to the third p-well and configured to receive a third input signal of the plurality of input signals, and the gate terminal of the third n-channel transistor may be coupled to the counter and configured to receive the inverted version of the first address bit. The first terminal of the fourth n-channel transistor may be coupled to the fourth p-well and configured to receive a fourth input signal of the plurality of input signals, and the gate terminal of the fourth n-channel transistor may be coupled to the counter and configured to receive the first address bit. The first terminal of the fifth n-channel transistor may be coupled to the second terminal of the first n-channel transistor and the second terminal of the second n-channel transistor, and the gate terminal of the fifth n-channel transistor may be coupled to the counter and configured to receive an inverted version of a second address bit of the set of address bits. The first terminal of the sixth n-channel transistor may be coupled to the second terminal of the third n-channel transistor and the second terminal of the fourth n-channel transistor, the gate terminal of the sixth n-channel transistor may be coupled to the counter and configured to receive the second address bit, and the second terminal of the sixth n-channel transistor may be coupled to the second terminal of the fifth n-channel transistor to output at least one of a group consisting of the first input signal, the second input signal, the third input signal, and the fourth input signal.