23. The CPU 23 is also connected to a memory 29 including a nonvolatile memory (for example, a ROM) and a volatile memory (for example, a RAM). The memory 29 of Embodiment 2 stores a table of correlations between write voltages and write bits.

Write Voltage Determination Flow

FIG. 7 is a flowchart illustrating write voltage determination according to Embodiment 2. In step S301, a write voltage test is started. Next, in step S302, the selector circuit 27 is switched such that the antifuse 10 for 10 V test in the write voltage storage area 30 is selected. Next, in step S303, the write voltage is set to 10 V. Next, in step S304, the state of the antifuse 10 is read. Next, in step S305, the read state of the antifuse 10 is checked (whether or not writing has been performed).

If it is determined by the check in step S305 that the read value is at a level that is assumed to represent the state after writing, the processing proceeds to step S306. In step S306, it is determined that there is an initial failure, and error handling is performed. If the state of the antifuse 10 read in step S305 is at a level that is assumed to represent the state before writing, the processing proceeds to step S307. In step S307, predetermined pulses are applied at 10 V. Next, in step S308, the state of the antifuse 10 is read again. Next, in step S309, it is checked whether or not there is a change in the read state of the antifuse 10.

If it is determined by the check in step S309 that there is no change in the state (no writing has been performed), the processing proceeds to step S310. In step S310, it is determined whether or not the current set value of the write voltage is smaller than a certain voltage (in this case, 40 V). If the current set value is smaller than the predetermined voltage (S310=Yes), the processing proceeds to step S311, and the antifuse 10 in the applied voltage test area 31 is changed. Next, the processing proceeds to step S312, and the write voltage is increased (in this case, +5 V). Thereafter, the flow from step S304 to step S309 is repeated.

The above process is repeated until the write voltage reaches the predetermined value (in this case, 40 V). If the state of the antifuse 10 does not change even when the write voltage becomes equal to or more than the predetermined value (S310=No), the processing proceeds to step S306, and in step S306, it is determined that there is an initial failure, and error handling is performed.

If it is determined that there is a change in the state of the antifuse 10 (the write operation has been completed normally) as a result of applying the write voltage, which is increased by 5 V at each application (S309=Yes), the processing proceeds to step S313. In step S313, the selector circuit 27 is switched to the write voltage storage area 30. Next, in step S314, the voltage at which the change in the state of the antifuse 10 has occurred is written. Next, in step S315, the processing ends.

The write/read operations according to Embodiment 2, which are performed in accordance with the applied voltage determined in this way, will be described. As described with reference to FIG. 6, the nonvolatile OTP memory 11 includes the write voltage storage area 30 for storing the write voltage, which is one of the write conditions, the applied voltage test area 31, and the write area 22, and is connected to the write circuit 13 and the read circuit 14 via the input A illustrated in FIG. 1. The write circuit 13 is connected to the CPU 23 and the write power supply 32, and the read circuit 14 is connected to the CPU 23 and read power supply 25. The CPU 23 controls the switching between the write and read circuits. When writing is performed, a high voltage is applied from the write power supply 32, and when reading is performed, a weak current is supplied from the read power supply 25.

The write power supply 32 can change the voltage value by using the voltage level change unit 33 in accordance with a signal from the CPU 23. The selector circuit 27 selects the write-target/read-target antifuse 10 by switching the connection to the gate terminal of the transistor 12 corresponding to the write-target/read-target antifuse 10. The selector circuit 27 is connected to the pulse generation unit 26, and pulse signals are applied to the gate terminal of the transistor 12 via the selector circuit 27. The selector circuit 27 is connected to the CPU 23, and the CPU 23 can control the switching to the transistor 12 corresponding to the target antifuse 10. The pulse generation unit 26 is connected to the pulse generation power supply 28 and the CPU 23, and can generate pulse signals by being controlled by the CPU 23. The CPU 23 is also connected to the memory 29 including a nonvolatile memory (for example, a ROM) and a volatile memory (for example, a RAM). The memory 29 stores a table of correlations between write voltages and write bits.

Write Operation Processing Flow

FIG. 8 is a flowchart illustrating the write operation according to Embodiment 2. In step S401, the write operation is started. Next, in step S402, the selector circuit 27 is switched such that the antifuse 10 in the write voltage storage area 30 is selected. Next, in step S403, the state of the antifuse 10 in which the set value of the applied voltage is written is read. After the write voltage information has been read, the write voltage is set in step S404.

When the write operation is performed, first, in step S405, the selector circuit 27 selects the target antifuse 10. Next, in step S406, the write operation is performed on the antifuse 10 at the set write voltage. Next, in step S407, the read operation is performed on the antifuse 10 on which the write operation has been performed. Next, in step S408, it is determined whether or not there is a change in the state (whether or not writing has been performed) based on the contents read from the antifuse 10.

If it is determined that there is no change in the state of the antifuse element Ca (no writing has been performed) (S408=No), the processing proceeds to step S409. In step S409, the number of retries is checked. If the number of retries is less than three times (S409=Yes), the application of the voltage at the set value (S406), the read operation (S407), and the determination of the presence or absence of the change in the state (S408) are performed again. If it is determined that the number of retries is three times or more (S409=No), the processing proceeds to step S410, and error handling is performed. Next, the processing ends in step S411. If it is determined in step S408 that a change in the state has occurred (writing has been performed) (Yes), the processing directly proceeds to step S411 and ends.

As described above, according to the present embodiment, the write voltage is appropriately set before the voltage is applied to the antifuse element Ca. In this way, the write time will not be prolonged, which leads to the reduction of the processing time.