211 of the memory cell array 210 shown in FIG. 2.

Referring to FIG. 3, the memory block 211 may include a plurality of word lines WL0 to WLn−1, a drain select line DSL and a source select line SSL coupled to the row decoder 240. These lines may be arranged in parallel, with the plurality of word lines between the DSL and SSL.

The memory block 211 may further include a plurality of cell strings 221 respectively coupled to bit lines BL0 to BLm−1. The cell string of each column may include one or more drain selection transistors DST and one or more source selection transistors SST. In the illustrated embodiment, each cell string has one DST and one SST. In a cell string, a plurality of memory cells or memory cell transistors MC0 to MCn−1 may be serially coupled between the selection transistors DST and SST. Each of the memory cells may be formed as a multiple level cell. For example, each of the memory cells may be formed as a single level cell (SLC) storing 1 bit of data. Each of the memory cells may be formed as a multi-level cell (MLC) storing 2 bits of data. Each of the memory cells may be formed as a triple-level cell (TLC) storing 3 bits of data. Each of the memory cells may be formed as a quadruple-level cell (QLC) storing 4 bits of data.

The source of the SST in each cell string may be coupled to a common source line CSL, and the drain of each DST may be coupled to the corresponding bit line. Gates of the SSTs in the cell strings may be coupled to the SSL, and gates of the DSTs in the cell strings may be coupled to the DSL. Gates of the memory cells across the cell strings may be coupled to respective word lines. That is, the gates of memory cells MC0 are coupled to corresponding word line WL0, the gates of memory cells MC1 are coupled to corresponding word line WL1, etc. The group of memory cells coupled to a particular word line may be referred to as a physical page. Therefore, the number of physical pages in the memory block 211 may correspond to the number of word lines.

The page buffer array 250 may include a plurality of page buffers 251 that are coupled to the bit lines BL0 to BLm−1. The page buffers 251 may operate in response to page buffer control signals. For example, the page buffers 251 my temporarily store data received through the bit lines BL0 to BLm−1 or sense voltages or currents of the bit lines during a read or verify operation.

In various embodiments of the present invention, the memory blocks 211 may include a NAND-type flash memory cell. However, the memory blocks 211 are not limited to such cell type, and may include NOR-type flash memory cell(s). Memory cell array 210 may be implemented as a hybrid flash memory in which two or more types of memory cells are combined, or one-NAND flash memory in which a controller is embedded inside a memory chip.

FIG. 4 is a diagram illustrating distributions of states or program voltage (PV) levels for different types of cells of a memory device.

Referring to FIG. 4, each of memory cells may be implemented with a specific type of cell, for example, a single level cell (SLC) storing 1 bit of data, a multi-level cell (MLC) storing 2 bits of data, a triple-level cell (TLC) storing 3 bits of data, or a quadruple-level cell (QLC) storing 4 bits of data. Usually, all memory cells in a particular memory device are of the same type, but that is not a requirement.

An SLC may include two states P0 and P1. P0 may indicate an erase state, and P1 may indicate a program state. Since the SLC can be set in one of two different states, each SLC may program or store 1 bit according to a set coding method. An MLC may include four states P0, P1, P2 and P3. Among these states, P0 may indicate an erase state, and P1 to P3 may indicate program states. Since the MLC can be set in one of four different states, each MLC may program or store two bits according to a set coding method. A TLC may include eight states P0 to P7. Among these states, P0 may indicate an erase state, and P1 to P7 may indicate program states. Since the TLC can be set in one of eight different states, each TLC may program or store three bits according to a set coding method. A QLC may include 16 states P0 to P15. Among these states, P0 may indicate an erase state, and P1 to P15 may indicate program states. Since the QLC can be set in one of sixteen different states, each QLC may program or store four bits according to a set coding method.

Referring back to FIGS. 2 and 3, the memory device 200 may include a plurality of memory cells (e.g., NAND flash memory cells). The memory cells are arranged in an array of rows and columns as shown in FIG. 3. The cells in each row are connected to a word line (e.g., WL0), while the cells in each column are coupled to a bit line (e.g., BL0). These word and bit lines are used for read and write operations. During a write operation, the data to be written (‘1’ or ‘0’) is provided at the bit line while the word line is addressed. During a read operation, the word line is again addressed, and the threshold voltage of each cell can then be acquired from the bit line. Multiple pages may share the memory cells that belong to (i.e., are coupled to) the same word line. When the memory cells are implemented with MLCs, the multiple pages include a most significant bit (MSB) page and a least significant bit (LSB) page. When the memory cells are implemented with TLCs, the multiple pages include an MSB page, a center significant bit (CSB) page and an LSB page. When the memory cells are implemented with QLCs, the multiple pages include an MSB page, a center most significant bit (CMSB) page, a center least significant bit (CLSB) page and an LSB page. The memory cells may be programmed for example using a coding scheme (e.g., Gray coding) in order to increase the capacity of the memory system 10 such as SSD.

FIG. 5A is a diagram illustrating an example of coding for a multi-level cell (MLC).

Referring to FIG. 5A, an MLC may be programmed using a set type of coding. An MLC may have 4 program states, which include an erased state E (or PV0) and a first program state PV1 to a third program state PV3. The erased state E (or PV0) may correspond to “11.” The first program state PV1 may correspond to “10.” The second program state PV2 may correspond to “00.” The third program state PV3 may correspond to “01.”

In the MLC, as shown in FIG. 5B, there are 2 types of pages including LSB and MSB pages. 1 or 2 thresholds may be applied in order to retrieve data from the MLC. For an MSB page, the single threshold value is VT1. VT1 distinguishes between the first program state PV1 and the second program state PV2. For an LSB page, 2 thresholds include a threshold value VT0 and a threshold value VT2. VT0 distinguishes between the erased state E and the first program state PV1. VT2 distinguishes between the second program state PV2 and the third program state PV3.

FIG. 6A is a diagram illustrating an example of Gray coding for a triple-level cell (TLC).

Referring to FIG. 6A, a TLC may be programmed using Gray coding. A TLC may have 8 program states, which include an erased state E (or PV0) and a first program state PV1 to a seventh program state PV7. The erased state E (or PV0) may correspond to “111.” The first program state PV1 may correspond to “011.” The second program state PV2 may correspond to “001.” The third program state PV3 may correspond to “000.” The fourth program state PV4 may correspond to “010.” The fifth program state PV5 may correspond to “110.” The sixth program state PV6 may correspond to “100.” The seventh program state PV7 may correspond to “101.”

In the TLC, as shown in FIG. 6B, there are 3 types of pages including LSB, CSB and MSB pages. 2 or 3 thresholds may be applied in order to retrieve data from the TLC. For an MSB page, 2 thresholds include a threshold value VT0 that distinguishes between an erase state E and a first program state PV1 and a threshold value VT4 that distinguishes between a fourth program state PV4 and a fifth program state PV5. For a CSB page, 3 thresholds include VT1, VT3 and VT5. VT1 distinguishes between a first program state PV1 and a second program state PV2. VT3 distinguishes between a third program state PV3 and the fourth program state PV4. VT5 distinguishes between the fourth program state PV5 and the sixth program state PV6. For an LSB page, 2 thresholds include VT2 and VT6. VT2 distinguishes between the second program state PV2 and the third program state PV3. VT6 distinguishes between the sixth program state PV6 and a seventh program state PV7.

After a memory array including a plurality of memory cells is programmed as described in FIGS. 5A and 6A, when a read operation is performed on the memory array using a reference voltage such as a read threshold voltage (also called “read voltage level” or “read threshold”), the electrical charge levels of the memory cells (e.g., threshold voltage levels of transistors of memory cells) are compared to one or more reference voltages to determine the state of individual memory cells. When a specific read threshold is applied to the memory array, those memory cells that have threshold voltage levels higher than the reference voltage are turned on and detected as “on” cell, whereas those memory cells that have threshold voltage levels lower than the reference voltage are turned off and detected as “off” cell, for example. Therefore, each read threshold is arranged between neighboring threshold voltage distribution windows corresponding to different programmed states so that each read threshold can distinguish such programmed states by turning on or off the memory cell transistors.

When a read operation is performed on memory cells in a data storage device using MLC technology, the threshold voltage levels of the memory cells are compared to more than one read threshold level to determine the state of individual memory cells. Read errors can be caused by distorted or overlapped threshold voltage distributions. An ideal memory cell threshold voltage distribution can be significantly distorted or overlapped due to, e.g., program and erase (P/E) cycles, cell-to-cell interference, and/or data retention errors. For example, as program/erase cycles increase, the margin between neighboring threshold voltage distributions of different programmed states decreases and eventually the distributions overlap. As a result, the memory cells with threshold voltages that fall within the overlapping region of the neighboring distributions may be read as being programmed to a value other than the original targeted value and thus cause read errors. Such read errors may be managed in many situations by using error correction codes (ECC). When the number of bit errors on a read operation exceeds the ECC correction capability of the data storage, the read operation using a set read threshold voltage fails. The set read threshold voltage may be a previously used read threshold voltage (i.e., a historical read threshold voltage). The historical read threshold voltage may be the read threshold voltage used in the last successful decoding, that is, a read voltage used in a read-passed read operation performed before read retry operations. When the read operation using the set read threshold voltage failed, the controller 120 may control an error recovery algorithm such as for example the algorithm shown in FIG. 7.

Referring to FIG. 7, a controller (such as control component 120 in FIG. 2) may perform one or more read retry operations for the memory cells using one or more read threshold voltages applied in a set order (S100). For example, the read threshold voltages may include N (e.g., N is 5 or 10) read threshold voltages (or read voltage levels) including a first read threshold voltage to an Nth read threshold voltage. The first read threshold voltage may be a previously used read threshold voltage (i.e., a history (historical) read threshold voltage). The historical read threshold voltage may be the read threshold voltage used in the last successful decoding, that is, a read voltage used in a read-passed read operation performed before the read retry operations. The controller 120 may perform the read retry operations until it is determined that decoding associated with a corresponding read retry operation is successful.

When all read retry operations using the read threshold voltages have failed, controller 120 may perform additional recovery operations. For example, the additional recovery operations may include an optimal read threshold voltage search (S200), a soft decoding using an error correction code (ECC) (S300) and/or a redundant array of independent disks (RAID) recovery (S400).

As noted above, in existing memory systems (e.g., a solid state drive (SSD)), searching for an optimal read voltage threshold or threshold voltage (Vt) is required if all/some of the pre-defined threshold voltages (called hard read retry (HRR)) lead to decoding failure. For the optimal read threshold voltage search, a controller (e.g., firmware (FW)) performs an optimal read algorithm (often referred to as an eBoost algorithm). The eBoost algorithm is accurate enough to provide high reliability. However, it is very costly since it needs additional reads to estimate distributions of all threshold voltage levels and to approximate Gaussian hyper parameters for each level distribution. Read data for each eBoost read is transferred from a memory device to the controller, which causes additional transfer delay for each read. This will increase read collision with other host read(s) and reduce the overall performance of the memory system. Accordingly, embodiments of the present invention provide a scheme for an optimal read threshold voltage search capable of reducing an amount of information transferred for each read and the transfer delay. Embodiments of the present inventions provide a non-blocking Vt search scheme in which the only needed information (i.e., count formation) for each eBoost read is transferred to a controller from a memory device, instead of transferring all the read data. Here, non-blocking refers to the ability of a program or system to continue execution without being blocked or held by other program or system calls. This scheme can reduce unnecessary transfer time for all the additional reads and improve the overall performance/power of the memory system.

FIG. 8 is a diagram illustrating a memory system 800 in accordance with one embodiment of the present invention.

Referring to FIG. 8, the memory system 800 may include a controller 810 and a memory device 820. As shown, the controller 810 may include a Gaussian Model (GM) module 812 and an optimal read threshold voltage (OPT Vt) determiner 814, and the memory device 820 may include at least one memory cell 822 and a pattern counter 824. Further, the controller 810 and the memory device 820 may include other elements such as elements shown in FIGS. 1 and 2. That is, the controller 810 and the memory device 820 may be a memory system corresponding to the memory system 10 including the controller 100 and the memory device 200 shown in FIGS. 1 and 2. In some embodiments, the controller 810 may be implemented with firmware and system on chip (SoC), and the memory device 820 may be implemented with a non-volatile memory such as a NAND flash memory.

The controller 810 may generate a command associated with an eBoost algorithm for searching for an optimal read threshold voltage. In some embodiments, the command may be referred to as a Gaussian model (GM) command, as the eBoost algorithm finds an optimal read threshold by estimating a region of each read threshold voltage level as a Gaussian model. The eBoost algorithm may be triggered if read operations using all/some of the pre-defined read threshold voltages lead to decoding failure. That is, the GM command may be a kind of a read request which is generated in response to the triggering of the eBoost algorithm. The GM command may be provided to the memory cell 822 of the memory device 820.

The memory cell 822 may output read data item among the multiple data items, which is data read corresponding to the read request (i.e., GM command). The memory cell 822 may be implemented with NAND flash memory cells, each cell including a plurality of pages for storing multiple data items. The memory cells are arranged in an array of rows and columns such as shown in FIG. 3. The cells in each row are connected to a word line (e.g., WL0), while the cells in each column are coupled to a bit line (e.g., BL0). These word and bit lines are used for read and write operations. During a write operation, the data to be written (‘1’ or ‘0’) is provided at the bit line while the word line is addressed. During a read operation, the word line is again addressed, and the threshold voltage of each cell can then be acquired from the bit line. Multiple pages may share the memory cells that belong to (i.e., are coupled to) the same word line. When the memory cells are implemented with MLCs, the multiple pages include a most significant bit (MSB) page and a least significant bit (LSB) page. When the memory cells are implemented with TLCs, the multiple pages include an MSB page, a center significant bit (CSB) page and an LSB page. When the memory cells are implemented with QLCs, the multiple pages include an MSB page, a center most significant bit (CMSB) page, a center least significant bit (CLSB) page and an LSB page. The memory cells may be programmed using a coding scheme (e.g., Gray coding) in order to increase the capacity of the memory system 800 such as an SSD. Operations for the memory cell 822 may be controlled by a control circuit (such as control circuit 220 in FIG. 2) and other elements as shown in FIG. 2.

In some embodiments, the memory cell 822 may output read data items corresponding to multiple reads in response to the GM command. For example, when the memory cell is implemented with TLC, read data items for 20 reads may be output to estimate distributions of all read threshold voltage levels.

The pattern counter 824 may receive at least one read data item from the memory cell 822. The pattern counter 824 may count, from the read data item, the number of cells reading as a particular value (e.g., one (1)) in multiple voltage level regions corresponding to multiple patterns for multiple pages among the plurality of pages. The pattern counter 824 may generate count information based on the counting operation and provide the count information to the GM module 810 of the controller 810.

A counting operation of the pattern counter 824 is described with reference to FIG. 9.

FIG. 9 illustrates a typical TLC read threshold voltage (Vt) histogram where an X-axis represents distributions (or regions) of read threshold voltage levels and a Y-axis represents the number of cells. The reference characters R1-R7 represent the corresponding read voltage for each voltage level distribution according to LSB, CSB, and MSB reference read levels (denoted by the legend on the left side).

The pattern counter 824 may perform a counting operation for reads from TLC memory cells according to particular patterns.

For the read of MSB page, the pattern counter 824 may obtain the number of cells reading as a particular value (e.g., cells reading as 1s) in the multiple voltage level regions according to the pattern (R1, R5) associated with MSB pages. Using R1, the number of cells reading 1s in the voltage level region LR0 are obtained as the count value (cnt0). Using R5, the total number of cells reading 1s in the voltage level regions LR0-LR4 are obtained. Further, the total number of cells reading 1s in the voltage level regions LR0-LR7 are obtained. Then, using this information and by subtracting the measured counts from the different voltage level regions, the pattern counter 824 may generate the following count information corresponding to the pattern (R1, R5): MSB_count_info=(cnt0, cnt1+cnt2+cnt3+cnt4, cnt5+cnt6+cnt7). In these count equations provided for MSB, we assume that the length of codeword is known. Let us call it n. There is an additional equation which is cnt0+cnt1+cnt2+cnt3+cnt4+cnt5+cnt6+cnt7=n. From R1, the number of cnt0 is obtained. From R5, the equation cnt0+cnt1+cnt2+cnt3+cnt4 is obtained. By subtracting the equation cnt0+cnt1+cnt2+cnt3+cnt4 (related to R5) from the additional equation n (assuming known codeword length), the sum of cnt5+cnt6+cnt7 is obtained.

In some embodiments, the number of cells reading as the particular value may indicate the number of ones (1s) bits in each voltage level region. The count information may include first count information (cnt0) indicating the number of cells in the first voltage level region LR0, second count information (cnt1+cnt2+cnt3+cnt4) indicating the number of cells in a range of the second to fifth voltage level regions LR1-LR4, and third count information (cnt5+cnt6+cnt7) indicating the number of cells in a range of the sixth to eighth voltage level regions LR5-LR7.

For read of CSB page, the pattern counter