116, an etch process is performed to the target layer 112 using the photoresist layer 114 as an etch mask, thus forming trenches 126 in the target layer 112. For example, the etch process is a dry etch process including a biased plasma etch process that uses a chlorine-based chemistry, CF₄, NF₃, SF₆, or the like. The dry etch process may be performed anisotropically. Due to the photoresist layer 114 deposited by the photoresist composition including the one or more first additives 116 (see FIG. 2B), the photoresist layer 114 can have enhanced etch resistance for the etch process. That is, during the etch process performed to the target layer 112, an undesired collapse or deformation of the photoresist layer 114 may be prevented. Therefore, the photoresist layer 114 can be prevented from failure of feature fidelity during the etch process, and an extensive process window can be accomplished.

FIGS. 8-11 are cross-sectional views of a semiconductor device 42 in an intermediate stage of fabrication in accordance with some embodiments of the present disclosure. FIG. 12A is a perspective view of the semiconductor device 42 in an intermediate stage of fabrication in accordance with some embodiments of the present disclosure. FIGS. 12B and 12C are cross-sectional views along line a1-a1 and line b1-b1 of FIG. 12A, respectively, in accordance with various aspects of the present disclosure. FIGS. 13-16 are cross-sectional views of the semiconductor device 42 in an intermediate stage of fabrication in accordance with some embodiments of the present disclosure. Reference is made to FIG. 8. A photoresist layer 45 is formed on a substrate 44. The photoresist layer 45 and the substrate 44 are similar to the photoresist layer 114 and the substrate 110 in terms of composition as discussed previously with regard to FIGS. 2A-4F, and thus the description thereof is omitted herein.

The photoresist layer 45 may be formed on the substrate 44 using multiple operations including the operations S102, S104, S106, S108, S110 and S112 in the method 1000 in FIG. 1. Therefore, the description thereof is omitted herein. Reference is made to FIG. 9. An etch process is performed to the substrate 44 using the photoresist layer 45 as an etch mask such that trenches 54 are formed in the substrate 44. In some embodiments, the etch process is similar to the operation S114, and thus the description thereof is omitted herein. As discussed previously with regard to FIGS. 2A to 4F, due to the photoresist layer deposited by the photoresist composition including the one or more first additives 116, the photoresist layer 45 can have enhanced etch resistance for the etch process. That is, during the etch process performed to the substrate 44, an undesired collapse or deformation of the photoresist layer 45 may be prevented. Therefore, the photoresist layer 45 can be prevented from failure of feature fidelity during the etch process, and an extensive process window can be accomplished.

The photoresist layer 45 is removed after etching the substrate 44 by using a suitable photoresist stripper solvent or by a photoresist ashing operation. Isolation regions such as shallow trench isolation (STI) regions 56 may be formed on the substrate 44, filling into the trenches 54. The resulting structure in shown in FIG. 10.

The STI regions 56 may include a liner oxide (not shown). The liner oxide may be formed of a thermal oxide formed through a thermal oxidation of a surface layer of the substrate 44. The liner oxide may also be a deposited silicon oxide layer formed using, for example, Atomic Layer Deposition (ALD), High-Density Plasma Chemical Vapor Deposition (HDPCVD), or Chemical Vapor Deposition (CVD). The STI regions 56 may also include a dielectric material over the liner oxide, and the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin-on coating, or the like.

Referring to FIG. 11, the STI regions 56 are recessed, so that the top portions of semiconductor strips 102 protrude higher than top surfaces of the neighboring STI regions 56 to form protruding fins 104. The etching may be performed using a dry etching process or a wet etching process.

Referring to FIGS. 12A-12C, a dummy gate stack 58 is formed on top surfaces and sidewalls of the protruding fins 104. The dummy gate stack 58 may include a dummy gate dielectric 60 and a dummy gate electrode 62 over the dummy gate dielectric 60. The dummy gate dielectric 60 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. The dummy gate electrode 62 may be deposited over the dummy gate dielectric 60 and then planarized, such as by a CMP. The dummy gate electrode 62 may be deposited by PVD, CVD, sputter deposition, or other techniques for depositing the selected material.

The dummy gate dielectric 60 may further include an interfacial layer (not shown) including silicon oxide. The dummy gate electrode 62 may be formed, for example, using polysilicon, and other materials may also be used. The dummy gate electrode 62 may be made of other materials that have a high etching selectivity from the etching of STI regions 56. The dummy gate stack 58 may also include hard mask layers 64a and 64b over the dummy gate electrode 62. The hard mask layers 64a and 64b may be formed of silicon nitride and silicon oxide, respectively. The dummy gate stack 58 may cross over a single one or a plurality of protruding fins 104 and/or STI regions 56. The dummy gate stack 58 also has a lengthwise direction perpendicular to the lengthwise directions of protruding fins 104.

A photoresist layer 66 is formed over the dummy gate stack 58. In some embodiments, a pad layer (not shown) and a hard mask layer (not shown) may be formed between the photoresist layer 66 and the dummy gate stack 58. The pad layer and the hard mask layer have an etch selectivity with respect to the photoresist layer 66. The pad layer may be a silicon oxide layer and the hard mask layer may be a silicon nitride layer, for example. The above discussion of the first additives 116 (see FIG. 2B) of the photoresist composition of the photoresist layer 114 (see FIG. 2A) applies to the photoresist layer 66, unless mentioned otherwise.

In FIG. 13, using the photoresist layer 66 (see FIG. 12C) as a mask, the pattern of the photoresist layer 66 are extended into the dummy gate stack 58 by etching, using one or more suitable etchants. In some embodiments, the photoresist layer 66 is removed after etching the dummy gate stack 58 by using a suitable photoresist stripper solvent or by a photoresist ashing operation. As discussed previously with regard to FIGS. 2A to 4F, due to the photoresist layer 66 deposited by the photoresist composition including the one or more first additives 116, the photoresist layer 66 can have enhanced etch resistance for the etch process. That is, during the etch process performed to the dummy gate stack 58, an undesired collapse or deformation of the photoresist layer 66 may be prevented. Therefore, the photoresist layer 66 can be prevented from failure of feature fidelity during the etch process, and an extensive process window can be accomplished.

Next, as illustrated in FIG. 14, gate spacers 72 are formed on sidewalls of the dummy gate stack 58. In some embodiments of the gate spacer formation step, a spacer material layer is deposited on the substrate 44 and the dummy gate stack 58. The spacer material layer may be a conformal layer that is subsequently etched back to form gate spacers 72. The spacer material layer is made of a low-k dielectric material. The low-k dielectric material has a dielectric constant (k value) of lower than about 3.5. Suitable materials for the low-k dielectric material may include, but are not limited to, doped silicon dioxide, fluorinated silica glass (FSG), carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, SiLK™ (an organic polymeric dielectric distributed by Dow Chemical of Michigan), Black Diamond (a product of Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, bis-benxocyclocutenes (BCB), polyimide, polynoroboneses, benzocyclocutene, PTFE, porous SiLK, hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ), and/or combinations thereof. By way of example and not limitation, the spacer material layer may be formed using processes such as, CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a physical vapor deposition (PVD) process, or other suitable process. An anisotropic etching process is then performed on the deposited spacer material layer to expose portions of the fins 104 not covered by the dummy gate stack 58 (e.g., in source/drain regions of the fins 104). Portions of the spacer material layer directly above the dummy gate stack 58 may be completely removed by this anisotropic etching process. Portions of the spacer material layer on sidewalls of the dummy gate stack 58 may remain, forming gate spacers, which are denoted as the gate spacers 72, for the sake of simplicity. In some embodiments, the gate spacers 72 may be used to offset subsequently formed doped regions, such as source/drain regions. The gate spacers 72 may further be used for designing or modifying the source/drain region profile.

In FIG. 15, after formation of the gate spacers 72 is completed, source/drain epitaxial structures 74 are formed on source/drain regions of the protruding fins 104 that are not covered by the dummy gate stack 58 and the gate spacers 72. In some embodiments, formation of the source/drain epitaxial structures 74 includes recessing source/drain regions of the fins 104, followed by epitaxially growing semiconductor materials in the recessed source/drain regions of the fins 104. The source/drain epitaxial structures 74 are on opposite sides of the dummy gate stack 58.

The source/drain regions of the fins 104 can be recessed using suitable selective etching processing that attacks the fins 104, but hardly attacks the gate spacers 72 and the hard mask layer 64b of the dummy gate stack 58. For example, recessing the fins 104 may be performed by a dry chemical etch with a plasma source and an etchant gas. The plasma source may be inductively coupled plasma (ICR) etch, transformer coupled plasma (TCP) etch, electron cyclotron resonance (ECR) etch, reactive ion etch (RIE), or the like and the etchant gas may be fluorine, chlorine, bromine, combinations thereof, or the like, which etches the protruding fins 104 at a faster etch rate than it etches the gate spacers 72 and the hard mask layer 64b of the dummy gate stack 58. In some other embodiments, recessing the protruding fins 104 may be performed by a wet chemical etch, such as ammonium peroxide mixture (APM), NH₄OH, tetramethylammonium hydroxide (TMAH), combinations thereof, or the like, which etches the fins 104 at a faster etch rate than it etches the gate spacers 72 and the hard mask layer 64b of the dummy gate stack 58. In some other embodiments, recessing the protruding fins 104 may be performed by a combination of a dry chemical etch and a wet chemical etch.

Once recesses are created in the source/drain regions of the fins 104, source/drain epitaxial structures 74 are formed in the source/drain recesses in the fins 104 by using one or more epitaxy or epitaxial (epi) processes that provides one or more epitaxial materials on the protruding fins 104. During the epitaxial growth process, the gate spacers 72 limit the one or more epitaxial materials to source/drain regions in the fins 104. In some embodiments, the lattice constants of the source/drain epitaxial structures 74 are different from the lattice constant of the fins 104, so that the channel region in the fins 104 and between the source/drain epitaxial structures 74 can be strained or stressed by the source/drain epitaxial structures 74 to improve carrier mobility of the semiconductor device and enhance the device performance. The epitaxy processes include CVD deposition techniques (e.g., PECVD, vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The epitaxy process may use gaseous and/or liquid precursors, which interact with the composition of the fins 104.

In some embodiments, the source/drain epitaxial structures 74 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material. The source/drain epitaxial structures 74 may be in-situ doped during the epitaxial process by introducing doping species including: p-type dopants, such as boron or BF₂; n-type dopants, such as phosphorus or arsenic; and/or other suitable dopants including combinations thereof. If the source/drain epitaxial structures 74 are not in-situ doped, an implantation process (i.e., a junction implant process) is performed to dope the source/drain epitaxial structures 74. In some exemplary embodiments, the source/drain epitaxial structures 74 in an n-type transistor include SiP, while those in a p-type include GeSnB and/or SiGeSnB. In embodiments with different device types, a mask, such as a photoresist, may be formed over n-type device regions, while exposing p-type device regions, and p-type epitaxial structures may be formed on the exposed fins 104 in the p-type device regions. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type device region while exposing the n-type device regions, and n-type epitaxial structures may be formed on the exposed fins 104 in the n-type device region. The mask may then be removed.

Once the source/drain epitaxial structures 74 are formed, an annealing process can be performed to activate the p-type dopants or n-type dopants in the source/drain epitaxial structures