Embodiments include a FET stack comprising one or more series-coupled positive-logic FETs M1-Mn (i.e., zero-Vt, low-Vt, or high-Vt FETs of a type that require a negative V_GSto turn OFF but configured so as to not require a negative power supply), series-coupled on at least one end to an “end-cap” FET M₀, where “M₀” designates a FET of a high-Vt type that turns OFF when the V_GSof such FET is essentially zero volts. The end-cap M₀FETs selectably provide either a capacitive DC blocking function or a resistive signal path. Some embodiments may comprise a stack of only M₀FETs, or a mix of positive-logic FETs and M₀FETs, so long as at least one end-cap FET is an M₀FET. Optional end-cap capacitors may be included to prevent early breakdown of corresponding end-cap M₀FETs.

Some embodiments are configured to withstand high applied RF voltages by including a series-connected bias resistor ladder for the gates of the FETs in the stack (i.e., M1-Mn, M₀), a series-connected Rds drain-source resistor ladder, and either a series-connected or a parallel-connected Rb body charge control resistor ladder. Some embodiments may use series-connected Rb body charge control resistor ladder in conjunction with a parallel-connected bias resistor ladder for the gates. Some embodiments may use a series-connected bias resistor ladder (in a “rail” configuration) in conjunction with a parallel-connected bias resistor ladder (in a “rung” configuration) for the gates.

Some embodiments are configured with one or more AC coupling modules each coupled to at least one end of a corresponding gate bias resistor ladder and/or body charge control resistor ladder, and configured to be coupled to a radio frequency voltage source.

Embodiments of the invention may be used in any circuit configuration in which a FET stack may be necessary or useful, such as RF switch circuits and digitally tuned capacitors (for example, of the type taught in U.S. patent application Ser. No. 15/256,453).

Selectable DC Blocking Embodiments

FIG. 4 is a schematic circuit of an improved positive logic FET stack 400. The stack 400 comprises one or more series-coupled FETs M1-Mn. Each of the FETs M1-Mn are of a type that require a negative V_GSto turn OFF (e.g., −3V) but which are configured to not require a negative power supply, as taught in co-pending U.S. patent application Ser. No. 15/256,453. Examples of such FETs M1-Mn may have a V_T≈0V and a low R_ON(e.g., much less than Z₀ohms, where Z₀is the system characteristic impedance).

In some embodiments, the FETs M1-Mn in the “interior” of the stack 400, which may be zero-Vt, low-Vt, or high-Vt FETs, are bracketed by “end-cap” M₀high-Vt FETs. In other embodiments, only one end of one or more series-coupled positive-logic FETs M1-Mn is series coupled to an M₀FET; thus, for example, the end-cap M₀FET in dashed box 402 or the end-cap M₀FET in dashed box 404 may be omitted in some applications. Zero-Vt, low-Vt and high-Vt FETs are available from a number of different IC commercial foundries. Examples of such end-cap M₀FETs may have a V_T≈0.7V, and may have a higher R_ONthan the FETs M1-Mn.

Each FET M1-Mn, M₀includes an associated gate resistor Rg; in the illustrated example, the gate resistors Rg are dedicated to each FET and parallel to each other (for other configurations, see below).

Two non-negative supply voltages, Vgate and Vdrain, are used to control the switch state, ON or OFF, of associated FETs M1-Mn, M₀. The Vgate supply voltage is coupled to the gates of the FETs of the stack 400 through corresponding dedicated parallel gate resistors Rg. The Vdrain supply voltage is coupled to a network of parallel resistors Rds that are coupled as shown to respective sources or drains of each of the FETs M1-Mn, including shared drains-source nodes between the FETs M1-Mn. In the embodiment of FIG. 4, the gate resistors Rg and the network resistors Rds may be of equal size, but a person skilled in the art will understand that other embodiments may include resistors of different sizes.

In the embodiment shown in FIG. 4, the drain and source of each end-cap M₀FET is coupled in parallel with a capacitor Cd. As disclosed in greater detail below, since the end-cap M₀FETs are biased with Vgs=0V and thus usually cannot handle the full drain-source voltage Vds applied across them, the Vds across each end-cap M₀FET is lowered (e.g., to 2V) by their respective capacitor Cd.

FIG. 5A is a table showing example voltages for Vgate and Vdrain corresponding to ON and OFF states for the FET stack of FIG. 4. FIG. 5B is a simplified schematic circuit of the FET stack of FIG. 4 showing example drain and source voltages for the interior FETs Mn and end-cap M₀FETs when in an ON state. FIG. 5C is a simplified schematic circuit of the FET stack of FIG. 4 showing example drain and source voltages for the interior FETs Mn and end-cap M₀FETs when in an OFF state.

In the example illustrated in FIGS. 4 and 5B, the FETs FET M1-Mn, M₀are turned ON by applying a positive Vgate voltage (e.g., +3V) to the FET gates through their respective gate resistors Rg, while applying a Vdrain voltage of 0V to the drains and sources of FETs M1-Mn through respective Rds resistors. (Note that, technically, the source for the “top” M₀FET would be, for example, a coupled antenna or other RF signal source, and thus its drain is at the “bottom” end of that FET. Similarly, the source for the “bottom” M₀FET would be, for example, circuit ground, and thus its drain is at the “top” end of that FET. Accordingly, the Vdrain voltage is coupled to the respective drains of both the “top” M₀FET and the “bottom” M₀FET. As should be clear, “top” and “bottom” are with respect to the illustrated orientation of the FET stack in FIG. 4 and are for convenience only). This configuration effectively creates a positive DC gate-source voltage, V_GS, for every FET M1-Mn, M₀(i.e., V_GS=+3V with respect to the source voltage of 0V if Vgate=+3V), as shown in FIG. 5B. In the ON state, the end-cap M₀FETs each present a series resistance of R_ON. Since the ON-state end-cap M₀FETs essentially present no series capacitance, shunt tuning inductors L for impedance matching may be omitted, thus improving broadband performance and reducing consumption of IC area.

In the example illustrated in FIGS. 4 and 5C, the FETs FET M1-Mn, M₀are turned OFF by applying a Vgate voltage of 0V to the FET gates through their respective gate resistors Rg, while applying a positive Vdrain voltage (e.g., +3V) to the drains and sources of FETs M1-Mn (and thus to the source of the “top” M₀FET, and to the drain of the “bottom” M₀FET) through respective Rds resistors. This effectively creates a negative V_GSfor every FET M1-Mn (i.e., V_GS=−3V with respect to the source voltage of +3V if Vgate=0V), as shown in FIG. 5C. The end-cap M₀FETs have either a V_GSof −3V (for the “top” M₀FET) or 0V (for the “bottom” M₀FET), either of which is sufficient to turn the end-cap M₀FETs OFF in light of their V_GScharacteristics (although the current blocking capability of the end-cap M₀FETs increases as V_GSbecomes more negative). In the OFF state, the end-cap M₀FETs each present a series capacitance of C_OFF, and thus perform a DC blocking function.

As an alternative embodiment, when the “bottom” M₀FET is ON, the terminal labeled Vdrain in FIG. 4 can be left as an open circuit, since all of the FETs coupled to the Rds resistor network would be coupled to circuit ground through the “bottom” M₀FET. For the OFF state, the terminal labeled Vdrain in FIG. 4 would be coupled to a suitable voltage (e.g., +3V).

In the example embodiment of FIG. 4, Vdrain is varied between 0V to 3V as a function of the ON or OFF state of the FET stack 400. In other embodiments, Vdrain may be set as a fixed voltage, such as a constant mid-rail voltage (e.g., +1.5V). Thus, similar to the example shown in FIG. 5A-5C, when Vgate is high (e.g., +3V), a positive voltage of +1.5V will appear across the gate-source of each FET M1-Mn, M₀and turn those FETs ON. Conversely, when Vgate is low (e.g., 0V), a negative voltage of −1.5V will appear across the gate-source of each interior FET M1-Mn and turn those FETs OFF; similarly, V_GSfor the “top” end-cap M₀FET will be −1.5V, while the V_GSfor the “bottom” end-cap M₀FET will be 0V, and thus both of the end-cap M₀FETs will be OFF. In a constant Vdrain biasing scheme, lower or higher voltages (e.g., +0.5V) may also be used for Vdrain. In a further embodiment, the fixed mid-rail voltage may be chosen based on the threshold voltage, V_T, of the FETs to provide a beneficial (potentially optimal) level of gate overdrive (V_GS−V_T) to balance performance parameters in both ON and OFF states. More generally, the voltages for Vgate and Vdrain can be selected (and potentially optimized) to provide a balanced amount of gate overdrive. If Vdrain is biased to a non-zero DC voltage, a correctly sized shunt capacitor (or RC filter) may need to be added to sufficiently filter out RF voltage swings.

The circuit configuration of the FET stack 400 of FIG. 4 is thus similar to the circuit configurations of the stacks 302, 304 of FIG. 3, except that the end-cap M₀FETs are used for DC blocking instead of explicit DC blocking capacitors C. In operation, the end-cap M₀FETs can be turned to an OFF state in which they function as DC blocking capacitors having a capacitance of C_OFF. Importantly, the end-cap M₀FETs also can be turned to an ON state that forms an actual resistive DC path rather than a capacitance, resulting in little or no insertion loss, mismatch loss, or frequency dependence penalty compared to constantly present DC blocking capacitors C, and also decreasing switching and settling times. While the R_ONfor the end-cap M₀FETs generally may be greater than the R_ONfor the interior FETs M1-Mn, with larger numbers of interior FETs M1-Mn (i.e., higher stack heights), the R_ONof the interior FETs M1-Mn will dominate the series resistance.

A further benefit of using one or more end-cap M₀FETs as DC blocking capacitances is that they provide automatic ESD protection, because the FET stack is self-protected by drain-to-source breakdown and there are no additional series components between the FET drain-source terminals and the external ports (ESD pulses are applied across external ports). Accordingly, shunt tuning inductors L for ESD protection of MIM capacitors in FET stacks coupled to ports may be omitted, thus reducing consumption of IC area. In addition, using one or more end-cap M₀FETs provides a reasonable “un-powered OFF” state for applications that benefit from some isolation when the system voltage supply, V_CC, equals 0V.

In some embodiments, all of the FETs in a stack 400 may be of the M₀type. In other embodiments, some (but not all) of the interior FETs in a stack 400 may be of the M₀type, so long as at least one end-cap M₀FET is provided. For example, the stack 400 may comprise a mix of FETs in a sequence such as M₀-M1-M₀-M2-M₀, where M1 and M2 are positive-logic FETS. Such mixed configurations may have a higher series resistance than the embodiment shown in FIG. 4, due to higher R_ONfor the M₀FETs, but would have a lower R_ONthan a stack comprising all M₀-type FETs. Mixed configurations of FET types and sequences can be used to help optimize the total stack performance parameters of R_ON, OFF isolation, peak voltage (Vpk) handling, DC operation, and un-powered circuit behavior.

Referring back to FIG. 4, optional capacitors Cd may be coupled in parallel with the end-cap M₀FETs, from drain to source, as indicated by the dotted connector lines. When the end-cap M₀FETs are in an ON state, the optional capacitors Cd are effectively bypassed and thus functionally out of the RF signal path. When the end-cap M₀FETs are in an OFF state, the optional capacitors Cd are coupled to the RF signal path in parallel with the end-cap M₀FETs (which each present as a capacitance of C_OFF). One advantage of the optional capacitors Cd is that they reduce RF voltage swing across the end-cap M₀FETs (e.g., to 2V instead of a full 3V) and thus help prevent early breakdown of those FETs. It may be desirable for the optional capacitors Cd to have a capacitance that is about 5-10 times the C_OFFof the end-cap M₀FETs. In some embodiments, only the “bottom” M₀FET (i.e., nearest circuit ground in FIG. 4) includes the capacitor Cd.

With further reference to FIG. 4, the person skilled in the art will appreciate that, regardless of the switching state of the FET stack 400, and except for leakage currents, the FET stack 400 and generation of the bias voltages Vgate and Vdrain does not consume any significant DC power, unlike the case of FET stacks that require a charge pump. This is very beneficial for integrated circuits with stringent power or current consumption requirements. Embodiments may use the existing system voltage supply rail to provide Vgate and Vdrain; however, a person skilled in the art will understand that other design choices to provide Vgate and Vdrain may be envisaged.

In yet other embodiments, the gates of one or both of the end-cap M₀FETs may be biased separately from the interior FETs M1-Mn. For example, biasing the gates of both end-cap M₀FETs with a negative gate voltage (and thus a negative V_GS) would more completely turn both FETs OFF and improve the linearity and harmonics performance of those FETs, but would not require a significant current draw since such FETs inherently draw low body current and are only two in number. Negative biasing would also allow the optional capacitors Cd to be much smaller than otherwise, or to be omitted entirely. Accordingly, a simple negative voltage generator could be used to generate a negative gate voltage bias for just the end-cap M₀FETs.

FIG. 6 is a schematic diagram of a series-shunt RF switch circuit 600 using the improved positive logic FET stacks of FIG. 4. In the illustrated example, an RF signal from an antenna ANT is coupled from RF_INthrough a series stack 602 to RF_OUT. A shunt stack 604 is coupled between RF_OUTand a reference potential (circuit ground in this case). Each of the stacks 602, 604 are similar to the FET stack 400 of FIG. 4, although “n” may differ for the two stacks 602, 604. (To avoid clutter, labels for the gate resistors Rg and the resistors Rds of the network coupled to the sources or drains of each of the FET M1-Mn, M₀are omitted). As described above with respect to FIG. 4, each of the stacks 602, 604 is configured to be coupled to two non-negative supply voltages, Vgate and Vdrain. Optional capacitors Cd are shown as coupled in parallel with the end-cap M₀FETs. Notably absent are constantly connected DC blocking capacitors or shunt tuning and ESD protection inductors L, as in FIG. 3.

In a variation of the series-shunt RF switch circuit 600 of FIG. 6, only one end of the series stack 602 and/or the shunt stack 604 includes an end-cap M₀FET.

Stacked FET Switch Bias Ladders

In the embodiments of the invention disclosed above, Vgate is applied to each FET M1-Mn, M₀through an associated gate resistor Rg in a conventional biasing scheme, which provides excellent performance in many applications, including low power RF switch circuits and many series and/or shunt circuit configurations. However, for high RF voltage applications, such as RF tuning switches, an innovative biasing scheme provides for an enhanced ability to withstand such voltages.

To better understand the problem posed by application of high RF voltages to a FET stack, FIG. 7 depicts a schematic equivalent circuit of a portion of a prior art FET stack 700, showing parasitic capacitances. The “top” FET, Mtop, of the FET stack 700 is coupled to an RF input voltage V_RF, and to a next sequential FET, Mnext. As should be appreciated, additional FETs may be similarly sequentially coupled to Mnext.

A conventional parallel gate bias resistor ladder 702 is shown in which a variable DC gate bias voltage Vgate is coupled to the gate of each FET Mtop, Mnext through a corresponding gate resistor Rg. Because the FETs and gate resistors are integrated devices formed on an IC substrate, there are inherent associated parasitic capacitances. In particular, each gate resistor Rg has a parallel parasitic capacitance Cp_R, and each FET includes parasitic capacitances Cp_Mbetween its gate and drain and between its gate and source. Accordingly, the gates of each FET are imperfectly isolated from the gate and source with respect to RF signals.

Using the example of FIG. 7, if V_RFis an RF voltage of 100V and the stack 700 is in the OFF state (i.e., all FETs are biased to block drain-source current flow), and if each FET Mtop, Mnext, etc. can safely withstand 3V from drain to source (further assuming that there sufficient other FETs to drop the applied RF voltage such that no one FET is subjected to more than 3V), then the source voltage for Mtop (and thus the drain voltage for Mnext) would be 97V, and the source voltage for Mnext would be 94V; additional FETs in the sequence would similarly drop 3V from drain to source. The parasitic capacitances Cp_Mwill cause imposition of an RF voltage on the gate of Mtop of about 98.5V (i.e., about one-half the difference between 100V-97V); for Mnext, the imposed gate voltage would be about 95.5V. More specifically, the gate resistor Rg for Mtop will essentially have AC ground (0V) on its Vgate side, and very high RF voltage (˜98.5V) on its other side. This causes excessive power dissipation in the gate resistor Rg for Mtop. The parallel parasitic capacitor Cp_Racross that gate resistor Rg makes the effective resistance even smaller, thereby increasing the RF power dissipation in the gate resistor Rg, which may cause device failure. A similar problem, but at increasingly lower RF voltages, occurs for each of the successive FETs Mnext in the stack 700.

FIG. 8A is a schematic equivalent circuit of a FET stack 800 with a series-connected resistor ladder gate bias scheme in accordance with one aspect of the present invention, showing parasitic capacitances. The “top” FET, Mtop, of the FET stack 800 is coupled to an RF input voltage V_RF, and to a next sequential FET, Mnext; additional FETs may be similarly sequentially coupled to Mnext. A variable DC gate bias voltage Vgate may be coupled to the gate of each FET Mtop, Mnext at nodes A, B situated after a corresponding one of a plurality of series-coupled gate resistors Rg, which thus form a series-connected gate bias resistor ladder 802. Stated another way, each gate resistor Rg is coupled to the gates of two adjacent FETs, and the series-connected gate bias resistor ladder 802 is configured to be connected to a gate bias voltage Vgate. Accordingly, in the illustrated example, for n FETs, there are n-1 gate resistors Rg (see also FIG. 8B); however, if desired, an additional gate resistor Rg can be coupled between Vgate and the gate of the “bottom” FET in the FET stack 800 (see, for example, resistor R_BFin FIG. 8B). Each FET gate will see an applied DC bias voltage of Vgate through the series connection of the gate resistors Rg of the resistor ladder 802; that is, Vgate essentially just charges or discharges each FET gate through corresponding gate resistors Rg.

Using the example values set forth above, if V_RFis an RF voltage of 100V and each FET Mtop, Mnext, etc. can safely withstand 3V from drain to source, then the source voltage for Mtop (and thus the drain voltage for Mnext) would be 97V, and the source voltage for Mnext would be 94V. When the stack 800 is in the OFF state, the parasitic capacitances Cp_Mwill enable imposition of an RF voltage on the gate of Mtop of about 98.5V; for Mnext, the imposed gate voltage would be about 95.5V. Importantly, because of the changed configuration of the series-connected gate resistors Rg of the resistor ladder 802, when the stack 800 is in the OFF state, each gate resistor Rg and its corresponding parasitic capacitance Cp_Rwill be subjected to an RF voltage of only 3V, representing the difference between the RF voltages imposed on the gates of adjacent FETs (e.g., 98.5V for the gate of Mtop, and 95.5 for the gate of Mnext). Accordingly, in these examples, while the topmost gate resistor for the FET stack 700 of FIG. 7 is subjected to an RF voltage of 98.5V across its terminals, all gate resistors of the FET stack 800 of FIG. 8 are subjected to an RF voltage of only 3V, and thus are protected from breakdown due to excessive RF voltages capacitively coupled through to the gates of associated FETs.

FIG. 8B is a schematic diagram of a positive logic FET stack 820 with a series-connected gate bias resistor ladder 802 and a series-connected drain-source resistor ladder in accordance with the present invention. The illustrated example is similar to the FET stack 400 of FIG. 4 (with optional capacitors Cd), but the gate resistors Rg are arrayed in a series-connected resistor ladder configuration 802 as in FIG. 8A, and, in addition, the resistors Rds of the drain-source resistor network are also arrayed as a series-connected resistor ladder 804 configured to be connected to a drain-source bias voltage Vdrain. More specifically, each resistor Rds is connected across the drain and source of a corresponding interior FET M1-Mn (but not across the end-cap M₀FETs, which would defeat the DC blocking state of the end-cap M₀FETs). As is the case with the series-connected gate bias resistor ladder 802, the series-connected drain-source resistor ladder 804 prevents any of the Rds resistors and FET devices from being subjected to high RF voltages V_RF. Note that DC blocking capacitors (not shown) may be coupled to Vgate and/or Vdrain as described below with respect to FIG. 8C.

In the example shown in FIG. 8B, the bias voltage Vgate is shown coupled to the “bottom” FET in the FET stack 820 at a “bottom feed” node BF through a “bottom feed” resistor R_BFat one end of the series of resistors comprising the gate bias resistor ladder 802. However, alternative connection points may be used if desired; for example, Vgate may be coupled to the series-connected gate bias resistor ladder 802 at a “middle feed” node MF, optionally through a “middle feed” resistor R_MF. As should be clear, the “middle feed” node MF need not be in the exact middle of the gate bias resistor ladder 802, but may be anywhere between the ends of the series of resistors comprising the gate bias resistor ladder 802. A “middle feed” configuration may be useful when the FET stack 820 could experience an applied RF voltage to FET at the “top” or “bottom” (in relation to FIG. 8B) of the stack 820, as may be the case if the FET stack 820 is designed for a dual-polarity series application (i.e., an RF signal can be applied to either end of the stack) rather than a shunt configuration (see also FIG. 8F below). In particular, a “middle feed” configuration can provide a reduction in power dissipation in the gate resistors Rg regardless of whether an RF voltage amplitude is applied at either end of the transistor stack. Further benefits of a “middle feed” configuration are described in U.S. patent application Ser. No. 15/289,768 referenced above.

In an optional configuration, an additional parallel-connected gate resistor ladder 805 may be included. The parallel-connected gate resistor ladder 805 comprises respective resistors Rg′ (indicated by a block symbol) coupled to the gates of the FETs in the FET stack 820. In some embodiments, a combination of a series-connected gate bias resistor ladder 802 and a parallel-connected gate resistor ladder 805 can provide reduced RF power dissipation while maintaining a low switching time constant (and therefore a high switching speed). Further benefits of a “series plus parallel” gate bias ladder configuration are described in U.S. patent application Ser. No. 15/289,768 referenced above.

FIG. 8C is a schematic diagram of a positive logic FET stack 830 with an added series-connected resistor ladder for controlling body charge, and thus “back gate” characteristics in the FETs. In this example, each FET (of any type M1-Mn, M₀) is treated as an explicit four-terminal transistor, and the body of each of the stacked four terminal FETs is configured to be connected to a body bias voltage Vbody directly or through a corresponding resistor Rb of a body charge control resistor ladder 806. As is the case with the series-connected gate bias resistor ladder 802 of FIG. 8B, the series-connected body charge control resistor ladder 806 prevents any of the resistors Rb from being subjected to high RF voltages V_RF. A series-connected body charge control resistor ladder 806 is also useful for FET stacks that draw a lot of body current, to mitigate or eliminate interference with gate voltages when high peak RF voltages are applied across the FET stack.

In an optional configuration, an additional parallel-connected gate resistor ladder (not shown, but essentially the same as the parallel gate resistor ladder 805 of FIG. 8C) may be included.

In the circuit configuration of FIG. 8C, a separate Vbody terminal is shown in the schematic diagram for flexibility, but in many applications Vbody can be tied directly to circuit ground. When Vbody is tied directly to circuit ground, all body current in the FETs M1-Mn, M₀is sourced from circuit ground (e.g., V_GS=Vbody=0V). In contrast, in a conventional FET stack of the type shown in FIG. 2, body current needs to be sourced from a negative power supply (e.g., V_GS=Vbody=−3V). Such a negative power supply is usually provided by a negative charge pump, the output of which, V_SS, will slump when high peak RF voltages are applied across the FET stack and induce significant body current.

In some embodiments, capacitors Cgate, Cdrain, and/or Cbody may be coupled as shown to the Vgate, Vdrain, and Vbody terminals, respectively, and to a reference potential, such as circuit ground. The Cgate, Cdrain, and/or Cbody capacitors, when present, serve to filter out RF voltage from DC bias voltages applied to those terminals (i.e., making Vgate, Vdrain, and/or Vbody AC grounds).

The series-connected gate bias resistor ladder 802 configuration of FIG. 8A, the series-connected drain-source resistor ladder 804 of FIG. 8B, and the series-connected body charge control resistor ladder 806 of FIG. 8C are applicable to conventional FET stacks (e.g., of the types shown in FIG. 2 or 3), as well as to FET switch stacks having one or more end-cap M₀FETs (i.e., FETs that turn OFF when their V_GSis essentially zero volts). For example, FIG. 8D is a schematic diagram of a conventional FET stack 840 with a series-connected gate bias resistor ladder 802, a series-connected drain-source resistor ladder 804, and a series-connected body charge control resistor ladder 806. In contrast to the embodiment of FIG. 8C, the “end-cap” FETs M1 and Mn are conventional FETS, additional drain-source resistors Rds' have been added to the drain-source resistor ladder 804 in order to span the drain and source of each of M1 and Mn, the optional capacitors Cd from FIG. 8C have been removed, and there is no Vdrain bias voltage. This configuration has the advantages for each series-connected resistor ladder 802, 804, 806 noted above for the series-connected gate bias resistor ladder 802, especially protection from breakdown due to excessive capacitively coupled RF voltages.

In some embodiments, the series-connected body charge control resistor ladder 806 may be replaced by a parallel-connected body charge control resistor ladder, either in a conventional FET stack or in a FET stack having one or more end-cap M₀FETs. For example, FIG. 8E is a schematic diagram of a conventional FET stack 850 with a series-connected gate bias resistor ladder 802, a series-connected drain-source resistor ladder 804, and a parallel-connected body charge control resistor ladder 808. This parallel-connected approach may prove to be advantageous if the body current for a series-connected resistor ladder configuration (as in FIG. 8D) would be high enough that the cumulative IR drop would cause the voltage on the body of the “top” FET Mn (i.e., the FET furthest from the input node for the bias voltage Vbody) to become undesirably high. The parallel-connected body charge control resistor ladder 808 configuration creates a consistent voltage drop across the body resistors Rb such that there is no additive voltage increase.

In an optional configuration, an additional parallel-connected gate resistor ladder (not shown, but essentially the same as the parallel-connected gate resistor ladder 805 of FIG. 8C) may be included. In some embodiments, the configuration of the body charge control resistor ladder may be series-connected (as in FIG. 8D) and the configuration of the gate bias resistor ladder may be parallel-connected (as in FIG. 4) or a combination of series-connected and parallel-connected (as in FIG. 8B, with the added parallel-connected gate resistor ladder 805), with benefits similar to those described above for FIG. 8E.

As should be appreciated, any combination of series-connected resistor ladders 802, 804, 806 may be used in conjunction with a FET stack, with or without adding a parallel-connected gate resistor ladder 805 or substituting a parallel-connected body charge control resistor ladder 808 for a series-connected resistor ladder 806. Examples include: a gate bias resistor ladder plus a body charge control resistor ladder; a gate bias resistor ladder plus a drain-source resistor ladder; a body charge control resistor ladder plus a drain-source resistor ladder; and a gate bias resistor ladder plus a body charge control resistor ladder plus a drain-source resistor ladder.

If more than one resistor ladder is used in a FET stack that includes end-cap M₀FETs, it may be necessary or useful to provide a non-overlapping sequencing for states changes to the Vgate, Vdrain, and Vbody voltages to help prevent “shoot through” DC current in the end-cap M₀FETs. Such current may occur because the positive-logic FETs (e.g., FETs M1-Mn in FIG. 4) have different ON-to-OFF and OFF-to-ON switching characteristics and timing compared to the essentially zero V_GSM₀FETs. For example, referring to FIG. 8C, when the FET stack is being switched from the OFF state to the ON state, it may be preferable to change Vdrain (e.g., from 3V to 0V) before changing Vgate (e.g., from 0V to 3V). Conversely, when the FET stack is being switched from the ON state to the OFF state, it may be preferable to change Vgate (e.g., from 3V to 0V) before changing Vdrain (e.g., from 0V to 3V).

Bias Ladders with AC Coupling Modules

The series-connected or series/parallel connected gate resistor ladders described above allow the gate of each FET in a switch stack to track the common mode voltage of its associated FET. In general, such gate resistor ladders must provide a high impedance relative to the impedance (capacitance) between the gate and the source/drain of the FETs in the switch stack. Despite the benefits of a series-connected gate bias resistor ladder 802 (e.g., as shown in FIG. 8A) or of a combination of series-connected gate bias resistor ladder 802 and a parallel-connected gate bias resistor ladder 805 (e.g., as shown in FIG. 8B) as described to this point, in some applications, the FET nearest an applied RF signal (e.g., the “top” FET in FIGS. 8B-8E coupled to V_RF) still has an effective RF load that can cause the gate of that FET to not fully track the transistor common mode voltage during RF operation. The RF load on the gate of the “top” FET acts as parasitic capacitance in producing non-ideal voltage division, and if not compensated, can reduce the peak breakdown voltage (BV) withstand capability of that FET by several percent.

However, the load seen by that “top” FET can be substantially mitigated or even totally eliminated by coupling an AC Coupling Gate Module 822 between an RF input terminal and the gate of the FET (through at least a gate resistor) in the stack nearest the RF input terminal. For example, in FIGS. 8B-8E, an AC Coupling Gate Module 822 is coupled between the terminal receiving a V_RFsignal and the gate of the “top” FET (Mn or M₀, as the case may be)—thus, the AC Coupling Gate Module 822 is also coupled to the “top” of the series-connected gate bias resistor ladder 802.

As another example, FIG. 8F is a schematic diagram of a conventional FET stack 860 with a series-connected gate bias resistor ladder 802 and an AC Coupling Gate Module 822. The FET stack 860 is configured to be coupled in a shunt configuration or in a series configuration. In a shunt configuration, the RF− terminal is usually circuit ground, an RF input signal is applied at the RF+ terminal, and Vgate is applied at the “bottom” of the FET stack 860 through resistor R_BF. In a series configuration, either or both of the RF+ and RF− terminals may be the source of an RF signal (e.g., RF+ may be coupled between an RF antenna and an amplifier), and Vgate would generally be applied at the “middle” of the FET stack 860 through resistor R_MF. As noted above, a “middle feed” configuration can provide a reduction in power dissipation in the gate resistors Rg regardless of whether an RF voltage amplitude is applied at either end of the FET stack 860. As should be clear, the FETs M1-Mn of the conventional FET stack 860 of FIG. 8F can be replaced by a positive logic stack of the type shown in FIG. 8B.

In some embodiments, the AC Coupling Gate Module 822 may comprise a DC blocking capacitor C1, while in other embodiments the AC Coupling Gate Module 822 may comprise a DC blocking capacitor C1 connected in series with a resistor R1 (the order of connection of C1 and R1 does not matter, whereas the order of connection does matter for Cgate and R_BFat the “bottom” of the stack for a shunt stack configuration). The AC Coupling Gate Module 822 improves voltage division along the gate bias resistor ladder 802 and allows the gate of the “top” FET to more fully track the transistor common mode voltage during RF operation. Another benefit of the AC Coupling Gate Module 822 in a series configuration is that it lets a coupled antenna be loaded directly, rather than through the FETs of the stack.

As noted above, in a series configuration, either or both of the RF+ and RF− terminals may be the source of an RF signal, and Vgate would generally be applied at the “middle” of the FET stack 860 through resistor R_MF. In such a case, it may be beneficial to couple a Coupling Gate Module between the series-connected gate bias resistor ladder 802 and both of the RF+ and RF− terminals. For example, FIG. 8G is a schematic diagram of a conventional FET stack 870 with a series-connected gate bias resistor ladder 802 and dual AC Coupling Gate Modules. The FET stack 870 of FIG. 8G is similar to the FET stack 860 of FIG. 8F, but with a “middle feed” configuration for Vgate, a first AC Coupling Gate Module 822 at the “top” of the stack nearest FET Mn, and a second AC Coupling Gate Module 822′ at the “bottom” of the stack nearest FET M1. The second AC Coupling Gate Module 822′ may comprise a DC blocking capacitor C2, while in other embodiments the second AC Coupling Gate Module 822′ may comprise a DC blocking capacitor C2 connected in series with a resistor R2. With the illustrated configuration of AC Coupling Gate Modules 822, 822′, the load seen by the FETs nearest the RF+ and R− terminals can be substantially mitigated or even totally eliminated.

Referring back to FIG. 8F, if a series-connected body charge control resistor ladder 806 is included in the FET stack 860, a similar AC Coupling Body Module 823 will provide the same benefits for the body (or “back gate”) of the “top” FET (in this example, FET Mn, nearest the RF+ terminal). In the illustrated embodiment, the AC Coupling Body Module 823 is coupled between the RF+ terminal and the series-connected body charge control resistor ladder 806 connected to the “top” FET Mn nearest the RF+ terminal. The AC Coupling Body Module 823 may comprise a DC blocking capacitor C2 in some embodiments, while in other embodiments the AC Coupling Body Module 823 may comprise a DC blocking capacitor C2 connected in series with a resistor R2 (again, the order of connection does not matter). Further, in a series configuration, a second AC Coupling Body Module (not shown) may be coupled between the RF− terminal and the series-connected body charge control resistor ladder 806 connected to the “bottom” FET M1 nearest the RF− terminal to provide similar benefits.

An AC Coupling Gate Module and an AC Coupling Body Module may be used independently of each other, or may be used together. In general, when using a series-connected gate bias resistor ladder 802 and/or a series-connected body charge control resistor ladder 806, there are significant benefits to using an AC Coupling Gate and/or Body Module between the respective ladders 802, 806 and any RF terminal presenting an RF load, in order to mitigate or even totally eliminate an RF load across the FET coupled to that RF terminal.

In some embodiments, a parallel-connected gate bias ladder 805 may be included with the values of the resistors Rg' being selected to isolate for a different voltage division in the gate bias resistor ladders versus the component FETs M1-Mn of the FET stack 860. More particularly, if the voltage division across the FET stack 860 is uniform, then constant Rg values for a series-connected gate bias resistor ladder 802 (i.e., a “rail” only configuration) in conjunction with an AC Coupling Gate Module 822 completely eliminates the RF load on the FETs since the voltage division across the gate bias resistor ladder is uniform. On the other hand, if there is non-ideal voltage division across the FET stack 860, a mismatch occurs between the voltage division across the FETs and the voltage division across the rail-only gate bias resistor ladder. This can be remedied by including a parallel-connected gate bias ladder 805 (i.e., adding “rungs” to the “rails” of the series-connected gate bias resistor ladder 802). Adding rung resistors Rg' helps reduce the RF load due to non-ideal voltage division across the FET stack 860, with minimal switching time constant penalty.

In some gate bias ladder embodiments having a series-connected gate bias resistor ladder 802 (a “rail” configuration) and a parallel-connected gate bias ladder 805 (a “rung” configuration), there is a benefit to having variable values for the resistors of either or both of the “rail” and “rung” bias resistor ladders 802, 805 (as opposed to constant resistance values). In general, the variation should be tapered from the top of the FET stack to the bottom; that is, the resistor values in one or both of the bias resistor ladders 802, 805 should be higher near the top, tapering to lower at the bottom. For example, compared to constant value rail and rung resistors, there is significant improvement in peak breakdown voltage (BV) for the top-most transistor (nearest the RF signal input) when the rail resistors are variable and the rung resistors are constant, while retaining similar switching time and power dissipation characteristics. In addition, a “variable rail/constant rung” gate bias resistor ladder configuration allows the size of the rung resistors to be much smaller than with other configurations, enabling greater flexibility in designing IC layouts. Similar benefits may be seen in embodiments using a “variable rail/variable rung” gate bias resistor ladder configuration. Note that variable rail resistor values may be adjusted to achieve a desired relationship of (1) the RF load on the FET gates to (2) the peak BV for the top-most transistor. However, there is a tradeoff with the switching time constant.

Note that when the FET stack 860 is coupled to an antenna or the like, then the resistance of R1 is preferably set to one-half of the resistance of the series-connected resistors Rg (i.e., R1=½Rg), since the gate of the “top” FET sees only one-half the voltage below the antenna compared to the voltage across each other FET.

Notably, the inclusion of the AC Coupling Gate Module 822 and/or the AC Coupling Body Module 823 has essentially no adverse effect on the performance characteristics of the FET stack 860 (e.g., in terms of switching time constant, resistor power dissipation, resistive voltage drop through body resistors due to body current, etc.). On the other hand, the inclusion of one or more of such modules 822, 823 substantially eliminates the reduction in the peak breakdown voltage (BV) withstand capability of the “top” FET of the FET stack that would otherwise occur. As one specific example, using modeled circuits to compare (1) a FET stack configuration using a series-connected gate bias resistor ladder 802 but no AC Coupling Gate Module 822 against (2) a FET stack configuration using a series-connected gate bias resistor ladder 802 and an AC Coupling Gate Module 822, the former configuration showed a decrease in BV withstand capability of the “top” FET of about 0.714, while the latter configuration showed a decrease in BV withstand capability of the “top” FET of about 0.001—a factor of over 700 in improvement due to the AC Coupling Gate Module 822.

Note that in a series configuration for the FET stack 860, where either or both of the RF+ and RF− terminals may be the source of an RF signal, an AC Coupling Gate Module 822 may be coupled between a terminal RF+, RF− and a respective end of the series-connected gate bias resistor ladder 802 for the FET stack 860. In such a case, Vgate would normally be applied to the FET stack 860 using a “middle feed” configuration. Similarly, an AC Coupling Body Module 823 may be coupled to each end of the body charge control resistor ladder 806 for the FET stack 860.

Accumulated Charge Sink Structure

Embodiments of the invention, including the embodiments described above, that are fabricated using silicon-on-insulator (SOI)—including silicon-on-sapphire (SOS) MOSFETs—may benefit by adding an accumulated charge sink (ACS) structure to one or more constituent FETs (i.e., M1-Mn and/or M₀). In particular, the linearity of an SOI MOSFET can be improved by providing a means for sweeping out accumulated charge trapped below the gate oxide of the MOSFET, such as by use of the “HaRP”™ accumulated charge sink (ACS) technology taught in U.S. Pat. No. 7,910,993, issued Mar. 22, 2011, entitled “Method and Apparatus for use in Improving Linearity of MOSFETs Using an Accumulated Charge Sink”, which is hereby incorporated by reference. An “accumulated charge”, as defined in more detail in U.S. Pat. No. 7,910,993 and as used herein, refers to gate-bias induced carriers that may accumulate in the body of an OFF-state MOSFET, even if the majority carriers in the body do not have the same polarity as the accumulated charge.

More particularly, as described in greater detail in U.S. Pat. No. 7,910,993, no matter what mode of operation an SOI MOSFET employs (i.e., whether enhancement or depletion mode), when the MOSFET is operated in an OFF-state (i.e., the gate voltage does not exceed V_th), and when a sufficient nonzero gate bias voltage is applied with respect to the MOSFET source and drain, an “accumulated charge” may occur under the MOSFET gate which adversely affects the linearity and other aspects of the performance of the MOSFET. To alleviate the effects of such accumulated charge, an SOI MOSFET may include an ACS structure that allows discharge of accumulated charge when the MOSFET is in a non-conducting (OFF) mode while allowing normal operation when the MOSFET is in a conducting (ON) mode.

FIG. 8H is a simplified schematic diagram of an SOI MOSFET 810 that includes an ACS structure along with conventional drain D, source S, and gate G terminals and a gate resistor Rg. In this particular illustrated example, the ACS structure comprises a diode 812 coupled from the body of the MOSFET 810 to the gate G of the MOSFET 810. The diode 812 discharges accumulated charge from the body of the MOSFET 810 through the gate G when the MOSFET 810 is in a non-conducting (OFF) mode, while allowing normal operation when the MOSFET 810 is in a conducting (ON) mode. Alternative ACS structure circuits and methods for reducing accumulated charge in floating body semiconductor devices are described in greater detail in U.S. Pat. No. 7,910,993 referenced above. The MOSFET 810 along with an ACS structure (e.g., a body-to-gate diode 812) may also be referred to as an “ACS FET”. As should be clear, in an SOI MOSFET stack comprising one or more series-coupled positive-logic MOSFETs M1-Mn (i.e., FETs not requiring a negative voltage supply to turn OFF), coupled to one or more series-coupled “end-cap” M₀MOSFETs, one or more of the MOSFETs may be ACS FETs.

Methods

Note that in specifying a particular circuit embodiment having the architecture and characteristics of the example circuits described above, the principal of “superposition” may be used as a method for optimizing DC biasing and best AC voltage handling configuration independently, and then combining the results. That is, one can first define an optimum circuit configuration independently for AC behavior and DC behavior, and then overlay and merge the two solutions. Mathematically, superposition may be expressed as f(DC+AC)=f(DC)+f(AC), where “DC” is the DC behavior of the circuit, and “AC” is the AC behavior of the circuit.

Another aspect of the invention includes methods for providing a FET switch stack. For example, FIG. 9 is a process flow diagram 900 showing one method for providing a FET switch stack. The method includes: providing one or more series-coupled positive-logic FETs (STEP 902); and providing a first end-cap FET of a type that turns OFF when the V_GSof such end-cap FET is essentially zero volts, series-coupled to a first end of the one or more series-coupled positive-logic FETs (STEP 904).

Additional aspects of the method of FIG. 9 may include one or more of the following: providing a second end-cap FET of a type that turns OFF when the VGS of such end-cap FET is essentially zero volts, series-coupled to a second end of the one or more series-coupled positive-logic FETs; further including series coupling, to the FET switch stack, at least one additional FET of the type that turns OFF when the VGS of such FET is essentially zero volts; wherein each end-cap FET functions as a DC blocking capacitor when in an OFF state, and as a resistive signal path when in an ON state; further including coupling at least one capacitor between the source and the drain of a corresponding end-cap FET; further including providing a gate bias resistor ladder including a plurality of series-coupled resistors configured to be coupled to a gate bias voltage, wherein each resistor is coupled to the respective gates of corresponding adjacent FETs; further including a capacitor coupled between the gate bias resistor ladder and a reference potential; further including coupling an AC coupling gate module to at least one end of the gate bias resistor ladder and configuring the AC coupling gate module to be coupled to a radio frequency voltage source; wherein the AC coupling gate module includes one of a capacitor or a capacitor series coupled to a resistor; further including providing a body charge control resistor ladder including a plurality of series-coupled or parallel-coupled resistors configured to be coupled to a body bias voltage, wherein each resistor is coupled to the body of at least one corresponding FET; further including a capacitor coupled between the body charge control resistor ladder and a reference potential; further including coupling an AC coupling body module to at least one end of the body charge control resistor ladder, the AC coupling body module configured to be coupled to a radio frequency voltage source; wherein the AC coupling body module includes one of a capacitor or a capacitor series coupled to a resistor; further including providing a drain-source resistor ladder including a plurality of series-coupled resistors configured to be coupled to a drain-source bias voltage, wherein each resistor is coupled to the respective drains and sources of corresponding adjacent positive-logic FETs; further including coupling a negative gate bias voltage supply to the gates of the end-cap FETs; and wherein at least one FET is an ACS FET.