₂) and a second sublayer with a dielectric constant less than 4.0 (e.g., PBO). In some embodiments, a sublayer of the dielectric layer 71 may include a material that is a same material as that used in the encapsulation layer 70.

Referring to FIG. 13, a removing operation is performed to thin the dielectric layer 71 until the tops of the connectors 30d, the emitter structures 40 and the ground structures 50 are exposed. The removing operation can be accomplished by grinding (e.g., CMP), etching back, or scraper. The grinding leaves the top ends of the emitter structures 40 and the ground structures 50, to be substantially level or coplanar with the top surface of the remaining dielectric layer. Some metal residues such as metal particles may remain after the grinding operation. Accordingly, after the grinding operation, a cleaning may be performed, for example, through a wet etching, to remove the metal residues. The remaining dielectric layer forms multiple dielectric bulks 72, and one dielectric bulk 72 is provided between each emitter structure 40 and the adjacent ground structure 50. In some embodiments, multiple antenna structures AS are accordingly formed after the formation of the dielectric bulks 72, and each antenna structure AS includes one dielectric bulk 72 interposed between two adjacent emitter structure 40 and ground structure 50.

In some embodiments, a curing and hardening process is performed to the dielectric layer 71 before the removing operation with CMP in FIG. 13. However, the disclosure is not limited thereto. In other embodiments, a curing and hardening process is performed to the dielectric layer 71 after the removing operation with scraper in FIG. 13. In some embodiments, the curing and hardening process is performed at a temperature of 300° C. or less.

Existing antennas are usually disposed on a printed circuit board (PCB) with a large area for the emitter plane or the ground plane. As a result, the capacitance effect becomes more pronounced at high transmission frequencies, e.g., transmission frequencies in the range of tens of GHz. Such inevitable capacitance effect adversely impacts the antenna performance. Moreover, the existing antenna designs adopt a dielectric material of a relatively low dielectric constant as the insulating layer between the pair of conductive plates. The resulting antenna performance can achieve a return loss of about −10 dB. In contrast, the proposed dielectric layer 71 of a high-k dielectric material that is embedded in a molding compound of a package device causes generation of a greater electric field between the pair of the conductive plates. Moreover, the high-k material leads to a reduced capacitance effect and an improved return loss of −30 dB or better. In addition, the impedance matching circuit can be tuned more easily to achieve better transmission performance.

Referring to FIG. 14 to FIG. 18, a redistribution layer (RDL) structure 400 is formed over and electrically connected to the semiconductor die 30, the emitter structures 40 and the ground structures 50. The redistribution layer structure 400 is referred to as a “top-side or front-side redistribution layer structure” in some examples.

As shown in FIG. 14 to FIG. 15, a first-level conductive line 412 is formed. In some embodiments, a metal layer 411 (e.g. copper) is formed over the top surface of the structure of FIG. 13 by plating, which may be electro plating or electro-less plating. Next, the metal layer 411 is patterned and etched, leaving behind the first-level conductive line 412 over the ground structures 50 and the connectors 30d of the semiconductor die 30. Then, a dielectric layer 413 (e.g. PBO) is applied over the resulting structure. This structure is shown in FIG. 15.

Referring to FIG. 16, the dielectric layer 413 is patterned to form via openings which are then filled with conductor metal (e.g. copper) to form the first-level conductive vias 415. The first-level redistribution layer 410 is thus completed.

As shown in FIG. 16 to FIG. 17, a second-level redistribution layer 420 is formed on the first-level redistribution layer 410. In some embodiments, a layer of conductor metal (e.g. copper) is deposited over the first-level redistribution layer 410 then patterned and etched, leaving behind the second-level conductive line 422 over the first-level redistribution layer 410. A dielectric layer 416 (e.g. PBO) is then applied over the resulting structure. This structure is shown in FIG. 16.

Thereafter, as shown in FIG. 17, the dielectric layer 416 is patterned to form via openings which are then filled with conductor metal (e.g. copper) to form second-level conductive vias 425. The second-level redistribution layer 420 is thus completed.

As shown in FIG. 17 and FIG. 18, a third-level redistribution layer 430 is formed on the second-level redistribution layer 420. In some embodiments, a layer of conductor metal (e.g. copper) is deposited over the second-level redistribution layer 420 then patterned and etched, leaving behind the third-level conductive line 432 over the second-level redistribution layer 420. A dielectric layer 426 (e.g. PBO) is then applied over the resulting structure. This structure is shown in FIG. 17.

Thereafter, as shown in FIG. 18, the dielectric layer 426 is patterned to form openings for under ball metal (UBM) pads which are then filled with conductor metal (e.g. copper) to form the UBM pads 435. The third-level redistribution layer 430 is thus completed. This structure is shown in FIG. 18.

FIG. 19 further shows the formation of the next level electrical connectors in accordance with some embodiments. In this embodiment, the electrical connectors are bumps 600 attached to the exposed portions of the UBM pads 435. In some embodiments, the bumps 600 can be formed by placing solder balls on the UBM pads 435 and then reflowing the solder balls. In other embodiments, the formation of the bumps 600 includes performing a plating operation to form solder regions over the UBM pads 435, and then reflowing the solder regions. In other embodiments, the bumps 600 can be metal pillars, or metal pillars with solder caps, which may also be formed through plating. In some embodiments, the bumps 600 include bumps 600A electrically connected to the ground structures 50, and bumps 600B electrically connected to the emitter structures 40 and the semiconductor chip 30.

In some embodiments, the first-level conductive line 412, the first-level conductive vias 415, the second-level conductive line 422, the second-level conductive vias 425, the third-level conductive line 432, and the UBM pads 435 can include a metal or a metal alloy including Cu, Al, W, Ni, or an alloy thereof. In some embodiments, the above metal features are formed separately, so there is an interface between the two adjacent metal features. However, the disclosure is not limited thereto. In some embodiments, some adjacent metal features (e.g., 422 and 415, 425 and 422) are formed integrally without an interface therebetween.

In some embodiments, the dielectric layers 413, 416, and 426 include a polymer such as polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or the like. Alternatively, the dielectric layers 413, 416, and 426 may include non-organic dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like. In the embodiments, In some embodiments, each of the dielectric layers has a dielectric constant (k) less than 3.5, such as from 2.8 to 3.0.

Referring to FIG. 19, the semiconductor package of FIG. 18 is debonded from the carrier 10. The debonding layer 12 is also cleaned from the semiconductor package. The resulting final semiconductor package 1 is shown in FIG. 19. The dotted arrows in FIG. 19 indicate the paths P for electromagnetic waves, which will be described later. In some embodiments, the buffer layer 20 acts as the final protective insulator for the finished semiconductor package 1. However, the disclosure is not limited thereto. In other embodiments, a board substrate (e.g., PCB) is formed below the semiconductor package 1 and electrically connected to the semiconductor die 30 with bumps penetrating through the back-side buffer layer 20.

In the above embodiments, upon the operation of forming antenna cavities C in FIG. 11, no encapsulation layer remains within the antenna cavities C, so the antenna cavities C are then all filled with the high-k dielectric bulk 72. However, the disclosure is not limited thereto. In other embodiments, upon the operation of forming antenna cavities C in FIG. 11, some encapsulation residues 70a remain within the antenna cavities C, so the dielectric bulk is formed within the antenna cavities C and over the encapsulation residues 70a, as shown in the semiconductor package 2 of FIG. 20. In some embodiments, the interface between the encapsulation residues 70a and the dielectric layer 72 is non-smooth and rough. Accordingly, in some embodiments, the antenna structure AS1 of the semiconductor package 2 includes an emitter structure 40, a ground structure 50, a dielectric bulk 72 between the emitter structure 40 and the ground structure 50, and encapsulation residues 70a between the dielectric bulk 72 and each of the emitter structure 40 and the ground structure 50. The encapsulation residues 70a are regarded as part of dielectric bulk 72 in some examples.

The above embodiments in which the dielectric layer 72 is a single-layer structure is provided for illustration purposes, and are not construed as limiting the present disclosure. In other embodiments, the dielectric layer 72 is a multi-layer structure, as shown in the semiconductor package 3 of FIG. 21. In some embodiments, the dielectric layer 72 includes two layers (e.g., 72a and 72b), three layers or more layers with different dielectric constants. In some embodiments, one of the two layers 72a and 72b has a dielectric constant less than 4, and the other of the two layers 72a and 72b has a dielectric constant greater than 10. In some embodiments, each of the two layers 72a and 72b has a dielectric constant greater than 10. Accordingly, in some embodiments, the antenna structure AS2 of the semiconductor package 3 includes an emitter structure 40, a ground structure 50, and two layers 72a and 72b between the emitter structure 40 and the ground structure 50. In some embodiments, encapsulation residues 70a are further included between the dielectric bulk 72 (including two layers 72a and 72b) and each of the emitter structure 40 and the ground structure 50.

FIGS. 22-26 illustrate various simplified top views of semiconductor packages in accordance with some embodiments. For simplicity and clarity of illustration, only few elements are shown in the top views of FIGS. 22-26, and these elements are not necessarily in the same plane.

As shown in FIG. 22, there are four antenna structures at four sides of the semiconductor die 30. Specifically, an emitter structure 40 and a ground structure 50 are configured as a pair of plates of an antenna structure at one side of the semiconductor die 30, with a dielectric bulk 72 therebetween serving as the resonance cavity and insulator thereof. In some embodiments, the emitter structure 40 is shaped as a conductive wall substantially parallel to the sidewall of the semiconductor chip 30, and the ground structure 50 is shaped as multiple conductive pillars 51 with gaps 52 therebetween. In some embodiments, the width of the conductive pillars 51 or the gaps 52 is constant. However, the disclosure is not limited thereto. In other embodiments, the width of the conductive pillars 51 or the gaps 52 is varied upon the process requirements. The dielectric bulk 72 is referred to as an “antenna oscillation cavity” or “antenna resonance cavity” in some examples. As shown by the dotted arrows in FIG. 22, when the electromagnetic waves resonate within the resonance cavity, i.e., dielectric bulk 72, and radiate laterally along the paths P from the emitter structure 70 through gaps 51 of the ground structure 50. Similarly, three more antenna structures are arranged at other sides of the semiconductor die 30. Such configuration forms a four-branch antenna to provide enhanced radiation performance.

In the embodiment of FIG. 22, four antenna structures are provided at four sides of the semiconductor die 30. However, the disclosure is not limited by the disclosure. The number of the antenna structures may be adjusted upon the process requirements. In some embodiments, the number of the antenna structure(s) is 2ⁿ, and n is zero or a positive integer.

In some embodiments, as shown in FIG. 23, only one antenna structure is provided at one side of the semiconductor die 30.

In some embodiments, as shown in FIG. 24, two antenna structures are provided at opposite sides of the semiconductor die 30. Such configuration forms a two-branch antenna to provide enhanced radiation performance.