The common circuit CMC may include one or more sub-common circuits SCC. The sub-common circuits SCC may be arranged in a line in the non-display area NDA in the second direction DR2. Each of the sub-common circuits SCC may be commonly connected to a horizontal line of pixels PX. For example, referring to FIG. 2, the common circuit CMC may include five sub-common circuits SCC, e.g., first through fifth sub-common circuits SCC that are sequentially arranged in the opposite direction of the second direction DR2, the first sub-common circuit SCC may be commonly connected to six pixels PX that are aligned next to the first sub-common circuit SCC in the first direction DR1, the second sub-common circuit SCC may be commonly connected to six pixels PX that are aligned next to the second sub-common circuit SCC in the first direction DR1, the third sub-common circuit SCC may be commonly connected to six pixels PX that are aligned next to the third sub-common circuit SCC in the first direction DR1, the fourth sub-common circuit SCC may be commonly connected to six pixels PX that are aligned next to the fourth sub-common circuit SCC in the first direction DR1, and the fifth sub-common circuit SCC may be commonly connected to six pixels PX that are aligned next to the fifth sub-common circuit SCC in the first direction DR1.

FIG. 3 is a circuit diagram illustrating an example pixel PX of FIG. 2 and a sub-common circuit SCC connected to the corresponding pixel PX.

Referring to FIG. 3, the pixel PX may include a driving transistor Td, a switching transistor Ts, a first capacitor C1, a second capacitor C2, and a light-emitting element ED.

The driving transistor Td may include a gate electrode, a source electrode, a drain electrode, and a body electrode. The driving transistor Td may control a source-drain current (hereafter, the driving current) based on a data voltage applied to the gate electrode. The driving current flowing through the channel region of the driving transistor Td may be proportional to the square of the difference between a threshold voltage and the voltage between the source electrode and the gate electrode. The gate electrode of the driving transistor Td may be electrically connected to a first node N1, the source electrode of the driving transistor Td may be electrically connected to a second node N2, the drain electrode of the driving transistor Td may be electrically connected to a third node N3, and the body electrode of the driving transistor Td may be electrically connected to a driving voltage line VDL, which transmits a driving voltage VDD.

The light-emitting element ED may emit light upon receiving the driving current. The luminance or brightness of the light-emitting element ED may be proportional to the magnitude of the driving current. The light-emitting element ED may be an organic light-emitting diode (OLED) including a first electrode (e.g., an anode), a second electrode (e.g., a cathode), and an organic luminescent layer positioned between the first and second electrodes. As another example, the light-emitting element ED may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor positioned between the first and second electrodes. As yet another example, the light-emitting element ED may be a quantum-dot light-emitting element including a first electrode, a second electrode, and a quantum-dot luminescent layer positioned between the first and second electrodes. As still another example, the light-emitting element ED may be a micro-light-emitting diode (micro-LED). The first electrode of the light-emitting element ED may be electrically connected to the third node N3. The second electrode of the light-emitting element ED may be electrically connected to a common voltage line VSL, which transmits a common voltage VSS.

The switching transistor Ts may be turned on by a write gate signal GW from a write gate line GWL, thereby electrically connecting the data line DL and the first node N1. The gate electrode of the switching transistor Ts may be electrically connected to the write gate line GWL, the source electrode of the switching transistor Ts may be electrically connected to the data line DL, the drain electrode of the switching transistor Ts may be electrically connected to the first node N1, and the body electrode of the switching transistor Ts may be electrically connected to the driving voltage line VDL. The data line DL may transmit a data voltage (“Vdt” of FIG. 4) or a reference voltage (“Vref” of FIG. 4).

The first capacitor C1 may be electrically connected between the first and second nodes N1 and N2. For example, the first electrode of the first capacitor C1 may be electrically connected to the first node N1, and the second electrode of the first capacitor C1 may be electrically connected to the second node N2.

The second capacitor C2 may be electrically connected between the second node N2 and the driving voltage line VDL. For example, the first electrode of the second capacitor C2 may be electrically connected to the second node N2, and the second electrode of the second capacitor C2 may be electrically connected to the driving voltage line VDL.

The sub-common circuit SCC may include an initialization transistor Ti.

The initialization transistor Ti may be turned on by an initialization gate signal GI from an initialization gate line GIL, thereby electrically connecting the third node N3 and the common voltage line VSL. The gate electrode of the initialization transistor Ti may be electrically connected to the initialization gate line GIL, the source electrode of the initialization transistor Ti may be electrically connected to the third node N3, the drain electrode of the initialization transistor Ti may be electrically connected to the common voltage line VSL, and the body electrode of the initialization transistor Ti may be electrically connected to the driving voltage line VDL.

The third node N3 may be connected to a common line CL. In other words, the third nodes N3 of a horizontal line of pixels PX including the pixel PX of FIG. 3 may be commonly connected to the common line CL.

In one embodiment, as the horizontal line of each of the pixels PX may share one sub-common circuit SCC, some transistors (e.g., the initialization transistor Ti) can be removed from each of the pixels PX. As a result, the size of each pixel PX can be reduced, enabling the implementation of fine pixels.

FIG. 4 is a schematic timing diagram illustrating an emission signal EM, the write gate signal GW, the initialization gate signal GI, the reference voltage Vref, and the data voltage Vdt of FIG. 3.

Referring to FIG. 4, the display device 10 may operate based on an initialization period P1, a threshold voltage detection period P2, a data write period P3, and an emission period P4.

During each of the initialization period P1, the threshold voltage detection period P2, the data write period P3, and the emission period P4, the emission signal EM, the write gate signal GW, and the initialization gate signal GI may have an active level or a non-active level. Here, the active level may refer to a voltage or level that can turn on a transistor. In other words, a signal with the active level may have a voltage greater than the threshold voltage of a corresponding transistor. For example, referring to FIG. 3, in case that the driving transistor Td, the switching transistor Ts, and the initialization transistor Ti are P-type transistors, the active level of each signal for the driving transistor Td, the switching transistor Ts, and the initialization transistor Ti may mean a low level (e.g., a negative level or a low voltage level).

The non-active level may refer to a voltage or level that can turn off a transistor (e.g., an off-stage voltage). For example, a signal with the non-active level may have a voltage smaller than the threshold voltage of a corresponding transistor. In an embodiment, referring to FIG. 3, in case that the driving transistor Td, the switching transistor Ts, and the initialization transistor Ti are P-type transistors, the non-active level of each signal for the driving transistor Td, the switching transistor Ts, and the initialization transistor Ti may mean a high level (e.g., a positive level or a high voltage level).

As another example, in case that the driving transistor Td, the switching transistor Ts, and the initialization transistor Ti are N-type transistors, the active level of each signal may mean a high level (e.g., a positive level or a high voltage level), and the non-active level of each signal may mean a low level (e.g., a negative level or a low voltage level).

During the initialization period P1, each of the emission signal EM, the write gate signal GW, and the initialization gate signal GI may have the active level. During the initialization period P1, the write gate signal GW may have the non-active level for some time before the end of the initialization period P1 (e.g., before the transition of the emission signal EM from the active level to the non-active level). During the initialization period P1, the reference voltage Vref may be applied to the data line DL.

During the threshold voltage detection period P2, the initialization gate signal GI may have the active level, and each of the emission signal EM and the write gate signal GW may have the non-active level. During the threshold voltage detection period P2, the reference voltage Vref may be applied to the data line DL. The data voltage Vdt may be applied to the data line DL for some time before the end of the threshold voltage detection period P2 (e.g., before the transition of the write gate signal GW from the non-active level to the active level).

During the data write period P3, each of the write gate signal GW and the initialization gate signal GI may have the active level, and the emission signal EM may have the non-active level. The write gate signal GW may have the non-active level for some time before the end of the data write period P3 (e.g., before the transition of the emission signal EM from the non-active level to the active level). During the data write period P3, the data voltage Vdt may be applied to the data line DL. Here, the data voltage Vdt may be a voltage with a gray level (or luminance) for displaying an image. For some time before the end of the data write period P3 (e.g., before the transition of the emission signal EM from the non-active level to the active level), the reference voltage Vref may be applied to the data line DL.

During the emission period P4, the emission signal EM may have the active level, and each of the write gate signal GW and the initialization gate signal GI may have the non-active level. The initialization gate signal GI may have the active level for some time after the beginning of the emission period P4 (e.g., after the transition of the emission signal EM from the non-active level to the active level). During the emission period P4, the reference voltage Vref may be applied to the data line DL.

The reference voltage Vref, the driving voltage VDD, and the common voltage VSS may be DC voltages. The reference voltage Vref may be smaller than the driving voltage VDD and larger than the common voltage VSS.

Operations of the display device 10 will hereinafter be described with reference to FIGS. 5 through 8. Referring to FIGS. 5 through 8, transistors circled with dotted lines are transistors in a turned-on state, and transistors not circled with dotted lines are transistors in a turned-off state.

The operation of the display device 10 during the initialization period P1 will hereinafter be described with reference to FIGS. 4 and 5.

FIG. 5 is a schematic diagram of an equivalent circuit illustrating the operation of the display device 10 of FIG. 3 during the initialization period P1 of FIG. 4.

Referring to FIGS. 4 and 5, each of the emission signal EM, the write gate signal GW, and the initialization gate signal GI may have the active level. The write gate signal GW may have the non-active level for some time before the end of the initialization period P1 (e.g., before the transition of the emission signal EM from the active level to the non-active level). During the initialization period P1, the reference voltage Vref may be applied to the data line DL.

The emission signal EM with the active level may be applied to the gate electrode of an emission control transistor Te through an emission line EML. As a result, the emission control transistor Te may be turned on.

The write gate signal GW with the active level may be applied to the gate electrode of the switching transistor Ts through the write gate line GWL. As a result, the switching transistor Ts may be turned on.

The initialization gate signal GI with the active level may be applied to the gate electrode of the initialization transistor Ti through the initialization gate line GIL. As a result, the initialization transistor Ti may be turned on.

During the initialization period P1, as the switching transistor Ts is turned on, the driving transistor Td may also be turned on. For example, the reference voltage Vref from the data line DL may be applied to the gate electrode of the driving transistor Td through the turned-on switching transistor Ts. Since the reference voltage Vref is smaller than the driving voltage VDD, which is applied to the source electrode (i.e., the second node N2) of the driving transistor Td, the driving transistor Td may be turned on. In response to the driving transistor Td being turned on, the drain electrode (i.e., the third node N3) of the driving transistor Td may have a value corresponding to the driving voltage VDD.

During the initialization period P1, as the switching transistor Ts, the initialization transistor Ti, and the emission control transistor Te are turned on, the gate electrode (i.e., the first node N1), the source electrode (i.e., the second node N2), and the drain electrode (i.e., the third node N3) of the driving transistor Td may be initialized. For example, the reference voltage Vref from the data line DL may be applied to the first node N1, which is the gate electrode of the driving transistor Td, through the turned-on switching transistor Ts. The driving voltage VDD from the driving voltage line VDL may be applied to the second node N2, which is the source electrode of the driving transistor Td, through the turned-on emission control transistor Te. The common voltage VSS from the common voltage line VSL may be applied to the third node N3, which is the drain electrode of the driving transistor Td, through the turned-on initialization transistor Ti. Consequently, the voltages of the gate electrode, the source electrode, and the drain electrode of the driving transistor Td may be initialized. Specifically, the gate electrode of the driving transistor Td may be initialized by the reference voltage Vref, the source electrode of the driving transistor Td may be initialized by the driving voltage VDD, and the drain electrode of the driving transistor Td may be initialized by the common voltage VSS. Furthermore, as the common voltage VSS is applied to both the first and second electrodes of the light-emitting element ED, the voltage across both ends of the light-emitting element ED during the initialization period P1 may be smaller than its threshold voltage. Therefore, the light-emitting element ED may remain off during the initialization period P1.

An operation of the display device 10 during the threshold voltage detection period P2 will hereinafter be described with reference to FIGS. 4 and 6.

FIG. 6 is a schematic diagram of an equivalent circuit illustrating an operation of the display device 10 during the threshold voltage detection period P2 of FIG. 4.

Referring to FIGS. 4 and 6, during the threshold voltage detection period P2, the initialization gate signal GI may have the active level, and each of the emission signal EM and the write gate signal GW may have the non-active level. During the threshold voltage detection period P2, the reference voltage Vref may be applied to the data line DL. For some period before the end of the threshold voltage detection period P2 (e.g., before the transition of the write gate signal GW from the non-active level to the active level), the data voltage Vdt may be applied to the data line DL.

The initialization gate signal GI with the active level may be applied to the gate electrode of the initialization transistor Ti through the initialization gate line GIL. As a result, the initialization transistor Ti may be turned on.

The emission signal EM with the non-active level may be applied to the gate electrode of the emission control transistor Te through the emission line EML. As a result, the emission control transistor Te may be turned off.

The write gate signal GW with the non-active level may be applied to the gate electrode of the switching transistor Ts through the write gate line GWL. As a result, the switching transistor Ts may be turned off. As the switching transistor Ts is turned off, the first node N1 may remain in a floating state.

During the threshold voltage detection period P2, the driving transistor may remain in the turned-on state due to the reference voltage Vref and the driving voltage VDD applied to the first and second nodes N1 and N2, respectively, previously (e.g., during the initialization period P1).

In case that the emission control transistor Te, the driving transistor Td, and the initialization transistor Ti are turned on, the driving current may flow from the driving voltage line VDL to the common voltage line VSL. The driving current may cause the voltage of the second node N2 (i.e., the voltage of the source electrode of the driving transistor Td) to fluctuate in a decreasing manner. Due to the fluctuation of the voltage of the second node N2 and the coupling of the first capacitor C1, the voltage of the first node N1 (i.e., the voltage of the gate electrode of the driving transistor Td) may also fluctuate. Therefore, a gate-source voltage of the driving transistor Td may remain constant. However, while the voltage of the body electrode of that driving transistor Td, i.e., the driving voltage VDD, remains constant, the voltage of the second node N2 fluctuates, and as a result, the absolute value of a threshold voltage Vth of the driving transistor Td shifts in an increasing manner. For example, the threshold voltage Vth of the driving transistor Td may increase in a negative direction. In case that the threshold voltage Vth of the driving transistor Td gradually increases to become substantially equal to the gate-source voltage, the driving transistor Td is turned off, and its voltage at the corresponding moment may be stored by the first capacitor C1. In other words, the threshold voltage Vth of the driving transistor Td may be detected by the first capacitor C1. Accordingly, in case that the driving transistor Td is turned off during the threshold voltage detection period P2, the threshold voltage Vth of the driving transistor Td may be stored in the first capacitor C1.

Thus, during the threshold voltage detection period P2, the threshold voltage Vth of the driving transistor Td may be detected and maintained by the first capacitor C1.

During the threshold voltage detection period P2, since the voltage across both ends of the light-emitting element ED is maintained at the same voltage (e.g., at the common voltage VSS), the light-emitting element ED may remain off.

An operation of the display device 10 during the data write period P3 will hereinafter be described with reference to FIGS. 4 and 7.

FIG. 7 is a schematic diagram of an equivalent circuit illustrating the operation of the display device 10 of FIG. 3 during the data write period P3 of FIG. 4.

Referring to FIGS. 4 and 7, during the data write period P3, each of the write gate signal GW and the initialization gate signal GI may have the active level, and the emission signal EM may have the non-active level. This write gate signal GW may have the non-active level for some time before the end of the data write period P3 (e.g., before the transition of the emission signal EM from the non-active level to the active level). During the data write period P3, the data voltage Vdt may be applied to the data line DL. Here, the data voltage Vdt may be a voltage with a particular gray level (or brightness) for displaying an image. The reference voltage Vref may be applied to the data line DL for some time before the end of the data write period P3 (e.g., before the transition of the emission signal EM from the non-active level to the active level).

The write gate signal GW with the active level may be applied to the gate electrode of the switching transistor Ts through the write gate line GWL. As a result, the switching transistor Ts may be turned on.

The initialization gate signal GI with the active level may be applied to the gate electrode of the initialization transistor Ti through the initialization gate line GIL. As a result, the initialization transistor Ti may be turned on.

The emission signal EM with the non-active level may be applied to the gate electrode of the emission control transistor Te through the emission line EML. As a result, the emission control transistor Te may be turned off.

As illustrated in FIG. 7, the data voltage Vdt may be applied to the first node N1 through the data line DL and the turned-on switching transistor Ts. Here, in case that the driving transistor Td, which was turned off during a previous data write period P