CROSS-REFERENCE TO RELATED APPLICATION(S)

The present application claims priority to U.S. Provisional Patent Application No. 63/530,127, filed Aug. 1, 2023, the disclosure of which is incorporated herein by reference in its entirety.

This application contains subject matter related to provisional U.S. Patent Application No. 63/530,132, filed Aug. 1, 2023, titled “APPARATUS WITH THINNING-BASED ALIGNMENT MARK AND METHODS OF MANUFACTURING THE SAME.” The related application is assigned to Micron Technology, Inc., and the subject matter thereof is incorporated herein by reference thereto.

TECHNICAL FIELD

The disclosed embodiments relate to devices, and, in particular, to semiconductor devices with alignment marks for locating and aligning circuits and methods of manufacturing the same.

BACKGROUND

The current trend in semiconductor fabrication is to manufacture smaller and faster devices with a higher density of components for computes, cell phones, pagers, personal digital assistants, and many other products. However, decrease in circuit size can lead to certain challenges during manufacturing processes. For example, locating circuits, such as in aligning and attaching wafers or surface mounting devices, becomes increasingly difficult as the circuits decrease in size.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A and FIG. 1B illustrate a wafer having alignment marks thereon in accordance with embodiments of the technology.

FIG. 2-FIG. 6 illustrate example phases for a manufacturing process in accordance with embodiments of the technology.

FIG. 7 is a flow diagram illustrating an example method of manufacturing an apparatus in accordance with an embodiment of the present technology.

FIG. 8 is a schematic view of a system that includes an apparatus configured in accordance with embodiments of the present technology.

DETAILED DESCRIPTION

In the following description, numerous specific details are discussed to provide a thorough and enabling description for embodiments of the present technology. One skilled in the relevant art, however, will recognize that the disclosure can be practiced without one or more of the specific details. In other instances, well-known structures or operations often associated with semiconductor devices are not shown, or are not described in detail, to avoid obscuring other aspects of the technology. In general, it should be understood that various other devices, systems, and methods in addition to those specific embodiments disclosed herein may be within the scope of the present technology.

Several embodiments of semiconductor devices, packages, assemblies, or combinations thereof in accordance with the present technology can include initially forming one or more alignment marks within the silicon of the semiconductor wafer and then surfacing/exposing the buried alignment marks during a wafer thinning process. In some embodiments, the resulting alignment marks can be used for wafer-to-wafer bonding that joins at least two silicon wafers together to create a single, integrated device. The exposed alignment marks can be used to align the separate wafers, thereby accurately connecting the electrical circuits and connections between the bonded wafers.

In some embodiments, the wafer manufacturing process can include implanting visually or otherwise detectable/locatable (via, e.g., ultraviolet wavelength of light) material under a top/front surface of the silicon wafer and under the circuitry. Some examples of the implanted material can include fluorescent material, phosphorescent material, and the like, such as Phosphorus, Gallium, or a combination thereof. In one or more embodiments, the depth of the implanted material can correspond to a targeted thickness of the silicon wafer (e.g., ranging between 1 μm to 2 μm, with a tolerance between 0.25 μm and 0.5 μm). The material can be implanted through a mask, such as through an opening in the mask, that is used to form the circuits or a portion thereof on the active side of the wafer. The implantation mask may be aligned with and/or applied over a circuit forming mask.

The wafer manufacturing process can include subsequently exposing the implanted material during a wafer thinning process. Backside portions of the wafer can be removed, such as using a dry etch process, until the remaining wafer is reduced to have the targeted thickness. The implanted material can have a shape, a size, a gradient, or other similar physical characteristics associated with being initially implanted at a depth, such as using a mask, and then exposed via a backside etch.

Implanting the marker through the frontside, aligned with the circuitry, and before the backside thinning can provide improved accuracy in relative positioning between the implanted marker and circuits. Accordingly, the implanted marker can improve the accuracy and the consistency in aligning the wafer and the corresponding circuits to another structure, such as for wafer-to-wafer bonding. Moreover, the use of the thinning process to expose the alignment marks is beneficial. For example, thinning can improve yield by reducing the amount of stress applied on the wafer during the alignment process. Reducing stress on the wafer will reduce the risk of breaking or damaging the wafer. Additionally, thinning can also improve accuracy during the alignment process. Because thinning reduces the distance between the alignment marks and the device layer, the accuracy of the alignment will improve. Moreover, thinning will also reduce the amount of reflection that occurs during the alignment process. Reflection can interfere with the alignment marks of the wafers, making it difficult to accurately align the wafers, thus thinning can alleviate this problem.

FIG. 1A and FIG. 1B illustrate a semiconductor wafer 100 having alignment marks 102 (e.g., implanted distinguishable material, such as fluorescent or phosphorescent material) thereon in accordance with embodiments of the technology. FIG. 1A illustrates a perspective view of the wafer 100. FIG. 1B illustrates a partial cross sectional view taken along a dashed line 1A-1A of FIG. 1A. Referring to FIG. 1A and FIG. 1B together, the wafer 100 can have the alignment marks 102 formed using a marking device 104 (e.g., an implantation device).

The wafer 100 can have circuits 106 (e.g., integrated circuits) formed on an active side 112. The alignment marks 102 can be on or detectable through a passive side (e.g., a backside) opposite the active side 112. The wafer 100 can have a target thickness 116 measured between the active side 112 and the passive side 114. In some embodiments, the target thickness 116 can be 5 μm or less (e.g., 2 μm, 1 μm, or less). In other embodiments, the target thickness can be 100 nm or less (e.g., 20 nm or less).

As described in detail below, the wafer 100 can be manufactured based on forming the alignment marks 102 implanted and buried within an initial wafer 120 (e.g., between the active side 112 and an initial backside of the initial wafer 120). The initial wafer 120 can have an initial thickness 126 (e.g., as measured between the active side 112 and the initial backside) greater than the target thickness 116. As an illustrative example, the marking device 104 can implant visually or otherwise detectable/locatable material at a targeted depth (e.g., a depth equivalent to the target thickness 116) within the initial thickness 126.

Subsequently, the initial wafer 120 can be thinned, such as by removing a backside portion thereof using an etching process, to form the wafer 100. Accordingly, the previously buried alignment marks 102 can surface and be exposed on the backside/passive side 114 of the wafer 100. Once exposed, the alignment marks 102 can be used to accurately align the circuits 106 to circuits on another structure, such as another wafer targeted to be bonded to the wafer 100.

In some embodiments, the formation of the alignment marks 102 can occur during frontside processing of the wafer 100. In other words, the buried alignment marks 102 can be implanted during, as a part of, or after forming the circuits 106. For example, the buried alignment marks 102 can be formed using a marking mask aligned with a circuit forming mask or using a designated opening or portion on the circuit forming mask.

The buried alignment marks 102 can be formed using one or more marking devices 104 to implant the detectable/locatable material. The implanted material can include fluorescent material, phosphorescent material, and the like that respond to visible or non-visible light (e.g., light having ultraviolet frequencies/wavelengths). For example, the implanted material can include Phosphorus, Gallium, or a combination thereof. In such embodiments, the marking devices 104 can be positioned above the wafer 100. A mask previously used to form the circuits 106 on the surface of the wafer 100 can further include openings for delivering the energy produced by the marking devices 104. The marking devices 104 can be configured or tuned to implant the material at a predetermined depth below the active side 112 of the wafer 100. In certain embodiments, the targeted depth of the alignment mark 102 is between 1 μm and 2 μm.

FIG. 2-FIG. 6 illustrate example phases for a manufacturing process in accordance with embodiments of the technology. FIG. 2 illustrates a cross sectional view of a semiconductor structure 200 (e.g., a wafer) in accordance with embodiments of the technology. The semiconductor structure 200 can correspond to the initial wafer 120 of FIG. 1B having the initial thickness 126 greater than the target thickness 116 of FIG. 1B.

The structure 200 can have a mask 202 over the active side 112 thereof. In some embodiments, the mask 202 can be used to form the circuits 106 of FIG. 1B or a portion thereof. In other embodiments, the mask 202 can be aligned with another mask used to form the circuits 106. Accordingly, the mask 202 can have marking openings 204 at designated/fixed locations relative to the circuits 106.

The marking devices 104 can apply and implant the target material through the marking openings 204 of the mask 202 to form buried marks 212. The marking devices 104 can form the buried marks 212 below the active side 112 (e.g., top surface), such as at a marking depth 214. The marking depth 214 can correspond to the target thickness 116 (e.g., at the same depth/location as or within a threshold distance of the planned backside of the passive side 114 of FIG. 1B). Also, the buried marks 212 can have a targeted vertical dimension that corresponds to (1) a depth for the resulting mark and/or (2) a variability or a tolerance level associated with the target thickness 116.

FIG. 3 illustrates a cross sectional view of an intermediate structure 300 (e.g., a bonded structure) in accordance with embodiments of the technology. The structure 300 can have the structure 200 (e.g., the initial wafer 120 of FIG. 1B) attached or bonded to a carrier wafer 302. In some embodiments, the structure 300 can be wafer bonded to the carrier wafer 302 to enhance structural support for the initial wafer 120. In other words, the carrier wafer 302 can be electrically isolated from the circuits 106 of FIG. 1B on the initial wafer 120. Instead, the carrier wafer 302 can be bonded to the initial wafer 120 to provide additional rigidity and structural integrity for the initial wafer 120 during subsequent manufacturing processes. For example, by bonding the carrier wafer 302 to the initial wafer 120, the carrier wafer 302 can prevent structural damages to the initial wafer 120 during and after thinning.

In some embodiments, the initial wafer 120 can have a cover over the active side 112 of FIG. 1B and the circuits 106. The initial wafer 120 can be bonded to the carrier wafer 302 after forming the alignment marks 102 under the active side 112 and/or the circuits 106. In some embodiments, once the wafer 100 with the buried alignment marks 102 is bonded to the carrier wafer 202, the carrier wafer 202 can act as a support to the wafer 100 during the wafer thinning process to surface or expose the buried alignment marks.

FIG. 4 illustrates a cross sectional view of an intermediate structure 400 in accordance with embodiments of the technology. The intermediate structure 400 can represent a result of thinning the initial wafer 120 of FIG. 3 from the structure 300 of FIG. 3. The thinning process can remove a back portion of the initial wafer 120 using a dry etching process, a mechanical etching or polishing process, a chemical or wet etching process, and/or the like. The thinning process can proceed until the initial thickness 126 of FIG. 1B of the initial wafer 120 is reduced to target thickness 116. As a result, the wafer 100 can be formed or remain bonded to the carrier wafer 302, and the thinning process can establish the backside/passive side 114 of the wafer 100.

The thinning process can further expose the alignment marks 102 on the passive side 114 of the wafer 302. The alignment marks 102 can correspond to the buried marks 212 of FIG. 2 and may have a reduced thickness compared to the buried marks 212. In other words, the alignment marks 102 can result from exposing the buried marks 212.

The resulting alignment marks 102 can have one or more physical traits indicative of the initial implantation and the subsequent exposure process. For example, the alignment marks 102 can have a shape, a depth, a gradient pattern, a dimension, or a combination thereof associated with implanting material at the targeted depth within silicon structure. The implantation at depth and the subsequent exposure can provide a different physical signature for the alignment marks 102 in comparison to mark formed directly on the backside after thinning.

In addition to the different physical traits, the alignment marks 102 can provide greater accuracy and consistency in its relative location to the active circuit in comparison to other marks formed on the thinned backside. Conventional alignment marks are formed by a step or a process separate from the formation of the circuits, thereby introducing an additional source for error, inaccuracy, and inconsistency. In contrast, the alignment marks 102 can be formed by implanting the marker material during or as a part of the frontside processing to form the circuits, such as using one or more masks used for the circuit formation as a common reference. Accordingly, the alignment marks 102 can have increased accuracy and consistency in their locations relative to the integrated circuit on the wafer.

FIG. 5 illustrates a cross sectional view of an intermediate structure 500 in accordance with embodiments of the technology. The structure 500 can have a first semiconductor wafer 502 bonded to a second semiconductor wafer 504. The first wafer 502, the second wafer 504, or both can have alignment marks 102 of FIG. 1B. In other words, the first wafer 502, the second wafer 504, or both can result from the process described above using FIG. 2 through FIG. 4. The wafers 502 and 504 can be bonded using one or more wafer bonding techniques, such as direct bonding, hybrid bonding, oxide bonding, and the like.

In bonding the wafers, the manufacturer or a corresponding system can use the alignment marks 102 on one or both of the wafers to control a relative positioning of the wafers. In other words, the method for bonding the wafers can include aligning the wafers using the alignment marks 102 on one or both of the wafers. Accordingly, the alignment marks 102 can increase the accuracy in the relative positions of the circuits on the bonded wafers and increase the likelihood that the electrical connections are formed as intended, thereby reducing bonding failures and any associated reworks and losses.

For illustrative purposes, FIG. 5 shows the wafers bonded at the front sides. However, it is understood that the wafers can be bonded differently, such as front-to-back or back-to-back. For other relative arrangements, one or more of the circuits can have vias or other vertical connections that extend across the thickness of the wafer to connection pads/locations. The alignment marks 102 can be used to relatively locate such connection pads/locations and ensure that they contact and are connected to targeted locations on the other wafer.

In some embodiments, the bonded wafers can be configured to form memory devices. For example, one of the wafers can be an array wafer that includes data storage cells in its circuits, and another of the wafers can be a control (CMOS) wafer with circuits configured to operate or control the wafer circuits.

The dashed lines in FIG. 5 can represent a singulation or dicing process for the bonded wafers or the structure 500. FIG. 6 illustrates a cross sectional view of a semiconductor device 600 in accordance with embodiments of the technology. The device 600 can represent one of the singulated devices resulting from cutting, sawing, or otherwise dicing the structure 500 of FIG. 5. Accordingly, the device 600 can include a first die 602 bonded to a second die 604. The dies 602 and 604 can have circuits on active sides thereof.

In some embodiments, the first die 602, the second die 604, or both can have the alignment marks 102 on backsides thereof. Both the bonding and the alignment marks 102 can be remnants or byproducts of the wafer-level processing described above. Additionally or alternatively, the alignment marks 102 can be placed at designated locations about the device 600, such as to provide identifiable locations relative to one or more circuits on the device 600. The alignment marks 102 can be further utilize to position the device 600 and/or one or more portions thereof relative to other circuits, such as during a mounting process. Also, the alignment marks 102 can provide reference locations for the circuits, such as for identifying and processing manufacturing defects within the device 600.

The device 600 can include a memory device, such as a Dynamic Random-Access Memory (DRAM), a NAND Flash memory, other volatile or non-volatile memory, a combination memory, or the like. For example, one of the first dies 602 or the second die 604 can include memory array(s) configured to store and provide access to data. The other of the first dies 602 or the second die 604 can include the control circuitry (e.g., CMOS) configured to control storage of and manage the data at the memory array and/or control access to the stored data. The control circuitry can include input/output circuitry, command and/or address processing circuitry, power management circuitry, clock or coordination circuitry, and/or the like.

FIG. 7 is a flow diagram illustrating an example method 700 of manufacturing an apparatus in accordance with an embodiment of the present technology. The example method 700 can be for manufacturing the wafer 100 of FIG. 1B, the bonded structure 500 of FIG. 5, the device 600 of FIG. 6, or a combination thereof. For example, the method 700 can include forming and utilizing the alignment marks 102 of FIG. 1B.

The method 700 can include providing an initial semiconductor wafer (e.g., the initial wafer 120 of FIG. 1B and FIG. 2) as illustrated at block 702. The initial wafer can have the initial thickness 126 of FIG. 2.

The method 700 can include, at block 704, forming circuits (e.g., the circuits 106 of FIG. 1B) on the initial wafer. The circuits can be formed by doping, shaping, and electrically connecting various portions. Circuits, such as transistors, capacitors, diodes, and the like, can be formed using one or more masks to deposit dopants to, deposit, and/or remove various materials and portions on the active side 112 of FIG. 1B of the initial wafer.

The method 700 can include forming buried alterations (e.g., the buried marks 212 of FIG. 2) under the active/top side of the initial wafer, such as by implanting distinguishable marker material, as illustrated at block 706. For example, the method 700 can include using the marking devices 104 of FIG. 1A and FIG. 2 to form the buried marks 212 at the marking depth 214 of FIG. 2. The marking devices 104 can use the mask 202 and implant the marking material into the initial wafer through the marking opening 204. The marking devices 104 can be configured or tuned to implant at the marking depth 214.

At block 708, the initial wafer can be bonded to a carrier wafer. For example, the initial wafer 120 of FIG. 3 can be bonded to the carrier wafer 302 of FIG. 3 to provide structural support for the initial wafer 120 during subsequent manufacturing processes.

At block 710, the initial wafer can be thinned. The back portions of the initial wafer can be removed or etched away as illustrated at block 712. The etching process can thin the wafer to the target thickness 116 of FIG. 1B using one or more etching processes as described above. At block 714, the method 700 can include exposing the implanted markings, such as the buried marks 212 of FIG. 2, thereby forming or establishing the alignment marks 102 of FIG. 1B.

The thinned and marked wafer can be bonded to another functional wafer as illustrated at block 720. For example, the first wafer 502 of FIG. 5 can be bonded to the second wafer 504 of FIG. 5 as described above. Also, one or more of the wafers can be detached from corresponding carrier wafers. In bonding the wafers, as illustrated at block 722, the method 700 can include aligning the wafers using the alignment marks 102 on one or more of the wafers. The alignment marks 102 can be positioned relative to other marks on another wafer and/or one or more reference locations apart from the wafers.

The method 700 can further include forming bonded dies as illustrated at block 724, such as by dicing or cutting the bonded wafers as described above. The resulting device 600 of FIG. 6 can have semiconductor devices/dies that are bonded to each other via wafer-level processing.

FIG. 8 is a schematic view of a system that includes an apparatus in accordance with embodiments of the present technology. Any one of the semiconductor devices described above with reference to FIGS. 1-7 can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system 890 shown schematically in FIG. 8. The system 890 can include a semiconductor device 800 (“device 800”) (e.g., a semiconductor device, package, and/or assembly), a power source 892, a driver 894, a processor 896, and/or other subsystems or components 898. The device 800 can include features generally similar to those devices described above. The resulting system 890 can perform any of a wide variety of functions, such as memory storage, data processing, and/or other suitable functions. Accordingly, representative systems 890 can include, without limitation, hand-held devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, and appliances. Components of the system 890 may be housed in a single unit or distributed over multiple, interconnected units (e.g., through a communications network). The components of the system 890 can also include remote devices and any of a wide variety of computer-readable media.

This disclosure is not intended to be exhaustive or to limit the present technology to the precise forms disclosed herein. Although specific embodiments are disclosed herein for illustrative purposes, various equivalent modifications are possible without deviating from the present technology, as those of ordinary skill in the relevant art will recognize. In some cases, well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the present technology. Although steps of methods may be presented herein in a particular order, alternative embodiments may perform the steps in a different order. Similarly, certain aspects of the present technology disclosed in the context of particular embodiments can be combined or eliminated in other embodiments. Furthermore, while advantages associated with certain embodiments of the present technology may have been disclosed in the context of those embodiments, other embodiments can also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages or other advantages disclosed herein to fall within the scope of the technology. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein, and the invention is not limited except as by the appended claims.

Throughout this disclosure, the singular terms “a,” “an,” and “the” include plural referents unless the context clearly indicates otherwise. Similarly, unless the word “or” is expressly limited to mean only a single item exclusive from the other items in reference to a list of two or more items, then the use of “or” in such a list is to be interpreted as including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list. Additionally, the terms “comprising,” “including,” and “having” are used throughout to mean including at least the recited feature(s) such that any greater number of the same feature and/or additional types of other features are not precluded. Reference herein to “one embodiment,” “an embodiment,” “some embodiments” or similar formulations means that a particular feature, structure, operation, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present technology. Thus, the appearances of such phrases or formulations herein are not necessarily all referring to the same embodiment. Furthermore, various particular features, structures, operations, or characteristics may be combined in any suitable manner in one or more embodiments.