CROSS-REFERENCE TO RELATED APPLICATIONS

This is a continuation of International Patent Application No. PCT/CN2021/104158, filed on Jul. 2, 2021, which claims the priority of Chinese Patent Application No. 202110269749.6 filed on Mar. 12, 2021. The entire disclosures of the above-referenced applications are incorporated herein by reference in their entirety.

BACKGROUND

With the gradual development of the storage device technology, a Dynamic Random-Access Memory (DRAM) is gradually applied to various electronic devices due to its higher density and faster reading and writing speed. The DRAM includes a bit line structure, a capacitor structure and a transistor structure. The bit line structure and the capacitor structure are respectively connected with the transistor structure. The data stored in the capacitor structure is read through the control of the transistor structure.

SUMMARY

The embodiments of the present disclosure relate to the technical field of semiconductor manufacturing, and particularly relate to a method for manufacturing a semiconductor structure and the semiconductor structure.

In a first aspect, the embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, including:

a substrate is provided;

a plurality of bit line structures distributed at intervals are formed on the substrate, each of the bit line structures includes a conductive layer, a transition layer and a covering layer stacked sequentially, and the width of the transition layer is smaller than the width of the conductive layer; and

air gaps are formed on a top surface of the conductive layer and side surfaces of the transition layer.

In some embodiments, the width of the covering layer is greater than the width of the conductive layer, and the air gaps protrude from the side surfaces of the conductive layer.

In a second aspect, the embodiments of the present disclosure further provide a semiconductor structure, including:

a substrate;

a plurality of bit line structures distributed at intervals on the substrate, each of the bit line structures including a conductive layer, a transition layer and a covering layer stacked sequentially, and the width of the transition layer being smaller than the width of the conductive layer; and

air gaps located on a top surface of the conductive layer and side surfaces of the transition layer.

According to the method for manufacturing the semiconductor structure and the semiconductor structure provided in this embodiment, a plurality of bit line structures are distributed on the substrate, each of the bit line structures includes a conductive layer, a transition layer and a covering layer stacked sequentially, the width of the transition layer is smaller than the width of the conductive layer, and the air gaps are formed on the top surface of the conductive layer and the side surfaces of the transition layer.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the drawings required for description in the embodiments or the prior art will be briefly described below. It is apparent that the drawings in the following description are some embodiments of the present disclosure. Those skilled in the art can also obtain other drawings according to these drawings without any creative work.

FIG. 1 is a flow diagram of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.

FIG. 2 is a schematic structural diagram after a mask layer is formed in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.

FIG. 3 is a schematic structural diagram after grooves are formed in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.

FIG. 4 is a schematic structural diagram after insulation sealing layers are formed in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.

FIG. 5 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.

DETAILED DESCRIPTION

In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It is apparent that the described embodiments are a part of the embodiments of the present disclosure, but are not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present disclosure.

Various embodiments of the present disclosure can address performance of DRAM.

More specifically, some embodiments provide a method for manufacturing a semiconductor structure and the semiconductor structure to improve the performance of the semiconductor structure.

As shown in FIG. 1, the method for manufacturing the semiconductor structure provided in this embodiment includes:

In S101, a substrate is provided.

The substrate serves as the basis of a subsequent film layer and can achieve a support effect on the subsequent film layer. Exemplarily, the material of the substrate can be a semiconductor material, including silicon, germanium, silicon germanium, etc. This embodiment does not limit the material of the substrate.

Referring to FIG. 2 to FIG. 5, shallow trench isolation structures 10 and active region structures 20 arranged at intervals can be formed on the substrate (not shown), so as to facilitate the formation of a transistor structure.

After the substrate is formed, the method for manufacturing the semiconductor structure provided in this embodiment further includes:

In S102, a plurality of bit line structures distributed at intervals are formed on the substrate, each of the bit line structures includes a conductive layer, a transition layer and a covering layer stacked sequentially, and the width of the transition layer is smaller than the width of the conductive layer.

Continuing to refer to FIG. 2 to FIG. 5, a conductive layer 301, a transition layer 302 and a covering layer 3031 are stacked, the transition layer 302 is located between the covering layer 3031 and the conductive layer 301, and the conductive layer 301 is arranged close to the substrate. For example, the conductive layer 301 can be connected with an active structure 20. Exemplarily, the conductive layer 301 can be connected with a source electrode or a gate electrode of the active structure 20.

The specific steps of forming the conductive layer 301 can include: as shown in FIG. 2, a conductive initial layer 311 is formed. Exemplarily, a first conductive initial layer 3111, a conductive contact initial layer 3112 and a second conductive initial layer 3113 are sequentially stacked along a direction distal from the substrate. The conductive contact initial layer 3112 is located between the first conductive initial layer 3111 and the second conductive initial layer 3113. The conductive contact initial layer 3112 can prevent the materials constituting the first conductive initial layer 3111 and the second conductive initial layer 3113 from permeating, and can also reduce the contact resistance between the first conductive initial layer 3111 and the second conductive initial layer 3113. Exemplarily, the material of the first conductive initial layer 3111 can include polysilicon, the material of the second conductive initial layer 3113 can include tungsten, and the material of the conductive contact initial layer 3112 can include titanium nitride or tungsten nitride.

In some embodiments, the width of the transition layer 302 is smaller than the width of the conductive layer 301 (taking the orientation shown in FIG. 3 as an example, the width is a size in a horizontal direction). After the conductive initial layer 311 is formed, a transition initial layer 312 and a covering initial layer 313 which are stacked are formed, and a mask layer 50 having a mask pattern is formed on the covering initial layer 313. As shown in FIG. 3, then the covering initial layer 313, the transition initial layer 312 and the conductive initial layer 311 are etched by taking the mask layer 50 as a mask, so as to form the covering layer 3031, the transition layer 302 and the conductive layer 301. At this time, the covering layer 3031, the transition layer 302 and the conductive layer 301 have the same width. After that, the transition layer 302 can be etched horizontally to remove a portion of the transition layer 302 to form grooves 304, such that the width of the finally formed transition layer 302 is smaller than the width of the conductive layer 301. Exemplarily, a portion of the transition layer 302 can be removed by a wet process. In other examples, when the covering initial layer 313, the transition initial layer 312 and the conductive initial layer 311 are etched by taking the mask layer 50 as a mask, a portion of the transition initial layer 312 that is partially located below the covering layer 3031 is etched simultaneously, such that the width of the formed transition layer 302 is smaller than the width of the conductive layer 301. Exemplarily, when the transition initial layer 312 is etched, the gas with a higher etching selection ratio of the transition initial layer 312 to the conductive initial layer 311 and the covering initial layer 313 can be selected for etching, and then, a portion of the transition initial layer 312 below the covering layer 3031 is etched along a width direction, such that the width of the finally formed transition layer 302 is smaller than the width of the conductive layer 301.

In this embodiment, a plurality of bit line structures 30 are distributed at intervals. Exemplarily, a plurality of bit line structures 30 extend in a line shape along a direction parallel to the substrate, a plurality of bit line structures 30 can be located in the same plane parallel to the substrate, and a plurality of bit line structures 30 are arranged in parallel and at intervals. Of course, the bit line structures 30 in this embodiment can also be distributed on the substrate in other forms, which is not limited in this embodiment.

After a plurality of bit line structures 30 distributed at intervals are formed, the method for manufacturing the semiconductor structure provided in this embodiment further includes:

In S104, air gaps are formed on the top surface of the conductive layer and the side surfaces of the transition layer.

As shown in FIG. 4 to FIG. 5, exemplarily, the width of the transition layer 302 in the bit line structure 30 is smaller than the width of the conductive layer 301, such that the bit line structure 30 forms grooves 304 on two sides of the transition layer 302 along a width direction. In order to form air gaps 305, the bit line structure 30 can include insulation sealing layers 3032 covering the side walls of the conductive layer 301 and the side walls of the covering layer 3031. At this time, the insulation sealing layers 3032 seal the grooves 304 to form the air gaps 305 located on two sides of the transition layer 302 along the width direction.

Exemplarily, the insulation sealing layers 3032 can be formed by CVD or ALD, and the grooves 304 are prevented from being filled with the insulation sealing layers 3032 at the same time, such that the air gaps 305 are enclosed by the insulation sealing layers 3032, the conductive layer 301, the transition layer 302 and the covering layer 3031.

Exemplarily, the material of the insulation sealing layer 3032 can be the same as the material of the covering layer 3031. For example, the material of both the insulation sealing layer 3032 and the covering layer 3031 can be silicon nitride, silicon oxide, etc. Since the material of the insulation sealing layer 3032 is the same as the material of the covering layer 3031, after the insulation sealing layers 3032 are formed, the covering layer 3031 and the insulation sealing layers 3032 can be formed into an integrated structure to improve the strength of a coating layer 303.

According to the method for manufacturing the semiconductor structure provided in this embodiment, a plurality of bit line structures 30 are distributed on the substrate, each of the bit line structures 30 includes a conductive layer 301, a transition layer 302 and a covering layer 3031 stacked sequentially, the width of the transition layer 302 is smaller than the width of the conductive layer 301, and the air gaps 305 are formed on the top surface of the conductive layer 301 and the side surfaces of the transition layer 302. By forming the air gaps 305 on the top surface of the conductive layer 301 and the side surfaces of the transition layer 302, the influence of the covering layer 3031 on the conductive layer 301 can be reduced. For example, when the material of the covering layer 3031 is silicon nitride and the material of the conductive layer 301 is tungsten, the existence of the air gaps 305 can reduce the degree to which nitrogen in the covering layer 3031 migrates to the conductive layer 301 to nitride the conductive layer 301 to form tungsten nitride so as to prevent the resistance of the conductive layer 301 from increasing, and also can reduce the parasitic capacitance between the bit line structures 30 and the surrounding structures thereof, thereby improving the performance of the semiconductor structure.

In some embodiments, the width of the covering layer 3031 can be greater than the width of the conductive layer 301, and the formed air gaps 305 can protrude from the side surfaces of the conductive layer 301. By such arrangement, the contact area between the air gaps 305 and the top surface of the conductive layer 301 can be increased to improve the protective effect on the top surface of the conductive layer 301. At the same time, the volume of the air gaps 305 can be increased to further improve the parasitic capacitance between the bit line structures 30 and the surrounding structures (such as conductive plugs 40).

Continuing to refer to FIG. 5, the method for manufacturing the semiconductor structure provided in this embodiment further includes: a conductive plug 40 is formed on the substrate between the bit line structures 30, the conductive plug 40 is located between adjacent bit line structures 30, and the conductive plug 40 is used to connect the active region structure 20. In an implementation manner in which a semiconductor structure is a DRAM, the conductive plug 40 is also used to connect a capacitor storage structure.

Exemplarily, the conductive plug 40 includes a first conductive portion 401 and a second conductive portion 402 which are sequentially stacked along a direction perpendicular to the substrate. In other words, the second conductive portion 402 is located over the first conductive portion 401, the first conductive portion 401 is connected with the active region structure 20, and the second conductive portion 402 can be used to connect a capacitor. Exemplarily, the material of the first conductive portion 401 can include polysilicon, etc., and the material of the second conductive portion 402 can include tungsten, etc. In order to prevent the materials of the first conductive portion 401 and the second conductive portion 402 from permeating each other, a conductive barrier film can be arranged between the first conductive portion 401 and the second conductive portion 402. The material of the conductive barrier film can include titanium nitride, etc.

The bottom portion of the second conductive portion 402 has an inclined surface 4021 facing the bit line structure 30.

In some embodiments, the bottom of the inclined surface 4021 is higher than the top of the conductive layer 301, and the top of the inclined surface 4021 is lower than the top of the transition layer 302, such that the top of the transition layer 302 is located between the top and bottom of the inclined surface 4021. At this time, the formed conductive layer 301 can be as high as possible and has smaller resistance.

Exemplarily, the bottom portion of the second conductive portion 402 further includes a bottom surface 4024, a first straight surface 4022 and a second straight surface 4023. The bottom surface 4024 is in direct contact with the top surface of the first conductive portion 401, and two ends of the bottom surface 4024 are respectively connected with the first straight surface 4022 and the second straight surface 4023. The first straight surface 4022 is also connected with the inclined surface 4021.

In the above implementation manner, the vertical distance between the top corner of the transition layer 302 and the inclined surface 4021 is smaller than the vertical distance between the top corner of the conductive layer 301 and the inclined surface 4021. The top corner of the transition layer 302 is a first vertex a of the top end of the transition layer 302 close to the inclined surface 4021 in a cross section perpendicular to the substrate and perpendicular to the extension direction of the bit line structure 30 (in the cross section as shown in FIG. 5). The vertical distance between the top corner of the transition layer 302 and the inclined surface 4021 is a vertical distance d1 between the first vertex a and the inclined surface 4021. Correspondingly, the top corner of the conductive layer 301 is a second vertex b of the top end of the conductive layer 301 close to the inclined surface 4021 in a cross section perpendicular to the substrate and perpendicular to the extension direction of the bit line structure 30 (in the cross section as shown in FIG. 5). The vertical distance between the top corner of the conductive layer 301 and the inclined surface 4021 is a vertical distance d2 between the second vertex b and the inclined surface 4021.

In other examples, the vertical distance d1 between the top corner of the transition layer 302 and the inclined surface 4021 is greater than the vertical distance d2 between the top corner of the conductive layer 301 and the inclined surface 4021. By such arrangement, when the transition layer 302 is a conductor, the resistance of the bit line structure 30 can be reduced, and the parasitic capacitance between the bit line structure 30 and the conductive plug 40 can also be further reduced.

In this embodiment, the width of the transition layer 302 is ⅔ to ¾ of the width of the conductive layer 301. Such arrangement can reduce the influence of the covering layer 3031 on the conductive layer 301, ensure the supporting force for the covering layer 3031, and avoid the covering layer 3031 collapsing due to a too small width of the transition layer 302.

The material of the transition layer 302 provided in this embodiment can include metal-rich nitride (such as tungsten nitride, molybdenum nitride, titanium nitride, etc.) or metal-rich silicide (such as titanium silicide, tungsten silicide, etc.). By such arrangement, the metal-rich nitride and the metal-rich silicide can capture nitrogen atoms migrated from the covering layer 3031 to the conductive layer 301, so as to further avoid the influence of the conductive layer 301 on the covering layer 3031 to prevent the resistance of the conductive layer 301 from increasing. Exemplarily, the metal-rich nitride means that the molar ratio of metal atoms to nitrogen atoms is greater than 1, such as 2, 3, 4, 5, 6, 7, etc., and the metal-rich silicide means that the molar ratio of metal atoms to silicon atoms is greater than 1, such as 2, 3, 4, 5, 6, 7, etc.

Continuing to refer to FIG. 5, this embodiment further provides a semiconductor structure which can be manufactured by the method for manufacturing the semiconductor structure provided by any one of the above embodiments. Each of the bit line structures of the semiconductor structure includes a conductive layer 301, a transition layer 302 and a covering layer 3031 stacked sequentially. The width of the transition layer 302 is smaller than the width of the conductive layer 301, and air gaps 305 are formed on the top surface of the conductive layer 301 and the side surfaces of the transition layer 302. The transition layer 302 and the air gaps 305 can reduce the influence of the covering layer 3031 on the conductive layer 301 to prevent the resistance of the conductive layer 301 from increasing, thereby improving the performance of the semiconductor structure.

The semiconductor structure provided in this embodiment includes a substrate and a plurality of bit line structures distributed at intervals on the substrate. Each of the bit line structures includes a conductive layer 301, a transition layer 302 and a covering layer 3031 stacked sequentially. The width of the transition layer 302 is smaller than the width of the conductive layer 301.

Exemplarily, the material of the substrate can include silicon, germanium, silicon germanium, etc. The material of the substrate is not limited in this embodiment. Shallow trench isolation structures 10 and active region structures 20 arranged at intervals can be formed on the substrate, so as to facilitate the formation of a transistor structure.

The conductive layer 301, the transition layer 302 and the covering layer 3031 are stacked, the transition layer 302 is located between the covering layer 3031 and the conductive layer 301, and the conductive layer 301 is arranged close to the substrate. The conductive layer 301 can include a first conductive layer 3011, a conductive contact layer 3012 and a second conductive layer 3013 which are sequentially stacked along a direction distal from the substrate. The conductive contact layer 3012 is located between the first conductive layer 3011 and the second conductive layer 3013, and the conductive contact layer 3012 can prevent the materials constituting the first conductive layer 3011 and the second conductive layer 3013 from permeating. Exemplarily, the material of the first conductive layer 3011 can include polysilicon, the material of the second conductive layer 3013 can include tungsten, and the material of the conductive contact layer 3012 can include titanium nitride.

In this embodiment, a plurality of bit line structures are distributed at intervals. Exemplarily, a plurality of bit line structures extend in a line shape along a direction parallel to the substrate, a plurality of bit line structures can be located in the same plane parallel to the substrate, and a plurality of bit line structures are arranged in parallel and at intervals. Of course, the bit line structures in this embodiment can also be distributed on the substrate in other forms, which is not limited in this embodiment.

Continuing to refer to FIG. 5, the air gaps 305 are located on the top surface of the conductive layer 301 and the side surfaces of the transition layer 302. In other words, the air gaps 305 are formed between the side surfaces of the transition layer 302 and the top surface of the conductive layer 301.

In some implementation manners, a coating layer 303 can include a covering layer 3031 located at the upper portion of the transition layer 302 and insulation sealing layers 3032 covering the side walls of the covering layer 3031 and the side walls of the conductive layer 301. Since the width of the transition layer 302 is smaller than the width of the conductive layer 301, grooves can be formed on two sides of the transition layer 302. After the insulation sealing layers are formed, the insulation sealing layers 3032 cover the grooves to form the air gaps 305.

In some embodiments, the width of the covering layer 3031 is greater than the width of the conductive layer 301.

In some embodiments, the air gaps 305 protrude from the side surfaces of the conductive layer 301, that is, the air gaps 305 protrude outward from the side surfaces of the conductive layer 301. By such arrangement, the contact area between the air gaps 305 and the top surface of the conductive layer 301 can be increased to improve the protection effect on the top surface of the conductive layer 301. At the same time, the volume of the air gaps 305 can be increased to further improve the parasitic capacitance between the bit line structures 30 and the surrounding structures (such as conductive plugs 40).

Continuing to refer to FIG. 5, the semiconductor structure provided in this embodiment further includes conductive plugs 40 located between the bit line structures, each of the conductive plugs 40 is located between adjacent bit line structures 30, and the conductive plug 40 is used to connect the active region structure 20. In an implementation manner in which a semiconductor structure is a DRAM, the conductive plug 40 is also used to connect a capacitor storage structure.

Exemplarily, the conductive plug 40 includes a first conductive portion 401 and a second conductive portion 402 which are sequentially stacked along a direction perpendicular to the substrate. In other words, the second conductive portion 402 is located over the first conductive portion 401, the first conductive portion 401 is connected with the active region structure 20, and the second conductive portion 402 is used to connect a capacitor storage structure. Exemplarily, the material of the first conductive portion 401 can include polysilicon, etc., and the material of the second conductive portion 402 can include tungsten, etc. In order to prevent the materials of the first conductive portion 401 and the second conductive portion 402 from permeating each other, a conductive barrier film can be arranged between the first conductive portion 401 and the second conductive portion 402. The material of the conductive barrier film can include titanium nitride, etc.

The bottom portion of the second conductive portion 402 has an inclined surface 4021 facing the bit line structure 30, and the bottom of the inclined surface 4021 is higher than the top of the conductive layer 301 and lower than the top of the transition layer 302, such that the top of the transition layer 302 is located between the top and bottom of the inclined surface 4021.

Exemplarily, the bottom portion of the second conductive portion further includes a bottom surface 4024, a first straight surface 4022 and a second straight surface 4023. The bottom surface 4024 is in direct contact with the top surface of the first conductive portion 401, and two ends of the bottom surface 4024 are respectively connected with the first straight surface 4022 and the second straight surface 4023. The first straight surface 4022 is also connected with the inclined surface 4021. By the arrangement of the first straight surface 4022 and the second straight surface 4023, the distance between the transition layer 302 and the second conductive portion 402 of the conductive plug 40 can be further increased to reduce the parasitic capacitance between the two, and at the same time, short circuit defects can be reduced to improve the yield.

In the above implementation manner, the vertical distance between the top corner of the transition layer 302 and the inclined surface 4021 is smaller than the vertical distance between the top corner of the conductive layer 301 and the inclined surface 4021. The top corner of the transition layer 302 is a first vertex a of the top end of the transition layer 302 close to the inclined surface 4021 in a cross section perpendicular to the substrate and perpendicular to the extension direction of the bit line structure 30 (in the cross section as shown in FIG. 5). The vertical distance between the top corner of the transition layer 302 and the inclined surface 4021 is a vertical distance d1 between the first vertex a and the inclined surface 4021. Correspondingly, the top corner of the conductive layer 301 is a second vertex b of the top end of the conductive layer 301 close to the inclined surface 4021 in a cross section perpendicular to the substrate and perpendicular to the extension direction of the bit line structure 30 (in the cross section as shown in FIG. 5). The vertical distance between the top corner of the conductive layer 301 and the inclined surface 4021 is a vertical distance d2 between the second vertex b and the inclined surface 4021.

In other examples, the vertical distance d1 between the top corner of the transition layer 302 and the inclined surface 4021 is greater than the vertical distance d2 between the top corner of the conductive layer 301 and the inclined surface 4021. By such arrangement, when the transition layer 302 is a conductor, the resistance of the bit line structure 30 can be reduced, and the parasitic capacitance between the bit line structure 30 and the conductive plug 40 can also be further reduced.

In this embodiment, the width of the transition layer 302 is ⅔ to ¾ of the width of the conductive layer 301. Such arrangement can reduce the influence of the covering layer 3031 on the conductive layer 301, ensure the supporting force for the covering layer 3031, and avoid the covering layer 3031 collapsing due to a too small width of the transition layer 302.

The material of the transition layer 302 provided in this embodiment can include metal-rich nitride (such as tungsten nitride, molybdenum nitride, titanium nitride, etc.) or metal-rich silicide (such as titanium silicide, tungsten silicide, etc.). By such arrangement, the metal-rich nitride and the metal-rich silicide can capture nitrogen atoms migrated from the covering layer 3031 to the conductive layer 301, so as to further reduce the influence of the conductive layer 301 on the covering layer 3031 to prevent the resistance of the conductive layer 301 from increasing. For example, the material of the covering layer 3031 can include silicon nitride, etc.

It should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, but are not limited thereto. Although the present disclosure is described in detail with reference to the above embodiments, it should be understood by those skilled in the art that the technical solutions recorded in the above embodiments may be modified, or some or all of the technical features may be equivalently replaced. However, the essence of the corresponding technical solutions does not depart from the scope of the technical solutions of the embodiments of the present disclosure due to these modifications or replacements.