CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 16/985,124, filed on Aug. 4, 2020, which is a continuation of application Ser. No. 16/691,016, filed on Nov. 21, 2019, which is a continuation of application Ser. No. 15/878,754, filed on Jan. 24, 2018, which claims the benefit of U.S. provisional application 62/551,477, filed on Aug. 29, 2017. All of the above-referenced applications are hereby incorporated herein by reference in their entirety.

BACKGROUND

As known by those skilled in the art, a conventional analog PLL may be susceptible to errors (or even error propagation) since said analog PLL uses analog operations and analog elements. Therefore, digital phase-locked loops (DPLL), which utilize a counter with a variable divisor on the feedback path, are proposed for relieving the errors with the partial aid of digital operations and digital elements, and moreover, an all-digital phase-locked loop (ADPLL) may significantly help in area reduction and process migration. For example, a digitally-controlled oscillator (DCO) may be used to replace the conventionally used voltage-controlled oscillator (VCO), which is an analog element. A phase detector may also be replaced with a time-to-digital converter. Therefore, ADPLL is gaining popularity and becoming a trend in radio communications.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. Specifically, dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a diagram illustrating an all-digital phase locked loop (ADPLL) in accordance with various embodiments of the present disclosure;

FIG. 2 is a diagram illustrating an LMS-based calibration unit in accordance with a first embodiment of the present disclosure;

FIG. 3 is a diagram illustrating an LMS-based calibration unit in accordance with a second embodiment of the present disclosure;

FIG. 4 is a diagram illustrating an LMS-based calibration unit in accordance with a third embodiment of the present disclosure;

FIG. 5 is a diagram illustrating an LMS-based calibration unit in accordance with a fourth embodiment of the present disclosure;

FIG. 6 is a timing diagram illustrating convergence of an estimated DCO normalization value during frequency hopping in accordance with various embodiments of the present disclosure;

FIG. 7 is a timing diagram illustrating an oscillator clock during frequency hopping in accordance with various embodiments of the present disclosure;

FIG. 8 is a diagram illustrating an R_Rgenerating unit in accordance with various embodiments of the present disclosure;

FIG. 9 is a diagram illustrating an ADPLL in accordance with various embodiments of the present disclosure; and

FIG. 10 is a timing diagram illustrating the status of the DCO at different modes in accordance with various embodiments of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in the respective testing measurements. Also, as used herein, the term “about” generally means within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the term “about” means within an acceptable standard error of the mean when considered by one of ordinary skill in the art. Other than in the operating or working examples, or unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages such as those for quantities of materials, durations of times, temperatures, operating conditions, ratios of amounts, and the likes thereof disclosed herein should be understood as modified in all instances by the term “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary as desired. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise.

The present disclosure is an apparatus and a method of calibrating the gain of a digitally controlled oscillator (DCO). The disclosure is applicable to any system in which it is desirable to estimate, calibrate and track the gain of an RF digitally controlled oscillator such as those in mobile phones and other wireless applications. The disclosure is intended for use in a digital radio transmitter or transceiver but can be used in other applications as well, such as a general communication channel. The present disclosure provides a solution to the problems and disadvantages of prior art gain calibration techniques.

To aid in understanding the principles of the present disclosure, the description is provided in the context of a digital RF processor (DRP) transmitter and receiver that may be adapted to comply with a particular wireless communications standard such as GSM, Bluetooth, WCDMA, etc. It is appreciated, however, that the disclosure is not limited to use with any particular communication standard and may be used in optical, wired and wireless applications. Further, the disclosure is not limited to use with a specific modulation scheme but is applicable to any modulation scheme including both digital and analog modulation. The disclosure is applicable to any system in which it is desirable to estimate, calibrate and track the modulation gain of a digitally controlled oscillator.

FIG. 1 is a diagram illustrating an all-digital phase locked loop (ADPLL) 100 in accordance with various embodiments of the present disclosure. For illustration purposes only, the ADPLL 100, as shown, is adapted for a system including frequency hopping modulation, such as the Bluetooth low energy v4.0 standard. It is appreciated, however, that one skilled in the communication arts can adapt the ADPLL 100 illustrated herein to other modulations and communication standards as well without departing from the spirit and scope of the present disclosure. For example, the ADPLL 100 illustrated in FIG. 1 can be employed by the GSM/EDGE cellular standard.

In this disclosure, a reference clock CKR of the ADPLL 100 is configured to have a reference frequency f_Rmuch lower than a modulation frequency f_FMof the modulation clock CKFM. For example, the reference frequency f_Rof the reference clock CKR may be 32.768 kHz for cost reduction and power saving. The modulation frequency f_FMof the modulation clock CKFM may be about 7 to 10 MHz. However, this is not a limitation of the present disclosure. The hopping frequency level is not limited, may be in a range from kHz to THz. In this disclosure, the Bluetooth low energy v4.0 includes 40 channels each having a 2 MHz bandwidth, and the total bandwidth is 80 MHz.

The core of the ADPLL 100 is a digitally controlled oscillator (DCO) 106 adapted to generate an oscillator clock CKV. This DCO 106 here may be any type of oscillator, such as an LC tank oscillator, a ring oscillator, a Colpitts oscillator, a Hartly oscillator. The output of the DCO 106, i.e. the oscillator clock CKV, may serve as a carrier frequency of a transmitter. In many instances, the oscillator clock CKV may be further divided before using. A value of the DCO gain of the DCO 106 may be defined as a frequency of the oscillator clock CKV over an oscillator tuning word (OTW) of the DCO 106. The DCO gain may be affected by the current state of process, voltage and temperature (PVT) at any point in time. With the help of the precisely calibrated DCO gain, the ADPLL 100 is able to employ a two point direct modulation scheme and does not need to redo extra close loop locking process each time the channel is changed throughout the frequency hopping.

The close loop locking process only needs to be carried out when each time the ADPLL 100 is powered up. In particular, the ADPLL 100 of the present disclosure is configured to always stay settled to a center channel CH_CENTamong all the channels, e.g. (the 20^thchannel of the Bluetooth low energy v4.0) and is configured to perform the combined channel hopping and frequency modulation by instantaneously offsetting resonance of the DCO 106 from the center channel CH_CENTvia the two point direct modulation scheme. In this way, fast frequency hopping can be achieved even at extremely low reference clock CKR since the locking time for frequency hopping is substantially zero. The accuracy of the frequency hopping modulation highly depends on accurate estimation and calibration of the DCO gain. Please note that it is not a limitation to configure the ADPLL 100 to always stay settled to the center channel CH_CENT. In many instances, the ADPLL 100 may be always stay settled to a channel that is not around the center channel CH_CENT.

The oscillator clock CKV may be divided by a divider 114 to produce the modulation clock CKFM. A frequency hopping and modulation control unit 102 is used to provide a current channel CH based on a predetermined channel hopping sequence in accordance with the system that the ADPLL 100 is designed for, e.g. the Bluetooth low energy v4.0 standard. However, this is not a limitation of the present disclosure. In some instances, the channel hopping sequence may be a random, pseudo random or periodic sequence that is predetermined or real-time generated, i.e. on-the-fly. The frequency hopping and modulation control unit 102 further generates components of an overall frequency command word (FCW). The FCW may be defined as the frequency of the oscillator clock CKV over the reference frequency f_Rof the reference clock CKR. The FCW includes components FCW_CENT, FCW_CH-CENTand FCW_FM. FCW_CENTcorresponds to a frequency of the center channel CH_CENT, e.g. (the 20^thchannel of the Bluetooth low energy v4.0). FCW_CH-CENTcorresponds to a frequency of the difference between the center channel CH_CENTand a channel indicated by the signal CH. FCW_FMcorresponds to a frequency of the frequency modulation. The overall frequency command word FCW is defined as the frequency division ratio of an expected variable frequency fv of the oscillator clock CKV to the reference frequency f_Rof the reference clock CKR. In the present disclosure, FCW_CENTand FCW_CH-CENTbelong to the reference clock CKR domain, and FCW_FMbelongs to the oscillator clock CKV domain.

A Least mean squares (LMS)-based calibration unit 104 is used to iteratively calibrate an estimated DCO gain K_DCObased on the LMS algorithm during frequency hopping according to the channel CH and a filtered phase error (i.e. φ_{E_filtered}as shown in FIG. 1) output by a digital loop filter 108. The LMS-based calibration unit 104 outputs an estimated DCO normalization value (i.e. f_R/K_DCOas shown in FIG. 1) for generating components of the oscillator tuning word (OTW), including OTW_CENT, OTW_CH-CENTand OTW_FM. OTW_CENTcorresponds to the center channel CH_CENT, e.g. (the 20^thchannel of the Bluetooth low energy v4.0). OTW_CH-CENTcorresponds to the difference between the center channel CH_CENTand the current channel CH. OTW_FMcorresponds to frequency modulation. In particular, OTW_CENTis a product of a multiplier 109 that multiplies the estimated DCO normalization value f_R/K_DCOby the filtered phase error φ_{E_filtered}. OTW_CH-CENTis a product of a multiplier 101 that multiplies the estimated DCO normalization value f_R/K_DCOby the FCW component FCW_CH-CENT. OTW_FMis a product of a multiplier 103 that multiplies the estimated DCO normalization value f_R/K_DCOby the FCW component FCW_FM. The OTW components OTW_CENT, OTW_CH-CENT, and OTW_FMthen are summed up by an adder 107 and fed to the DCO 106.

An R_Rgenerating unit 110 is used to generate a reference phase R_Raccording to the reference clock CKR, the modulation clock CKFM, the FCW components FCW_FM, FCW_CENT, and FCW_CH-CENT. An accumulator 112 is used to generate a variable phase R_Vaccording to the reference clock CKR and the oscillator clock CKV. A phase error φ_Eis obtained by subtracting the variable phase R_Vfrom the reference phase R_Raccording through an adder 105. The variable phase R_Voutput from the accumulator 112 reflects a cycle number of the oscillator clock CKV per cycle of the reference clock CKR. The reference phase R_Routput from the R_Rgenerating unit 110 reflects the averaged FCW (i.e. FCW_CENT+FCW_CH-CENT+averaged FCW_FM) per cycle of the reference clock CKR.

FIG. 2 is a diagram illustrating the LMS-based calibration unit 104 in accordance with a first embodiment of the present disclosure. The LMS-based calibration unit 104 includes a sampler 1044 to sample the received the filtered phase error φ_{E_filtered}according to a delayed reference clock CKR_d. The delayed reference clock CKR_d is obtained by delaying the reference clock CKR, and a delay time thereof is determined according to a delay unit 1046. In the present disclosure, the delay time is predetermined. A sign unit 1042 is configured to perform a sign function, i.e. to extract the sign, upon (the current channel CH−the center channel CH_CENT). For instance, when the center channel is the 20^thchannel and the frequency hopping and modulation control unit 102 controls ADPLL 100 hopping to the 30^thchannel, sign (30-20) is +1 and the sign unit 1042 output+1. When the center channel is the 20^thchannel and the frequency hopping and modulation control unit 102 controls ADPLL 100 hopping to the 8^thchannel, sign (8-20) is −1 and the sign unit 1042 output −1. In the present disclosure, when the current channel CH and the center channel are the same, the sign unit 1042 output +1.

The sampled filtered phase error φ_{E_filtered}is then multiplied by the sign (CH−CH_CENT) to obtain a gradient ∇, and the gradient ∇ is multiplied by a step size μ to obtain a phase error err. The step size μ may be a predetermined value or can adaptively change according to the status of convergence. An accumulator 1048 is configured to accumulate the phase error err and is operated at the reference clock CKR domain. The accumulated phase error err is also representative of the estimated DCO normalization value f_R/K_DCO. The behavior of the LMS-based calibration unit 104 of FIG. 2 can be summarized as f_R/K_DCO[n]=f_R/K_DCO[n−1]+μ*φ_{E_filtered}[n]*sign (CH−CH_CENT), where n is the index of the reference clock CKR.

Alternative embodiments of the LMS-based calibration unit 104 are shown in FIG. 3 to FIG. 5. FIG. 3 is a diagram illustrating the LMS-based calibration unit 104 in accordance with a second embodiment of the present disclosure. In FIG. 3, another sign unit 1045 shows to extract the sign of the sampled filtered phase error φ_{E_filtered}. The behavior of the LMS-based calibration unit 104 of FIG. 3 can be summarized as f_R/K_DCO[n]=f_R/K_DCO[n−1]+μ*sign (φ_{E_filtered}[n])*sign (CH−CH_CENT), where n is the index of the reference clock CKR.

FIG. 4 is a diagram illustrating the LMS-based calibration unit 104 in accordance with a third embodiment of the present disclosure. In FIG. 4, no sign units are used. The behavior of the LMS-based calibration unit 104 of FIG. 4 can be summarized as f_R/K_DCO[n]=f_R/K_DCO[n−1]+μ*φ_{E_fitered}[n]*(CH−CH_CENT), where n is the index of the reference clock CKR. FIG. 5 is a diagram illustrating the LMS-based calibration unit 104 in accordance with a fourth embodiment of the present disclosure. The behavior of the LMS-based calibration unit 104 of FIG. 3 can be summarized as f_R/K_DCO[n]=f_R/K_DCO[n−1] μ*sign (φ_{E_filtered}[n])*(CH−CH_CENT), where n is the index of the reference clock CKR.

FIG. 6 is a timing diagram illustrating convergence of the estimated DCO normalization value during frequency hopping in accordance with various embodiments of the present disclosure. In FIG. 6, the center channel CH_CENTis configured to be the 20^thchannel. At time point t1, the current channel CH is the 40^thchannel, as such sign (CH−CH_CENT) is +1. After multiplying the filtered phase error φ_{E_filtered}[t1] having a negative value by +1, the gradient ∇ [t1] having a negative value is obtained. The gradient ∇[t1] is then multiplied by the step size μ and accumulated with the previous estimated DCO normalization value f_R/K_DCOby the accumulator 1048, to output the current estimated DCO normalization value f_R/K_DCO[t1]. At time point t2, the current channel CH is the 1^stchannel, as such sign (CH−CH_CENT) is −1. After multiplying the filtered phase error φ_{E_filtered}[t2] having a positive value by −1, the gradient ∇ [t2] having a negative value is obtained. The gradient ∇[t2] is then multiplied by the step size μ and accumulated with the previous estimated DCO normalization value f_R/K_DCO[t1] by the accumulator 1048, to output the current estimated DCO normalization value f_R/K_DCO[t2]. As illustrated in FIG. 6, the current estimated DCO normalization value f_R/K_DCO[t2] has a value less than the previous estimated DCO normalization value f_R/K_DCO[t1] since the gradient V[t2] is a negative value.

It can be seen from FIG. 6 that the current channel CH then hops to the 30^thchannel, and then to the 10^thchannel, and the estimated DCO normalization value f_R/K_DCO[t3] and the estimated DCO normalization value f_R/K_DCO[t4] are gradually converges to the dashed line, which represents the calibrated value of the estimated DCO normalization value f_R/K_DCO[t3] and estimated DCO normalization value f_R/K_DCO.

In light of the above, the estimated DCO normalization value f_R/K_DCOcan be precisely calibrated during the frequency hopping. The precisely estimated DCO normalization value f_R/K_DCOis advantageous for two point direct modulation scheme since the estimated DCO normalization value f_R/K_DCOcan be used to produce the oscillator tuning word OTW directly. The OTW component OTW_CH-CENTis obtained by multiplying the FCW component FCW_CH-CENTby the estimated DCO normalization value f_R/K_DCO; and the OTW component OTW_FMis obtained by multiplying the FCW component FCW_FMby the estimated DCO normalization value f_R/K_DCO; and the OTW component OTW_CENTis obtained by multiplying the filtered phase error φ_{E_filtered}by the estimated DCO normalization value f_R/K_DCO. If the estimated DCO normalization value f_R/K_DCOis accurate enough, the ADPLL 100 is able to instantaneously hop to any channel with high accuracy.

FIG. 7 is a timing diagram illustrating the oscillator clock CKV during frequency hopping in accordance with various embodiments of the present disclosure. Compared to conventional ADPLL, the ADPLL 100 of the present disclosure only performs the close loop locking process at the initial stage, e.g. when the ADPLL 100 is powered on. Please note that in FIG. 7, the frequency modulation is omitted for conciseness.

FIG. 8 is a diagram illustrating the R_Rgenerating unit 110 in accordance with various embodiments of the present disclosure. As mentioned above, the R_Rgenerating unit 110 is used to generate the reference phase R_Raccording to the reference clock CKR, the modulation clock CKFM, the FCW components FCW_FM, FCW_CENT, and FCW_CH-CENTThe R_Rgenerating unit 110 includes an average unit 1102, an accumulator 1104 and an adder 1101. The average unit 1102 is used to obtain an average value of the FCW components FCW_FMin each cycle of the reference clock CKR. The averaged FCW_FMis added to the FCW components FCW_CENT, and FCW_CH-CENTto obtain the overall frequency command word FCW. The overall frequency command word FCW then is accumulated in the accumulator 1104 and the accumulated overall frequency command word FCW is output as the reference phase R_R.

Referring back to FIG. 1, the accumulator 112 is used to accumulate the number of rising edges of the oscillator clock CKV in each cycle of the reference clock CKR, and the accumulated number of rising edges of the oscillator clock CKV is output as the variable phase R_V. The difference between the reference phase R_Rand the variable phase R_Vis the phase error φ_E. By using the R_Rgenerating unit 110 and the accumulator 112 to calculate the reference phase R_Rand the variable phase R_V, the reference frequency f_Rof the reference clock CKR can be configured to be lower than the modulation frequency f_FMof the modulation clock CKFM.

FIG. 9 is a diagram illustrating an ADPLL 900 in accordance with various embodiments of the present disclosure. Compared to the ADPLL 100, the ADPLL 900 further includes a retainer 902 for storing the filtered phase error φ_{E_filtered}. In particular, the retainer 902 is configured to store the filtered phase error φ_{E_filtered}before the ADPLL 900 entering into a power saving mode. In many instances, the retainer 902 always updates the filtered phase error φ_{E_filtered}when the ADPLL 900 operates in a normal mode. The date stored in the retainer 902 is not effected even when the ADPLL 900 enters into the power saving mode. For example, the retainer 902 may be supplied by a voltage source which is not powered down during the power saving mode. When the ADPLL 900 is waked up, the filtered phase error φ_{E_filtered}stored in the retainer 902 can be immediately resumed and fed to the subsequent LMS-based calibration unit 104 and the multiplier 109 for use via a multiplexer 901. The multiplexer 901 selectively outputs the filtered phase error φ_{E_filtered}from the digital loop filter 108 or the retainer 902 according to a signal wakeup, which indicates whether the ADPLL 900 is in the power saving mode. In this way, fast wake up of the ADPLL 900 can be achieved.

Moreover, the ADPLL 900 further includes a retainer 904 for storing the estimated DCO normalization value f_R/K_DCOand a retainer 906 for storing the OTW component OTW_CENT. Similar to the retainer 902, the retainers 904 and 906 can temporarily store data in before the ADPLL 900 entering into the power saving mode, and the stored data can be used for fast wake up when the ADPLL 900 leaves the power saving mode and enters the normal mode.

FIG. 10 is a timing diagram illustrating the status of the DCO 106 at different modes in accordance with various embodiments of the present disclosure. The ADPLL 900 is initially configured to be in the normal mode. At time point t1, the retainers 902, 904 and 906 save the filtered phase error φ_{E_filtered}, the estimated DCO normalization value f_R/K_DCOand the OTW component OTW_CENTrespectively. Then the ADPLL 900 enters into the power saving mode at time point t2, and the DCO 106 is turned off. At time point t3, the signal wakeup is asserted, and the ADPLL 900 starts to resumes the filtered phase error φ_{E_filtered}, the estimated DCO normalization value f_R/K_DCOand the OTW component OTW_ENTstored in the retainers 902, 904 and 906. In this way, the DCO 106 is able to be back to normal operation and directly produce a desired frequency at time point t4 in a short time.

Some embodiment of the present disclosure provides a frequency generator for generating an oscillator clock according to a reference clock, the frequency generator being used in a frequency hopping system that switches a carrier frequency among a plurality of channels, the carrier frequency further carrying a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, wherein the FCW includes: a first FCW component corresponding to a frequency of a predefined channel; a second FCW component corresponding to a frequency difference between the predefined channel and the current channel; and a third FCW component corresponding to the modulation frequency; a calibration unit, arranged for iteratively calibrating an estimated DCO normalization value during frequency hopping according to the current channel and a phase error obtained according to the oscillator clock and the reference clock; and a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) obtained according to the estimated DCO normalization value.

Some embodiment of the present disclosure provides a frequency generator for generating an oscillator clock according to a reference clock, the frequency generator being used in a frequency hopping system that switches a carrier frequency among a plurality of channels, the carrier frequency further carrying a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence; a calibration unit, arranged for iteratively calibrating an estimated DCO normalization value during frequency hopping according to the current channel and a phase error obtained according to the oscillator clock and the reference clock, the calibration unit including: a sampler, arranged for sampling the phase error according to the reference clock; and an arithmetic unit, arranged for obtain a difference by subtracting a predefined channel from the current channel; and a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) obtained according to the estimated DCO normalization value.

Some embodiment of the present disclosure provides a frequency generation method for generating an oscillator clock according to a reference clock, the frequency generation method being used for a frequency hopping system that switches a carrier frequency among a plurality of channels, the carrier frequency further carrying a modulation frequency for data transmission. The method includes: providing a current channel according to a channel hopping sequence; and iteratively calibrating an estimated DCO normalization value during frequency hopping at least according to the current channel.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other operations and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.