CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No. 62/537,334 filed on Jul. 26, 2017, the contents of which are hereby incorporated by reference.

TECHNICAL FIELD

The present disclosure relates generally to self-powered power sensors (SPPSs) and, more specifically, to accurately synchronizing an SPPS for measuring power consumption when using wireless SPPSs.

BACKGROUND

The use of self-powered power sensors (SPPSs) placed at a plurality of locations within a facility's electrical grid allows for the remote measurement of power consumption throughout the grid. Typically, such SPPSs are positioned at points of interest of power consumption, such as at circuit breakers or at higher power consumption devices.

FIG. 1 is a block diagram of a SPPS 100 that includes a current transformer (CT) 103 having its primary winding accepting the primary current 102. The SPPS 100 further includes an analog-to-digital converter (ADC or A/D) 105 that converts the analog signal into a series of digital samples under the control of a clock or timer 113 and a microcontroller (MC) 107. The samples gathered by the ADC 105 are processed by the MC 107 and then, using a transceiver 109, the processed information is transmitted using an antenna 116. An oscillator 110 oscillates at a desired frequency and feeds to the clock or timer 113.

FIG. 2 is a block diagram of a modified SPPS 200 that includes the same basic elements as described for the SPPS 100 depicted in FIG. 1. The modified SPPS 200 further includes a low pass filter (LPF) 202 coupled to the CT 103 and ADC 105. In one configuration, the LPF 202 is an analog filter. The input current 201 may be derived from the CT 103. The LPF 202 may be implemented in many different ways including, but not limited to, passive or active filters, matched filters, or harmonic filters. The filtered signal 203 is fed to the ADC 105. The MC 107 can select what signal shall be sampled (i.e., an input signal 104 or a filtered signal 203). The ADC 105 may include two channels, where both signals can be sampled simultaneously. In one configuration, the LPF 202 can be activated only when sampling the fundamental signal 203, thus saving power consumption.

FIG. 3 is a block diagram of yet another modified SPPS 300 that includes the same basic elements as described regarding the modified SPPS 200 depicted in FIG. 2. The SPPS 300 further includes a zero-crossing (or zero-cross) detector circuit 301 connected to the LPF 202 and the clock or timer 113. The filtered signal 203 is fed to a zero-crossing detection circuit 301 which generates a signal 302 relative to the zero-crossing time of the filtered signal 203. Further, the generated signal 302 may be time-stamped by, for example, the clock or timer 113. The zero-crossing detection circuit 301 may include a comparator, preferably with a small aperture to avoid significant errors in the zero-crossing detection.

Regardless of these and other implementations for determining power consumption, currently available SPPSs allow for only limited accuracy of measurement. That is, to accurately measure the power consumption of a load it is necessary to measure the power factor. Such a factor contains information of the phase difference between the voltage and the load current, as well as the distortion of the load current and voltage from a pure sinusoidal wave. In previous power measuring systems, voltage and current are simultaneously measured by the same physical device and therefore the relationship between the two signals is easy to calculate and measure. However, when there is a wireless connection between the current and voltage sampling, accurate measurement requires additional innovation to overcome the deficiencies of wireless SPPSs for measuring power consumption accurately.

It would therefore be advantageous to provide a solution that would overcome the challenges noted above.

SUMMARY

A summary of several example embodiments of the disclosure follows. This summary is provided for the convenience of the reader to provide a basic understanding of such embodiments and does not wholly define the breadth of the disclosure. This summary is not an extensive overview of all contemplated embodiments, and is intended to neither identify key or critical elements of all embodiments nor to delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later. For convenience, the term “certain embodiments” may be used herein to refer to a single embodiment or multiple embodiments of the disclosure.

Certain embodiments disclosed herein include a method for the synchronization of a central controller wirelessly connected to at least one self-powered power sensor (SPPS). The method includes: sampling an electrical signal by at least one SPPS; estimating by the at least one SPPS a time of a sample of the electrical signal; generating a packet comprising packet components including a preamble, a synchronization field, and message data; generating synchronization information for the synchronization field of the packet; transmitting wirelessly the packet components; determining a time offset value for the packet, the time offset calculated from the time of the sample of the electrical signal and a transmission time-stamp of the synchronization information; and transmitting the time offset value by appending it to the packet, wherein the time offset value is used for the purpose of calculating at least an electrical parameter.

Certain embodiments disclosed herein also include a non-transitory computer readable medium having stored thereon instructions for causing a processing circuitry to perform a process. The process includes: sampling an electrical signal by at least one SPPS; estimating by the at least one SPPS a time of a sample of the electrical signal; generating a packet comprising packet components including a preamble, a synchronization field, and message data; generating synchronization information for the synchronization field of the packet; transmitting wirelessly the packet components; determining a time offset value for the packet, the time offset calculated from the time of the sample of the electrical signal and a transmission time-stamp of the synchronization information; and transmitting the time offset value by appending it to the packet, wherein the time offset value is used for the purpose of calculating at least an electrical parameter.

Certain embodiments disclosed herein also include a system for the synchronization of a central controller wirelessly connected to at least one self-powered power sensor (SPPS). The system includes: a processing circuitry; and a memory, the memory containing instructions that, when executed by the processing circuitry, configure the system to: sample an electrical signal by at least one SPPS; estimate by the at least one SPPS a time of a sample of the electrical signal; generate a packet comprising packet components including a preamble, a synchronization field, and message data; generate synchronization information for the synchronization field of the packet; transmit wirelessly the packet components; determine a time offset value for the packet, the time offset calculated from the time of the sample of the electrical signal and a transmission time-stamp of the synchronization information; and transmit the time offset value by appending it to the packet, wherein the time offset value is used for the purpose of calculating at least an electrical parameter.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter disclosed herein is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the disclosed embodiments will be apparent from the following detailed description taken in conjunction with the accompanying drawings.

FIG. 1 is a first exemplary self-powered power sensor (SPPS).

FIG. 2 is a second exemplary SPPS.

FIG. 3 is a third exemplary SPPS.

FIG. 4 is a message timing diagram and message structure transferred between an SPPS and central controller.

FIG. 5 is a block diagram of a central controller according to an embodiment.

FIG. 6 is a flowchart of a method for providing samples and synchronization information from an SPPS to a central controller according to an embodiment.

FIG. 7 is a flowchart of a method for calculation of root mean square information of an input voltage according to an embodiment.

FIG. 8 is a flowchart of a method for receiving synchronized samples from an SPPS according to an embodiment.

FIG. 9 is a diagram of a system including a plurality of SPPSs wirelessly connected to a central controller according to an embodiment.

DETAILED DESCRIPTION

It is important to note that the embodiments disclosed herein are only examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily limit any of the various claimed embodiments. Moreover, some statements may apply to some inventive features but not to others. In general, unless otherwise indicated, singular elements may be in plural and vice versa with no loss of generality. In the drawings, like numerals refer to like parts through several views.

Some example disclosed embodiments include a method and system for a self-powered power sensor (SPPS) to sample a current signal and wirelessly transmit a message. Current signal samples and transmission time offset information is further provided. Transmission begins prior to the completion of the creation of the packet so as to include a transmission offset time that is used by a central controller for the estimation of electrical parameters. The central controller may sample the voltage signal and determine, based on the packet received and the information received from the SPPS, a phase shift of the current versus the voltage, as well as a power factor. This method reduces the need of the SPPS to detect sampled signal zero crossing.

The various embodiments will be described with reference to FIGS. 1 to 3. As noted above, the SPPS 100 includes a CT 103 having its primary winding accepting the primary current 102 and an ADC 105 that converts the analog signal 104 into a series of digital samples 106 under the control of a clock or timer 113 and a microcontroller (MC) 107. The samples 106 gathered by the ADC 105 are processed by the MC 107 and then, using a transceiver 109, processed information is transmitted using antenna 116. An oscillator 110 oscillates at a desired frequency and feeds to the clock or timer 113. U.S. Pat. No. 9,134,348 entitled “Distributed Electricity Metering System,” and which is assigned to common assignee, describes in further details such an exemplary SPPS.

The power of the input current may be used to provide the power needed for the operation of the SPPS 100; to detect the actual power consumption of the load connected to the power line 102; and to detect and time stamp the phase of the current signal.

The following description is focused on the detection of the actual power consumption of the load connected to the power line 102 and to the detection and time stamping of the phase of the current signal. Specifically, the disclosed embodiment allows for accurately measuring the power consumption of a load based on the measurement of a power factor, which is a factor that contains information on the phase difference between the voltage and the load current, as well as the distortion of the load current and voltage from a pure sinusoidal wave. In standard power measuring systems, voltage and current are simultaneously measured by the same physical device and therefore the relation between the two signals is easy to determine and measure.

According to one embodiment, the input current signal (i.e., the signal sampled from the power line) 102 is transformed by the current transformer 103 to an analog signal 104 which can be sampled by an ADC 105 connected to a microcontroller 107. The analog signal 104 is a periodic signal representing the load current with a frequency equivalent to the grid frequency. Such a signal typically is a sinusoidal or close to sinusoidal waveform but may also be highly distorted and include high-order harmonics. Typically, the CT analog signal is a current signal connected to a small resistor (e.g., a current sense resistor—not shown in the figure). The voltage generated across the sense resistor is then sampled by the ADC 105.

The ADC 105 can sample the input signal 104 with a sampling clock 112 which can be provided by the clock or timer 113. For example, this sampling clock 112 can be 3,200 Hz when sampling 50 Hz signals. In one embodiment, the clock or timer 113 is driven from a clock signal 111 provided by an oscillator 110. The samples 106 can be stored in the MC 107, for example, in a memory therein or a memory connected thereto (not shown), for further processing. In one embodiment, the MC 107 is in standby mode when triggered 114 by the clock or timer 113 to exit standby mode and start processing. This trigger may be an interrupt signal provided by the clock or timer 113.

When the MC 107 wakes-up, the MC 107 is configured to program the clock or timer 113 and the ADC 105 to start sampling the signal 104. The number of samples may include at least a half cycle of the signal (e.g., 32 samples when sampling a 50 Hz signal with a 3,200 Hz sampling clock). Once the samples 106 have been stored, the MC 107 is configured to process the samples to roughly estimate the start of a cycle (T_S) of the input signal 104.

In an embodiment, once the start of the cycle (T_S) has been estimated, the MC 107 can program the clock or timer 113 to force the ADC 105 to start a new burst of samples (e.g., 32 samples) at Ts. Since the start of the sampling is triggered by the clock or timer function 113, and not by a software command from the MC 107, the time-stamp of all the samples can be accurately recorded.

Without interrupting the clock or timer operation 113 (to avoid losing synchronization to the time-stamped samples), the SPPS 100 may start transmitting a wireless message 117 to a central controller (not shown). For that purpose, a radio frequency (RF) transceiver 109 is coupled to the MC 107 and to an antenna 116 to provide one or two-way communication with a central controller, such as employing a bridge, discussed in more detail herein below with respect of FIGS. 5 and 6.

In one embodiment, the RF transceiver 109 supports transmission only, i.e., uplink communication. Moreover, it should be noted that the method is designed to enable accurate power factor measurement using only an uplink communication. This advantage avoids activating the SPPS in receive mode in order to save energy with a self-powered device. However, the RF transceiver 109 may include a receiver portion to support features such as, but not limited to, sensing for a carrier signal, clock synchronization, acknowledgement, firmware download, configuration download, and the like. Typically, this should be an unlicensed industrial scientific medical (ISM) band transceiver, operative, for example and without limitation, at 2.4 GHz or sub GHz bands.

In another embodiment, some form of spread-spectrum modulation technique may be used, for example and without limitation, direct sequence spread spectrum (DSSS), to enable better coexistence with other systems working in the same environment. The communication rate should be high enough to enable coexistence of a couple of hundred SPPSs in the same electrical closet. The power consumption of the RF transceiver 109 should be low enough to adhere to energy harvesting limitations which may be used by an SPPS. Yet another requirement of the RF transceiver 109 is to support a communication range sufficient to operate in an electrical closet, e.g., 3-4 meters metallic reach environment.

In another embodiment, the range may reach up to a few tens of meters in an indoor environment. This enables the placing of SPPSs on individual devices, e.g., on machines in a production line of a factory, and a minimum number of bridge units in a given area. The RF transceiver 109 preferably uses a standard physical layer (PHY) supporting, for example, IEEE 802.15.4, or communication protocol, for example, ZigBee. Use of such standards enables easy integration with existing systems that already include wireless hardware, e.g., smart meters.

Upon determination that a transmission is to take place, the MC 107 prepares a message 108 to be transmitted. The message 108 is typically a single packet of data that may contain various types of information and includes the SPPS's unique identification (UID) which enables a central controller to positively associate the current data received with previous data handled by the central controller with respect of the SPPS 100. The transmitted message 108 may include different fields of information. One of those message fields may be a SYNC field which is typically transmitted following a message preamble. The SYNC field allows an accurate time-stamping 115 by the clock or timer 113 of the message transmission time (T₂).

In an embodiment, the message 108 packet may include, without limitations, various SPPS status information, hardware version, software version, alerts such as overload, average current, SPPS temperature, time-stamped samples, input signal characteristics, power off indication, e.g., upon identification that the load was turned off, and other system parameters. According to one embodiment, the message 108 may include the time stamp of the first sample T_Sand the values of all the samples. Such parameters may be saved until such time of transmission in the MC 107 memory (not shown). A cyclic redundancy code (CRC) calculation, forward error correction (FEC), or data redundancy may be further added to a packet for data validation at the receiver side.

As previously described, the input signal 104 may be a superposition of the fundamental frequency (for example 50 Hz) and higher order harmonics or noise. This is typical when sampling power lines connected to non-linear loads, such as, for example, on/off operations. In such an embodiment, estimating the phase shift of the sampled signal 106 (e.g., by a central controller 500) to another signal (e.g., voltage signal) may require a filtering of the input or sampled signal to allow estimation of the true phase of the fundamental component of the input signal.

According to one embodiment, filtering the input signal 104 may be performed by a digital filter implemented by the MC 107. In such an embodiment, the MC 107 may use the signal samples to generate a new set of samples of a filtered signal. For example, a third-order low pass filter with an attenuation of 20 dB of the third harmonic (i.e., 150 Hz harmonic for a 50 Hz input signal) may suffice for typical third harmonic distortions. Other embodiments may include different types of digital filters with a higher order.

The settling time of the digital filter may require using more than half a cycle. It may be necessary in certain embodiments to store 5 or 10 cycles so as to let the digital filter settle and provide an accurate output. In addition, as previously described, 32 samples per half cycle may not be sufficient for the same reason. In certain embodiments, it may be necessary to sample 80-120 per half cycle, or even more.

According to one embodiment, the MC 107 may also estimate the root mean square (RMS) value of the input signal 102 and the RMS value of the filtered signal (i.e., the fundamental component). Those values may be calculated using the respective signal samples and the filtered samples. This allows for a more accurately computation of the power factor according to the following approximation:

P



F

=

V
f



[
RMS
]

V
s



[
RMS
]

*

I
f



[
RMS
]

I
s



[
RMS
]

*

cos


(
φ
)

where, I_s[RMS] is the RMS value of the input (non-filtered) signal; I_f[RMS] is the RMS value of the fundamental component of the input signal; V_s[RMS] is the RMS value of the voltage; V_f[RMS] is the RMS value of the fundamental component of the voltage; cos (ϕ) is the displacement power factor, or the power factor of the fundamental signal; and, PF is the true power factor.

It should be noted that when using a filter to attenuate the harmonics and the noise, the phase delay introduced by the filter itself should be factored. This is important to allow estimating the true phase of the input current signal.

In one embodiment, when conditions to transmit are met, the MC 107 can implement a carrier sense multiple access (CSMA) protocol mechanism for the purpose of collision avoidance. The following steps may be taken: first, the receiver of the RF transceiver 109 is switched on. Second, the receiver senses whether there are currently other transmissions. This is particularly important in the environment in which the SPPS operates, which may be an environment rich with SPPSs. Third, upon determination that the air is free, the receiver is disabled and the transmitter of the RF transceiver 109 is enabled for transmission to send the information message 108; otherwise, the receiver is disabled and the MC 107 selects a random time interval, after which the MC 107 attempts to start a new transmission, until the desired transmission is completed.

In one embodiment, the information messages are short enough and the intervals between transmissions are long enough such that collisions are highly unlikely. In such an embodiment, the transmission of the transmitted message 117 may take place without pre-sensing of the air, thereby conserving energy. During the message 108 transmission, immediately after the SYNC field is transmitted, the SYNC transmission is time-stamped 115 by the clock or timer 113. The time-stamp of the SYNC field transmission is denoted as T₂. Since the clock or timer 113 is continuously running from the time the time-stamped samples have been collected until a message transmission is performed, the time-stamp T₂denoting the SYNC field transmission is fully synchronized with the time stamps of the first sample T_S. Thus, during the message 108 transmission the MC 107 determines the time difference between the SYNC field transmission T₂and the time stamp of the first sample T_Sof the signal 106. We denote this time as Delta T:

Delta T=T₂−T_S

In some configurations, the computation of the Delta T value includes handling the wraparound of the timer 113 between T_Sand T₂. According to one embodiment, the MC 107 is configured to estimate the value Delta T and insert this value in the message being transmitted 117. In addition, it should be apparent that the accuracy of Delta T is affected by the accuracy of the time stamps T_Sand T₂. For example, using a timer clock resolution of <1 μsec should provide highly accurate time stamps for an accurate power factor determination in accordance with the disclosed embodiments (for a 50 Hz signal, 1 degree of phase is around 55.56 μsec). It is important to note that Delta T is computed on the fly, that is, while the message 108 is being transmitted. Therefore, Delta T links the time stamp of the first sample T_Sto the actual time of the message transmission T₂. This process is further explained in relation to FIG. 4 below.

In one embodiment, the transmitted message may also include information to let the central controller receiving the message fully compute the phase shift, or time offset value, of the primary input current signal (i.e., the current signal through the power line, which is the primary winding of the current transformer 103) based on the voltage signal. This information may include the values of all or part of the filtered (if the signal is also filtered by the SPPS) and non-filtered samples of the input signal 104, the time delay of the CT 103 (T_CTD) which is the time delay of the SPPS's 100 current transformer 103 (i.e., the time difference between the primary current 102 and the signal 104 fed to the ADC 105).

It should be noted that a CT-based sensor may also cause a phase shift that may impact the accuracy of the measurements. In some cases, this phase delay may be significant and should not be ignored if an accurate power factor computation is desired. The CT 103 phase delay is not constant and is affected by several factors, including, but not limited to, input current 102 amplitude (RMS); type of current transformer; current transformer temperature; input signal 102 frequency; and, the air gap of the current transformer (in the case of a split core CT). Therefore, in one embodiment, a phase calibration factor value may be transmitted in the message sent from the SPPS 100 to the central controller. Such a calibration factor may be embedded as part of the code or configuration parameters of the MC 107 during manufacturing, or, if the SPPS 100 is susceptible to change, for example over time or a temperature range, by periodically performing a self-determination of the calibration factor necessary due to the current characteristics of the SPPS 100.

In another embodiment, the phase calibration factor can be a linear or a higher degree function of the input current, expressed in a formula or lookup table. This is specifically relevant for nonlinear CT's. In yet another embodiment, the phase calibration factor may be known to the central controller. Regardless of the way such a calibration factor is provided, the phase calibration factor may be used for the purpose of correcting the power factor or signal timing on a per SPPS 100 basis. It should be noted that a single calibration factor for all of the SPPS 100 is also possible without departing from the scope of the disclosure. According to one embodiment, the estimated CT 103 delay (T_CTD) is then transmitted to a central controller in the transmitted message.

The time delay of the CT 103 may also include the delay of filter (T_FD) which is the time delay of the filter (e.g., a low pass filter) used to attenuate the input signal distortion caused by harmonics and noise. T_FDrefers to the phase delay of the fundamental component of the input signal. According to one embodiment, the T_FDis computed or measured and transmitted to a central controller as part of the transmitted message. When digital filters are used, the delay of this filter is a function of the filter type, but it does not change among different SPPS units or the amplitude of the input current.

This information may also include the delay of transmitter (T_TD), which is the time delay introduced by the transmitter before the signal is actually transmitted through the antenna 116. This time delay is the difference between the time stamp (T₂) of the SYNC field and the time when the SYNC field has been transmitted through the antenna 116. This delay depends on the transmitter implementation and the logic used to generate a pulse at the end of the SYNC field transmission.

In one embodiment, this delay may be in the order of 10-20 μsec and cannot be ignored. However, often it is constant and can be accurately measured. According to one embodiment, the delay of the SPPS transmitter (T_TD) is determined or measured and transmitted to a central controller in the transmitted message. In different embodiments, all of the above delay factors can be summed together (T_CTD+T_TD+T_FD) and transmitted together as a single delay factor, transmitted separately, stored in any part of the receiving system, or any combination of the above.

The disclosed embodiments will now be described with reference to FIG. 2. As previously noted, the SPPS 200 includes the same basic elements as described for SPPS 100 depicted in FIG. 1. The SPPS 200 further includes a low pass filter 202 connected to the current transformer 103 and ADC 105. The low pass filter 202 may be an analog filter. The input 201 may be derived from the current transformer 103. The analog filter may be implemented in various ways, including passive or active filters, harmonic filters, and the like.

According to the embodiment shown in FIG. 2, the filtered signal 203 is fed to the ADC 105. Thus, the MC 107 can select which signal to be sampled (i.e., input signal 104 or filtered signal 203). In other embodiments, the ADC 105 includes two channels and both signals can be sampled simultaneously. According to one embodiment, the low pass filter 202 can be activated only when sampling the fundamental signal 203 is required, thus saving power consumption.

The disclosed embodiments will now be described with reference to FIG. 3. As previously noted, the SPPS 300 includes the same basic elements as described for SPPS 200 depicted in FIG. 2, where SPPS 300 further includes a zero-crossing detector circuit 301 coupled to the low pass filter 202 and the clock or timer 113. In one embodiment, the low pass filter 202 is an analog filter. The input 201 may be derived from the current transformer 103. The analog filter may be implemented in many different ways, including passive or active filters, matched filters, harmonic filters, and the like.

The filtered signal 203 is fed to a zero-crossing detection circuit 301 which generates a signal 302 relative to the zero-crossing time of the filtered signal 203. In an embodiment, using the zero-crossing circuitry is utilized to compare how accurate the calculations performed by the central controller 500 (FIG. 5) is, or for any other component of a system designated for such purposes, with respect to a zero-crossing determination at an SPPS. It should be noted that a central controller may be connected to a plurality of SPPSs, some as described in FIG. 1, others as described in FIG. 2 and yet others as described in FIG. 3.

FIG. 4 shows an example block diagram of a message timing and message structure for a message sent from an SPPS according to one embodiment. In an example, FIG. 4 shows a transfer of a message from SPPS 100 to a central controller, e.g., central controller (or bridge) 500.

According to one embodiment, the MC 107 in the SPPS 100 has the time stamp of the first sample T_Sof the input signal 408 if it contains harmonics that can cause an error in the phase shift estimation Without interrupting the time counting of the clock or timer 113, the MC 107 in the SPPS 100 may start transmitting a wireless message 400 to a central controller 500.

According to one embodiment, the transmitted message 400 includes a preamble 401, typically used by the receiver to detect the incoming signal and if necessary to align some of its parameters (e.g., gain, receive clock frequency and phase, and the like). Following the preamble 401, a SYNC field 402 may be transmitted. Typically, the SYNC field 402 is used to align the receiver to the frame itself (i.e., to the start of the message payload 406). The SYNC field 402 can be represented by a binary series that has good autocorrelation properties in order to allow for accurate frame synchronization of the receiver even in the presence of bit errors caused by a wireless link.

According to one embodiment, the receiver may discard the received message 400 if more than a certain amount of errors is detected (e.g., in a case in which the SYNC field 402 is 16 bits long, one can discard the received message if 2 out of 16 bits are wrong).

According to yet another embodiment, the transmission of the SYNC field 402 is time-stamped by the SPPS, denoted as T₂411. Further in accordance with this embodiment, time stamping of the SYNC field 402 transmission may be performed by the transmitter logic itself (not shown) or by adding an external logic (not shown). For example, some System-in-Package devices may have this function built-in, e.g., in the transmitter or receiver logic. The transmitted message payload 406 may include message data 403 including SPPS identification, the value of all the time stamped samples, status of the SPPS, RMS values of the input current and filtered current signals, and any other information required by the system.

During the transmission of the message data 403, which, depending on the implementation and selected bit rate of the transmitter, may take several hundreds of μsec (for example, a typical 240 bit message and a typical 250 Kbps transmission rate may take 960 μsec), the MC 107 determines Delta T 461 based on the stamp of the first sample T_S460 and the time stamped SYNC field transmission T₂411. Delta T value 461 may or may not take into account the various correction factors described above such as, but not limited to, the filter delay, the CT delay and the transmitter delay. Note that Delta T 461 is determined with the accuracy of the clock provided by the master clock 110. Before the end of transmission of the message data 403 field, the MC 107 inserts the Delta T value 461 in the data buffer being transmitted. Once the message data field 403 is transmitted, the message transmission continues with the transmission of the data field 404 which includes the Delta T value 461.

In one embodiment, additional auxiliary bits may be added to the message data 403 prior to the Delta T value 461 in order to allow sufficient time for the MC to determine Delta T value 461 and insert it to the message on the fly. The message 400 transmission is completed by transmitting a CRC field 405 which is used by the receiver to detect errors in the message payload 406 or CRC 405.

The transmitted message 400 may be received by a central controller 500 (e.g., a bridge) located at a wireless communication distance from SPPS 100. According to one embodiment, the communication distance may vary between a few to tens of meters. In such an embodiment, the propagation delay caused by the wireless link T_SBD432 is typically less than 0.2 μsec, which may be determined to be insignificant with respect to the phase delay accuracy required for the power factor computation. It should be appreciated that in some cases the propagation delay can also be accounted for as an additional correction factor to the ones mentioned herein and as will be shown further on.

When the central controller 500 receives the message 400, the controller 500 is configured to time stamp the reception of the SYNC field 402, denoted as T₃431 in FIG. 4. Following the SYNC field 402 reception by the central controller 500, the message data 403 and Delta T value 461 fields are received from the received message at Tr 433. Assuming the message was received without errors (this is checked with the CRC 405), the central controller 500 now has the T₃time stamp and the value of Delta T value 461 retrieved from the received message at Tr 433. According to one embodiment, the central controller 500 can now determine the time stamp of the first sample T_S460 of the primary current signal 102 in the SPPS 100, adjusted to the central controller 500 time base. The computation is as follows:

T_PFS=T₃+T_cycle−T_CTD−T_FD−(Delta T)−T_TD−T_RD−T_SBD

where, T_PFSis the time stamp of the first sample of the primary input signal 102 in the SPPS 100. The time stamp is according to the central controller 500 (e.g. bridge) time base (timer); T₃is the time stamp of the received SYNC field 402 at the central controller 500; T_cycleis the cycle time of the input signal (e.g., 20 msec for a 50 Hz signal); T_CTDis the time delay of the current transformer; T_FDis the time delay of the SPPS filter (if used); Delta T is the value of T₂−T_Sas determined by the SPPS 100; T_TDis the time delay of the SPPS transmitter; T_RDis the time delay of the central controller receiver (similar to T_TD); and T_SBDis the propagation time of the wireless message. Ignoring T_SBD432, which may be insignificant, the central controller 500 can further compute an accurate time stamp of the primary current signal zero-crossing at the SPPS 100 in its own time base using the time stamped samples received in the message.

It should be noted that wherever technically appropriate, the SPPS 200 or SPPS 300 may replace the SPPS 100 described herein, and the use of SPPS 100 is for convenience of description and not intended to limit the scope of the disclosure.

Since the SPPS 100 and central controller 500 have different clocks which are also unsynchronized, it is expected that time measurements in both units will not be identical. For example, in accordance of one embodiment, a 200-ppm clock drift between the SPPS 100 and the central controller 500 may be assumed. Furthermore, and as an example, if the value of Delta T (the interval between the time stamp of the first sample T_S460 and the SYNC transmission) is 15 msec, a typical 200 ppm drift generates an error of 3 μsec in the estimation of T_S460 by the central controller 500. In other words, if the central controller 500 generated a pulse at time T_szcit would have an offset of ˜3-4 μsec to a pulse generated by the SPPS at T_S. This error caused by the clock drift generates an error in the estimation of the time stamp of the first sample T_S460 and consequently in the zero-crossing estimation of around 0.05° for a 50 Hz signal.

It may be determined that this error is acceptable and therefore the clock drift is negligible and does not need to be taken into account in a typical embodiment. Nevertheless, it is possible to reduce this error by using one or more of the following methods: reduce the clock drift by selecting more accurate oscillators 110 in the SPPS 100 and central controller 500; measure and calibrate the SPPS oscillator 110 during manufacturing and transfer this information to the central controller 500; and, measure by the central controller 500 the clock drift by estimating the difference in the RF carriers (typically generated from the same oscillator).

The disclosed embodiments therefore enables a highly accurate time stamping by the central controller 500 of the time stamp of the first sample T_Sof a signal in the SPPS 100. This accuracy is achieved without a complicated synchronization mechanism between the SPPS and the central controller 500 and contemplating a case where the central controller 500 has to handle hundreds of SPPS 100 units periodically transmitting their respective time stamped samples as described. The time of the zero-crossing of the current input signal in the central controller 500 may be used to determine the time difference to the voltage signal zero-crossing and then determine cos(ϕ).

FIG. 5 is a block diagram of an exemplary central controller 500 according to a fourth embodiment. The central controller 500 includes an analog section that is coupled to a microcontroller (MC) 502. The analog section includes a signal conditioner 505 to adapt the voltage signal from the power line 515, to a signal suitable to be sampled by an analog-to-digital converter (ADC) 506. The signal conditioner 505 may also include a protection circuit (not shown) to protect the bridge from disturbances in the voltage line.

According to one embodiment, the primary voltage signal 515 is adapted by the signal conditioner 505 to a conditioned signal 516. The ADC 506 can sample the conditioned signal 516 with a sampling clock 513, which can be provided by a clock or timer 503. For example, this sampling clock 513 can be 3,200 Hz when sampling 50 Hz signals. In one embodiment, the clock or timer 503 is driven from a clock signal 511 provided by an oscillator 507. The samples 517 can be stored in the MC 502 of the central controller 500 or memory attached thereto (not shown) for further processing. In one embodiment, the MC 502 is configured to periodically program and activate the clock or timer 503 to trigger and provide the clock 513 for the sampling of the conditioned signal 516 by the analog-to-digital converter 506.

The number of samples may include a full cycle of the signal 516 (e.g. 64 samples when sampling a 50 Hz signal with a 3,200 Hz sampling clock). Once the samples 517 have been stored in the MC 502 or the attached memory (not shown), the MC 502 can process the samples together with the input current samples provided by an SPPS 100 to accurately determine the phase difference between input current and input voltage signals. Since the start of the sampling is triggered by the clock or timer function 513 rather than a software command from the MC 502, the time-stamp of all the samples can be accurately recorded.

According to one embodiment, without interrupting the clock or timer operation 503 (i.e., to avoid losing synchronization to the time-stamped samples), the central controller 500 may start receiving a wireless message 510 from an SPPS unit. For that purpose, the RF transceiver 501 is connected to the MC 502 and to an antenna 508 to provide one or two-way communication with an SPPS unit.

In one embodiment, the RF transceiver 501 supports reception only, i.e., uplink communication. Moreover, the method described herein is designed to enable accurate power factor measurement using only an uplink communication. This allows avoiding the activation of the SPPS in receive mode in order to save energy with a self-powered device. However, the RF transceiver 501 may include a transmitter portion to support features such as, and without limitation, clock synchronization with an SPPS, acknowledgement, firmware download, and configuration download. Typically, this should be an unlicensed industrial scientific medical (ISM) band transceiver, operative, for example and without limitation, at 2.4 GHz or Sub GHz frequencies.

In one embodiment, some form of spread-spectrum modulation technique may be used, for example and without limitation, direct sequence spread spectrum (DSSS), to enable better coexistence with other systems working in the same environment. The communication rate should be high enough to enable coexistence of a couple hundred SPPSs in the same electrical closet. The power consumption of the RF transceiver 501 should be low enough to adhere to energy harvesting limitations which may be used by an SPPS. Yet another requirement of the RF transceiver 501 is to support a communication range sufficient to operate in an electrical closet, e.g., 3-4 meters metallic reach environment.

In another embodiment, the range may reach up to a few tens of meters in an indoor environment. This enables the placing of SPPSs on individual devices, e.g., on machines in a production line of a factory, and a minimum number of bridge units in the area. The RF transceiver 501 preferably uses a standard PHY layer supporting, for example and without limitations, IEEE 802.15.4, and/or communication protocol, for example and without limitation, ZigBee. Use of such standards enables easy integration with existing systems that already include wireless hardware, for example and without limitations, smart meters.

According to one embodiment, when the central controller 500 starts receiving an incoming message transmitted by an SPPS 100, a logic in the receiver detects the reception of the SYNC field 402 and generates a pulse 512 which may be time stamped by the clock or timer 503. This time stamp is denoted T₃. Hence, having the input current samples with their respective time stamps and input voltage samples with their respective time stamps, wherein all the time stamps are related to the same time base, the central controller 500 can determine the time delay between the current and voltage signals.

Several methods are employed to estimate the phase shift between two sampled sine waves (i.e., current and voltage) having the same frequency. The embodiments disclosed herein may use some of the following methods according to the required performance (i.e., desired accuracy of the phase shift estimation), processing power available in the central controller, and other factors. Such methods include the following:

A) calculating a phase difference between the peaks or zero crossing of the signals. This method includes local linear interpolation around zero crossings or peaks, and allows resolution increase. Signal pre-processing before detection of crossings of zero level is often required in practice to prevent additional zero crossings caused by additive noise and/or signal higher harmonic components.

B) using discrete Fourier Transform (DFT). The phase difference between fundamental harmonic components of the two measured signals is found as the phase difference of the fundamental harmonics DFT phase spectrum values of the two measured signals. For sinusoidal signals, there is only one non-zero spectral line in the basic DFT spectrum interval if integer number of periods is sampled.

C) virtual vector-voltmeter. This method uses a multiplication of the signal by a reference signal (sinusoid of the same frequency as the measured signals) and finding a mean value (DC component) of this product. This mean value is proportional to the cosine of the phase difference between the fundamental harmonic component of the measured signal and the reference signal, the phase shift of which is considered to be zero.

D) sine-wave-fits: Sine-wave-fit techniques, based on least-square error (LSE) between (the samples of) the measured signal and (samples of) an ideal sinusoid. This sinusoid is characterized by the three parameters of magnitude, frequency and phase, and may include a fourth parameter of a nonzero DC component added, which are used for calculating the minimum LSE. If applied to both the input current and input voltage signals, the phase difference is obtained as the difference of phases of the both signals.

E) cross correlation of the signals. In this method, the phase difference between both signals is estimated by computing the cross correlation function and then finding the time T at which the cross correlation function reaches a maximum. In some cases, prior to the phase shift estimation, a signal conditioning may be required including filtering, equalization of amplitudes, direct current (DC) component removal and other techniques. According to one embodiment, the output of the processing described herein is the time difference T_VIDbetween the current and voltage signals.

The computed value T_VIDmay require an adjustment as follows (e.g., if it is determined the delay cannot be more than +/−0.25*T_cycle): if T_VID<0, then an integer number of quarter cycles is added (i.e., N*0.25*T_cycle) until the number is positive and <0.25*T_cycle; if T_VID>0.25*T_cycle, an integer number of quarter cycles is subtracted (i.e., N*0.25*T_cycle) until the number is positive and <0.25*T_cycle; and, if 0≤T_VID≤0.25*T_cycle, then no need to adjust T_VID.

In one embodiment, the cycle time of the input voltage signal (i.e., the power line frequency) may be estimated based on the time stamped samples 517. Since the line frequency is not expected to change at short intervals, this estimation may be performed at intervals of a minute or more. In another embodiment, as the line frequency is kept relatively constant by the power provider (for example, at a 50 Hz grid the frequency may not change by more than 0.25 Hz—i.e., 0.5%), a constant value of T_cyclecan be used and stored in the central controller 500 without measuring it periodically. In another embodiment, the central controller 500 may be periodically updated from a server though an Ethernet link 518, which can accurately measure the line frequency in a site and update all the central controllers 500 in the site. After the voltage-current delay has been determined, the phase difference ϕ between the input voltage and the input current is computed as follows:

ϕ[degrees]=360*(T_VID/T_cycle)

ϕ[radians]=27*(T_VID/T_cycle)

In one embodiment, the central controller 500 may also include a low pass filter, implemented as a digital filter in the MC or as an external filter (not shown), generating another signal (not shown) that contains only the fundamental frequency of the voltage. This signal will also be measured by the ADC 506 and then the ratio of Vf[RMS]/Vs can be computed [RMS]. However, in some cases this stage is not necessary, assuming the input voltage distortion is relatively negligible.

According to the disclosed embodiments, the power factor can then be computed in the central controller 500 using the computed cos ϕ as well as other parameters, including V_s[RMS], I_s[RMS], V_f[RMS], and I_f[RMS]. The power factor can then be used to determine the power consumption of the load. The central controller 500 can handle simultaneously the computation of cos ϕ for multiple SPPS units. According to one embodiment, the computed phase difference ϕ or the resulting cos ϕ or power factor may be sent by the central controller (e.g. bridge) 500 to a management server (not shown). This information, along with other parameters from both the SPPS 100 and the central controller (e.g. bridge) 500, such as (but not limited to) Vs[RMS], Is[RMS], Vf[RMS], and If[RMS] can be sent to the management server 519 using an Ethernet adapter 504 coupled to the MC 502.

Many other communication means may be used by the bridge to transfer this information to the server, including and without limitation, IEEE802.11/a/b/g/n/ac/ad networks, IEEE802.15.4, cellular 3G/4G/5G networks, USB, and their like.

FIG. 6 depicts an example flowchart 600 of a method for providing samples and synchronization information from an SPPS to a central controller according to an embodiment. The method starts after the SPPS has been initialized. As part of that initialization, a clock or timer 113 is programmed to send a wake-up trigger to the MC 107 at periodic intervals (e.g., every second).

At S602, it is determined if it is time to sample the input current signal. If so, the input current signal is sample at S605 (e.g., via the clock or timer 113 and the ADC 105). Otherwise, the method begins again.

After N samples (e.g., 32 samples for a 50 Hz signal) have been stored, e.g., in the MC 107 memory, the time of the start of the input signal cycle (Ts) is estimated. This is possible since the time when the sampling process began had been recorded. Having an estimate of the start of the cycle, a new sampling process is initiated (e.g., 32 samples for a 50 HZ signal via the clock or timer 113), but with the difference that the start of this sampling process is triggered by the clock or timer 113 itself (i.e., not by an MC command). The outcome of this hardware trigger is having an accurate time stamp of the new samples, limited only by the clock or timer accuracy.

According to one embodiment as depicted in flowchart 600, the RMS value of the input signal 102 and the RMS value of a filtered signal (i.e., the fundamental component) are computed. Those values may be determined using the respective signal samples and the filtered samples. This is needed to compute more accurately the power factor according to the following approximation:

P



F

=

If


[
RMS
]

Is


[
RMS
]

*

cos


(
φ
)

where I_s[RMS] is the RMS value of the input (non-filtered) signal; I_f[RMS] is the RMS value of the fundamental component of the input signal; cos (ϕ) is the displacement power factor, or the power factor of the fundamental signal; and, PF is the true power factor.

Upon determination that a transmission is to take place, a message is prepared to be transmitted. The message is typically a single packet of data that may contain various types of information and include the SPPS's unique identification (UID) which enables a central controller 500 to positively associate the current data received with previous data handled by the central controller with respect of the SPPS 100 (e.g., the message 400 of FIG.4).

At S612, without interrupting the clock or timer operation 113 (to avoid losing synchronization to the time-stamped samples), a wireless message is transmitted, e.g., to a central controller 500. The transmitted message may include different fields of information.

It should be noted that one of the message fields may be a SYNC field 402 which is typically transmitted following the message preamble 401. Once the message 400 transmission started, the MC waits, at S613, until the SYNC field is transmitted. When this happens, the time of the end of transmission of the SYNC field is sampled at S616, e.g., by the clock or timer 113.

The SYNC field 402 allows for accurate time-stamping by the clock or timer 113 of the message transmission time (T₂). The message 400 packet may include, without limitations, various SPPS status information, hardware version, software version, alerts such as overload, average current, SPPS temperature, time-stamped samples, input signal characteristics, power off indication, e.g., upon identification that the load was turned off, and other system parameters. According to one embodiment, the message 108 may include the time stamp of the first sample T_Sand the values of all the samples. While the message 108 is transmitted, the time difference between the SYNC field transmission T₂and the time stamp of the first sample T_Sof the sampled signal 106 is determined. This time is denoted as Delta T:

Delta T=T₂−T_S

It should be noted that the computation of Delta T may include handling the wraparound of the timer 113, between T_Sand T₂. In one embodiment, additional auxiliary bits may be added to the message data 403 prior to the Delta T value in order to allow sufficient time for the MC to determine delta T and insert it to the message on the fly. According to one embodiment, as depicted in flowchart 600, the MC 107 estimates Delta T and inserts this value and the values of I_sand I_f, in the message 400 packet being transmitted.

At S619, it is determined if the entire message has been transmitted and if so, at S622 it is checked if there is a need to continue signal sampling; if that is determined to be necessary, the flow returns to S602 to wait for the start of a new measurement cycle; otherwise it ends its execution. According to the implementation, this may incur reprogramming of the clock or timer 113 as previously explained.

Reference is now made to FIGS. 7 and 8, where FIG. 7 depicts an example flowchart of a method 700 for the calculation of root mean square information of an input voltage according to an embodiment, and FIG. 8 depicts an example flowchart of a method 800 for receiving synchronized samples from an SPPS according to an embodiment. For the sake of clarity, the flowcharts 700 and 800 only describe flow elements that are needed for the purpose of explaining the methods while other flow elements are omitted. Furthermore, merely for the sake of clarity, the flowcharts are divided into two parallel flows, flowchart 700 and flowchart 800. The two flows will be explained separately but it should be understood, that the flows are executed concurrently, for example, but not by way of limitation, by an operating system managing several tasks.

At S702 it is determined if it is time to start sampling the input voltage signal, e.g., signal 515. If so, at S705 the input voltage signal 515 is sampled, e.g., via the clock or timer 503 and the ADC 506; otherwise, execution resets.

At S706, the samples are stored, e.g., in a memory. This determination and storage is possible since the time when the sampling process has started has been recorded. The start of this sampling process maybe triggered by the clock or timer 503 itself (i.e., not by an MC command). The outcome of this hardware trigger is having an accurate time stamp of the new samples, limited only by the clock or timer accuracy.

At optional S708, the RMS value of the input voltage signal 515 is computed. Thereafter, at S709 it is checked whether to continue and if so execution continues with S702; otherwise, execution ceases.

According to an embodiment shown in flowchart 800, at S810 it is determined if there has been receipt of a new wireless message preamble. When a message preamble is detected, the incoming wireless message is received at S813, e.g., over wireless transmission. Following the receipt of the message preamble, it is determined if there is receipt of the SYNC field. If so, the end of the SYNC field reception is time stamped at S817. This time stamp may be denoted as T₃. At S818, it is determined if the message has been fully received. It then checked at S821 if the message has been received successfully without uncorrectable errors, e.g., cyclic redundancy code (CRC) errors. If the received message does contains uncorrectable errors, then the received message is discarded at S823 and the process continues with S828.

If the received message has no errors, then the values of I_sand I_fof the input current are decoded at S825 together with the value of Delta T. The management unit 500 can now calculate the time stamp of the first sample T_S460 of the primary current signal 102 in the SPPS 100, in accordance with the management unit 500 time base. The calculation is as follows:

T_PFS=T₃+T_cycle−T_CTD−T_FD−(Delta T)−T_TD−T_RD−T_SBD

where, T_PFSis the Time stamp of the first sample of the primary input signal 102 in the SPPS 100, the time stamp corresponding with the management unit 500 time base (timer); T₃is the time stamp of the received SYNC field 402 at the central controller 500; T_cycleis the cycle time of the input signal (e.g. 20 msec for a 50 Hz signal); T_CTDis the time delay of the current transformer; T_FDis the time delay of the SPPS filter (if used); Delta T is the value of Ts₂−Ts as computed by the SPPS 100; T_TDis the time delay of the SPPS transmitter; T_RD: Time delay of the bridge receiver; and, T_SBD: Propagation time of the wireless message.

In an embodiment, T_SBD432 can be ignored if it is determined to be insignificant, and the management unit 500 can calculate an accurate time stamp of the first sample of the primary current signal of SPPS 100 using its own time base. The management unit 500 can now calculate S825 the time delay T_VIDbetween the current and voltage signals since it has the input current samples with their respective time stamps and the input voltage samples with their respective time stamps, wherein all the time stamps are related to the management unit time base.

It should be noted that since the time stamp of the input voltage T_VZCmay be performed after or before the determined time stamp of the input current T_P_zc, the computed value T_VIDmay require an adjustment as follows (e.g., if it is determined that the delay cannot be more than +/−0.25*T_cycle): if T_VID<0, an integer number of quarter cycles is added (i.e. N*0.25*T_cycle) until the number is positive and <0.25*T_cycle; if T_VID>0.25*T_cycle, an integer number of quarter cycles is subtracted (i.e. N*0.25*T_cycle) until the number is positive and <0.25*T_cycle; and, if 0≤T_VID≤0.25*T_cycle, no adjustment is made to T_VID.

At S827, the values of T_VID, I_sand I_fof the input current signal and V_sof the input voltage signal are reported to a server. Such values allow a server to compute the power factor cos (ϕ). In another embodiment, the central controller 500 may report to the server the time stamped samples of both the input current and input voltage signals and have the server calculate a respective power factor. Once the reporting to the server at S827 is completed, it is checked whether to continue execution at S828, and if so, execution continues with S810, waiting for the reception of a new SPPS message; otherwise, execution terminates.

FIG. 9 is an example block diagram of a system 900 including a plurality of SPPSs 920 wirelessly connected to a central controller 930 according to an embodiment. The SPPS 920-1 to 920-N, where N is a positive integer, may be, for example, any one of the SPPSs shown in FIGS. 1 through 3, or others that may be adapted to perform the teachings of the instant disclosure. A power line 910 distributes current to the plurality of SPPS 920-1 through 920-N through distribution lines 910-1 through 910-N respectively.

A portion of each of the distribution lines 910-1 through 910-N that run through the core of their respective SPPSs 920-1 through 920-N act as a respective primary winding. Thereafter the line provides the current to respective loads (not shown) marked as L₁through L_N. The SPPSs 920 are wirelessly connected to a central controller 930, the operation of which has been discussed in detail elsewhere herein, for the transfer of packets with information of both electrical parameters and timing information. The central controller 930 is further connected to the power line 910 for the purpose of sampling the voltage signal as discussed in more detail elsewhere herein.

In one embodiment, the central controller 500 may be further connected to a network, which may include, but is not limited to, a local area network (LAN), wide area network (WAN), metro area network (MAN), the Internet, the worldwide web (WWW), wired or wireless networks, and the like. The central controller 930 may include a processor (not shown) and a memory (not shown) connected to the processor. More details are provided herein with respect of FIGS. 5 and 6. The memory may store therein a plurality of instructions that, when executed by the processor, perform the tasks described elsewhere herein. The central controller further includes one or more antennas for the wireless communication with the one or more SPPSs 920.

The various embodiments disclosed herein can be implemented as hardware, firmware, software, or any combination thereof. Moreover, the software is preferably implemented as an application program tangibly embodied on a program storage unit or computer readable medium consisting of parts, or of certain devices and/or a combination of devices. The application program may be uploaded to, and executed by, a machine comprising any suitable architecture. Preferably, the machine is implemented on a computer platform having hardware such as one or more central processing units (“CPUs”), a memory, and input/output interfaces. The computer platform may also include an operating system and microinstruction code. The various processes and functions described herein may be either part of the microinstruction code or part of the application program, or any combination thereof, which may be executed by a CPU, whether or not such a computer or processor is explicitly shown. In addition, various other peripheral units may be connected to the computer platform such as an additional data storage unit and a printing unit. Furthermore, a non-transitory computer readable medium is any computer readable medium except for a transitory propagating signal.

As used herein, the phrase “at least one of” followed by a listing of items means that any of the listed items can be utilized individually, or any combination of two or more of the listed items can be utilized. For example, if a system is described as including “at least one of A, B, and C,” the system can include A alone; B alone; C alone; A and B in combination; B and C in combination; A and C in combination; or A, B, and C in combination.

It should be understood that any reference to an element herein using a designation such as “first,” “second,” and so forth does not generally limit the quantity or order of those elements. Rather, these designations are generally used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements may be employed there or that the first element must precede the second element in some manner. Also, unless stated otherwise, a set of elements comprises one or more elements.

All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the disclosed embodiment and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the disclosed embodiments, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.