CROSS REFERENCE TO RELATED APPLICATION

The present application claims priority from Japanese Patent Application No. 2017-072999 filed on Mar. 31, 2017, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND
Field of the Invention

The present invention relates to a liquid jetting apparatus configured to jet liquid, for example, ink.

Description of the Related Art

There is conventionally known an ink-jet recording apparatus that drives recording elements of a recording head by using first drive power, second drive power greater than the first drive power, or a third drive power greater than the first drive power and smaller than the second drive power (e.g., see Japanese Patent Application laid-open No. 2013-154595).

The ink-jet recording apparatus firstly drives the recording elements by using the first drive power, then drives the recording elements by using the third drive power, and lastly drives the recording elements by using the second drive power. Gradually changing the drive power prevents rapid change in density of an image.

SUMMARY

An equal change amount is added to a current drive power every time the drive power changes. A certain amount of time is needed after the drive power is changed before a voltage value driving the recording elements stabilizes. When the change amount is large, the recording elements may be driven before the voltage value stabilizes, which may cause ink jetting failure.

The present teaching has been made in view of the above circumstances, and an object of the present teaching is to provide a liquid jetting apparatus configured to change a voltage value by using an appropriate change value when the voltage value to be output from a power source to each drive element is changed.

According to the present teaching, there is provided a liquid jetting apparatus including: a head including nozzles and driving elements arranged to correspond to the nozzles; a power source connected to the driving elements; and a control circuit connected to the power source. The control circuit determines whether an output voltage value of the power source is changed from a first voltage value to a second voltage value. When the control circuit has determined that the output voltage value is changed from the first voltage value to the second voltage value, the control circuit calculates an absolute value of a difference between the first voltage value and the second voltage value and compares the absolute value of the difference and a threshold value. When the absolute value of the difference is equal to or more than the threshold value, the control circuit determines a calculation voltage value smaller than the absolute value of the difference.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic plan view of a printing apparatus according to a first embodiment.

FIG. 2 is a schematic cross-sectional view taken along a line II-II depicted in FIG. 1.

FIG. 3 is a bottom view of an ink-jet head.

FIG. 4 is a schematic block diagram depicting connection between a controller and a head unit.

FIG. 5 is a schematic block diagram of a configuration in the vicinity of a power circuit.

FIG. 6 is a schematic circuit diagram of a configuration of a Complementary Metal-Oxide-Semiconductor (CMOS) circuit driving each nozzle.

FIG. 7 is an exemplary table indicating relations between ranks of first to sixth power circuits, the number of channels mapped to the respective ranks, and output voltages of the first to sixth power circuits mapped to the respective ranks.

FIG. 8 is a flowchart illustrating output-voltage change processing.

FIG. 9 is an exemplary timing chart that indicates the number of channels driven that is mapped to a rank 4.

FIG. 10 is a flowchart illustrating output-voltage change processing according to a second embodiment.

FIGS. 11A and 11B are a flowchart illustrating output-voltage change processing according to a third embodiment.

FIG. 12 is a flowchart illustrating output-voltage change processing according to a fourth embodiment.

FIG. 13 is an illustrative view of a first mode.

FIG. 14 is an illustrative view of a second mode.

DESCRIPTION OF THE EMBODIMENTS
First Embodiment

A printing apparatus according to a first embodiment is explained below with reference to the drawings.

In FIG. 1, a downstream side of a recording sheet 100 in a conveyance direction is defined as a front side of a printing apparatus 1, and an upstream side of the recording sheet 100 in the conveyance direction is defined as a rear side of the printing apparatus 1. A sheet width direction parallel to a surface on which the recording sheet 100 is conveyed (a surface parallel to a paper surface of FIG. 1) and orthogonal to the conveyance direction is defined as a left-right direction of the printing apparatus 1. The left side in FIG. 1 is the left side of the printing apparatus 1, and the right side in FIG. 1 is the right side of the printing apparatus 1. A direction perpendicular to the surface on which the recording sheet 100 is conveyed (a direction perpendicular to the paper surface of FIG. 1) is defined as an up-down direction of the printing apparatus 1. A front surface of FIG. 1 is the upper side, and a back surface of FIG. 1 is the lower side. In the following, the explanation is made by appropriately using the front, rear, left, right, up (upper), and down (lower) directions.

As depicted in FIG. 1, the printing apparatus 1 includes a casing 2, a platen 3, four ink-jet heads 4, two conveyance rollers 5 and 6, and a controller 7.

The platen 3 is placed in the casing 2. An upper surface of the platen 3 supports the recording sheet 100 conveyed by using any of the two conveyance rollers 5 and 6. The four ink-jet heads 4 are disposed above the platen 3 such that they are arranged in the front-rear direction. The conveyance roller 5 is disposed on the rear side of the platen 3 and the conveyance roller 6 is disposed on the front side of the platen 3. The two conveyance rollers 5 and 6 are driven by an unillustrated motor. The motor causes the two conveyance rollers 5 and 6 to convey the recording sheet 100 on the platen 3 frontward.

The controller 7 is connected to an external apparatus 9 such as a PC to perform data communication therebetween. The controller 7 controls parts or components of the printing apparatus 1 based on printing data sent from the external apparatus 9.

For example, the controller 7 controls the motor driving the two driving rollers 5 and 6 to cause the conveyance rollers 5 and 6 to convey the recording sheet 100 in the conveyance direction. Further, the controller 7 controls the ink-jet head 4 to jet ink onto the recording sheet 100 during conveyance of the recording sheet 100 by use of the two conveyance rollers 5 and 6. Accordingly, an image is printed on the recording sheet 100.

The casing 2 includes four head holders 8. The four head holders 8 are disposed above the platen 3 such that they are arranged in the front-rear direction between the two conveyance rollers 5 and 6. Each of the head holders 8 holds the corresponding one of the ink-jet heads 4.

The four ink-jet heads 4 respectively jet inks of four colors (cyan (C), magenta (M), yellow (Y), and black (K)). Each of the inks is supplied from the corresponding one of ink tanks (not depicted) to the corresponding one of the ink-jet heads 4.

As depicted in FIG. 2, each of the ink-jet heads 4 includes a holder 10 and head units 11. The holder 10 has a rectangular plate shape that is long in the sheet width direction. The holder 10 holds the head units 11.

A lower surface of each head unit 11 includes nozzles 11a. Each nozzle 11a communicates with a channel 11p (see FIG. 6). As depicted in FIG. 3, the nozzles 11a of the head unit 11 are arranged in the sheet width direction that is a longitudinal direction of the ink-jet head 4. The head units 11 are arranged zigzag in the conveyance direction and the sheet width direction (arrangement direction).

In the following, the head units 11 on the front side in the conveyance direction (the downstream side in the conveyance direction) form a first head row 81. The head units 11 on the rear side in the conveyance direction (the upstream side in the conveyance direction) form a second head row 82. As depicted in FIG. 3, a left end of each head unit 11 of the first head row 81 is substantially the same position as a right end of each head unit 11 of the second head row 82 in the left-right direction. Each head unit 11 is electrically connected to the controller 7.

As depicted in FIGS. 1 and 2, a reservoir 12 is arranged above the head units 11. The reservoir 12 is connected to the ink tank (not depicted) via a tube 16. The reservoir 12 temporarily contains the ink supplied from the ink tank. A lower portion of the reservoir 12 is connected to the corresponding head units 11. Each ink is supplied from the corresponding reservoir 12 to the corresponding head units 11.

As depicted in FIG. 4, the controller 7 includes a first substrate 71 and second substrates 72. The first substrate 71 includes a Field Programmable Gate Array (FPGA) 71a. Each second substrate 72 includes a FPGA 72a. As depicted in FIG. 5, the FPGA 72a includes a memory interface (memory I/F) 72b, a power interface (power I/F) 72c, and a receiving interface (receiving I/F) 72d.

The FPGA 71a is connected to the multiple FPGAs 72a to control driving of the multiple FPGAs 72a. The number of FPGAs 71a is the same as the number of ink-jet heads 4. The FPGAs 72a correspond to the head units 11, respectively. The FPGAs 72a are connected to the head units 11, respectively. Namely, the number of FPGAs 72a is the same as the number of head units 11 included in each ink-jet head 4.

As depicted in FIG. 4, each head unit 11 includes a substrate 11c. The substrate 11c includes a removable connector 11d, a non-volatile memory 11e, and a driver IC 11f. Each head unit 11 is removably connected to the corresponding second substrate 72 via the connector 11d. The driver IC 11f includes a switching circuit 27 described below.

As depicted in FIG. 5, the second substrate 72 includes a Digital/Analog (D/A) converter 20. The second substrate 72 includes a power circuit unit 73. The power circuit unit 73 includes power circuits, for example, a first power circuit 21 to a sixth power circuit 26. The first power circuit 21 to the sixth power circuit 26 each have a FET, a resistance, and the like to change output voltage. The second substrate 72 includes an A/D converter 74.

The first power circuit 21 to the sixth power circuit 26 are connected to the FPGA 72a via the D/A converter 20 and the A/D converter 74. The FPGA 72a outputs a signal for setting the output voltage to each of the first power circuit 21 to the sixth power circuit 26 via the D/A converter 20. Each of the first power circuit 21 to the sixth power circuit 26 inputs the output voltage to the FPGA 72a via the A/D converter 74 and the power I/F 72c.

As depicted in FIGS. 4 and 5, each of the first power source circuit 21 to the sixth power source circuit 26 is connected to any of power wires 34(n) (n=1, 2, . . . ) via the switching circuit 27 of the driver IC 11f. The number of power wires 34(n) corresponds to the number of pairs of piezoelectric bodies 11b, 11b′ described below, in other words, the number of channels 11p. Namely, the number of power wires 34(n) is equal to the number of channels 11p. The switching circuit 27 causes each of the power wires 34(n) to be connected to any of the first power circuit 21 to the sixth power circuit 26. For example, of the first power circuit 21 to the sixth power circuit 26, the first power circuit 21 has a highest output voltage, and the output side of the first power circuit 21 is connected to a terminal of HVDD and a terminal of VCOM.

As depicted in FIG. 6, the printing apparatus 1 includes a Complementary Metal-Oxide-Semiconductor (CMOS) circuit 30 driving the piezoelectric bodies 11b and 11b′. The number of CMOS circuits 30 corresponds to the number of pairs of the piezoelectric bodies 11b, 11b′. For example, the number of CMOS circuits 30 is equal to the number of pairs of the piezoelectric bodies 11b, 11b′. The FPGA 72a outputs a gate signal to the CMOS circuit 30 via control wires 33(n) (n=1, 2, . . . ). The control wires 33(n) correspond to the power wires 34(n).

For example, the FPGA 72a outputs, to the switching circuit 27, a signal for causing each of the power wires 34(n) to be connected to any of the first power circuit 21 to the sixth power circuit 26. The FPGA 72a accesses the non-volatile memory 11e via the memory I/F 72b. The non-volatile memory 11e stores information such as nozzle addresses for identifying the respective nozzles 11a and voltages corresponding to the respective nozzle addresses.

The external memory 75 stores bit stream information for executing voltage change processing described below. The FPGA 72a includes circuit components forming a logic circuit. The FPGA 72a receives the bit stream information from the memory 75 via the receiving I/F 72d. The FPGA 72a builds a connection relation between the circuit components based on the bit stream information received. This causes the FPGA 72a to form the logic circuit executing the voltage change processing. The non-volatile memory 11e may store the bit stream information. In that case, the FPGA 72a may receive the bit stream information via the memory I/F 72b.

As depicted in FIG. 6, the CMOS circuit 30 includes, for example, a P-type Metal-Oxide-Semiconductor (PMOS) transistor 31, a N-type Metal-Oxide-Semiconductor (NMOS) transistor 32, a resistance 35, and two piezoelectric bodies 11b, 11b′. The piezoelectric bodies 11b, 11b′ function as a capacitor. It is allowable to only provide the piezoelectric body 11b. A source terminal 31a of the PMOS transistor 31 is connected, for example, to the n-th power wire 34(n). A source terminal 32a of the NMOS transistor 32 is connected to the ground.

Drain terminals 31b, 32b of the PMOS transistor 31 and the NMOS transistor 32 are connected to a first end of the resistance 35. A second end of the resistance 35 is connected to a second end of the piezoelectric body 11b′ and to a first end of the piezoelectric body 11b. A first end of the piezoelectric body 11b′ is connected to the terminal of VCOM (a common power source) and a second end of the piezoelectric body 11b is connected to the ground.

Gate terminals 31c, 32c of the PMOS transistor 31 and the NMOS transistor 32 are connected to any of the control wires 33(1) to 33(n). Any of the control wires 33(1) to 33(n) corresponds to the power wire connected to the source terminal 31a of the PMOS transistor 31. The PMOS transistor 31 is connected to the terminal of HVDD (a power source on the drain-side).

The PMOS transistor 31 becomes conductive when the FPGA 72a inputs an “L” output signal to the gate terminal 31c of the PMOS transistor 31 and the gate terminal 32c of the NMOS transistor 32. This makes the piezoelectric body 11b a charge state and makes the piezoelectric body 11b′ a discharge state. The NMOS transistor 33 becomes conductive when the FPGA 72a inputs a “H” output signal to the gate terminal 31c of the PMOS transistor 31 and the gate terminal 32c of the NMOS transistor 32. This makes the piezoelectric body 11b the discharge state and makes the piezoelectric body 11b′ the charge state. The piezoelectric bodies 11b, 11b′ are deformed by making the piezoelectric body 11b the charge state and making the piezoelectric body 11b′ the discharge state. The deformation of the piezoelectric bodies 11b, 11b′ changes the volume in the channel 11p. The change in volume in the channel 11p jets ink from each nozzle 11a.

An exemplary relation between a rank of each of the first power circuit 21 to the sixth power circuit 26, the number of channels mapped to one of the ranks, and the output voltage of each of the first power circuit 21 to the sixth power circuit 26 having the corresponding one of the ranks is explained while referring to FIG. 7. FIG. 7 includes a table before output voltage is changed and a table after output voltage is changed. The table before output voltage is changed is stored in the memory 75 in advance. After output voltage is changed, the table after output voltage is changed is stored in the memory 75.

Each rank is determined depending on the speed of liquid droplets (ink droplets) jetted from each nozzle 11a. For example, the liquid droplet speed is set to have five speed widths so that the speed widths are mapped to a rank 1 to a rank 5, respectively. The nozzle address of each nozzle 11a is mapped to any of the ranks 1 to 5 and then stored in the non-volatile memory 11e. In this embodiment, the liquid droplet speed is used as an example, but it is possible to similarly use a jetting amount of liquid droplets instead of the liquid droplet speed.

The number of channels means the number of channels 11p mapped to each of the ranks. As described above, each of the channels 11p communicates with the corresponding one of nozzles 11a. Thus, the number of nozzles 11a mapped to each of the ranks corresponds to the number of channels.

Six power circuits are allocated to the five ranks. Two power circuits of the six power circuits are allocated to a rank having a largest number of the channels. For example, as indicated in the table before output voltage is changed in FIG. 7, two power circuits are allocated to the rank 2 having the largest number of the channels, and one power circuit is allocated to each of the ranks 1, and 3 to 5. The first power circuit 21 to the sixth power circuit 26 are connected to the respective channels 11p mapped to the respective ranks allocated.

Next, output-voltage change processing is explained while referring to FIG. 8. The FPGA 72a determines whether the change of output voltage of the power circuit that is connected to the nozzle 11a mapped to one of the ranks is requested (step S1). For example, when the temperature decreases or when the cumulative number of times of driving exceeds a threshold value, the increase in voltage is requested. On the other hand, for example, when the temperature increases, the decrease in voltage is requested. When the change of output voltage of the power circuit is not requested (step S1: NO), the FPGA 72a repeats the processing of the step S1.

When the change of output voltage of the power circuit that is connected to the nozzle 11a mapped to one of the ranks is requested (step S1: YES), the FPGA 72a reads a current output voltage Vp of the power circuit from the memory 75 (step S2). For example, when the change of output voltage of the power circuit, which is connected to 300 channels 11p mapped to the rank 4, is requested, the FPGA 72a reads 28.8 V (see FIG. 7) from the memory 75.

The FPGA 72a reads a post-change target output voltage Va from the memory 75 (step S3). For example, when the post-change target output voltage Va is 29.6 V, the FPGA 72a reads 29.6 V from the memory 75 (see FIG. 7). For example, when the post-change target output voltage Va is 28.0 V, the FPGA 72a reads 28.0 V from the memory 75 (see FIG. 7). The FPGA 72a calculates an absolute value of a difference between the Vp and the Va (step S4), and determines whether the absolute value of the difference calculated is equal to or more than a threshold value T1 (step S5).

The threshold value TI is stored in the memory 75 in advance. The average value of a current that drives the channels 11p is in proportion to a voltage to be applied to each channel 11p, a jetting frequency, a capacity of the piezoelectric bodies 11b, 11b′, the number of times of vibration of the piezoelectric bodies 11b, 11b′ during one period of the jetting frequency, the number of channels, and the like. The threshold value T1 is determined, for example, based on an equation or relation representing the above proportional relation.

When the difference calculated is equal to or more than the threshold value T1 (step S5: YES), the FPGA 72a sets T1 to a variable K (step S6). At the next printing timing, the FPGA 72a adds or subtracts the K to or from the Vp (step S8). Specifically, when Va>Vp is satisfied, the FPGA 72a adds the K (=T1) to the Vp. This changes, for example, the output voltage of the power circuit that is connected to 300 channels 11p mapped to the rank 4, from 28.8 V to 29.6 V. When Va<Vp is satisfied, the FPGA 72a subtracts the K (=T1) from the Vp. This changes, for example, the output voltage of the power circuit that is connected to 300 channels 11p mapped to the rank 4, from 28.8 V to 28.0 V.

When the difference calculated is less than the threshold value T1 (step S5: NO), the FPGA 72a sets an absolute value of the difference to the variable K (step S7). At the next printing timing, the K is added to or subtracted from the Vp (step S8). Specifically, when Va>Vp is satisfied, the FPGA 72a adds the K (=the absolute value of the difference) to the Vp. This changes, for example, the output voltage of the power circuit that is connected to 300 channels 11p mapped to the rank 4, from 28.8 V to 29.6 V. When Va<Vp is satisfied, the FPGA 72a subtracts the K (=the absolute value of the difference) from the Vp. This changes, for example, the output voltage of the power circuit that is connected to 300 channels 11p mapped to the rank 4, from 28.8 V to 28.0 V.

After the step S8, the FPGA 72a determines whether the current output voltage Vp is the target output voltage Va (step S9). When the current output voltage Vp is not the target output voltage Va (step S9: NO), the FPGA 72a calculates an absolute value of a difference between the Vp and the Va (step S10). The FPGA 72a determines whether the absolute value of the difference calculated is less than the threshold value T1 (step S11).

When the absolute value of the difference is equal to or more than the threshold value T1 (step S11: NO), the FPGA 72a makes the processing return to the step S6. When the absolute value of the difference is less than the threshold value T1 (step S11: YES), the FPGA 72a changes the current output voltage Vp into the target output voltage Va (step S12), and ends the processing.

In the step S9, when the current output voltage Vp is the target output voltage Va (step S9: YES), the FPGA 72a ends the processing.

In the first embodiment, when the output voltage value of the power circuit is changed from the current output voltage value Vp (a first voltage value) to the target output voltage value Va (a second voltage value), the FPGA 72a calculates an absolute value of a difference between the Vp and the Va. When the absolute value of the difference calculated is equal to or more than the threshold value T1 and when printing timing (first timing) has arrived, a calculation voltage value smaller than the absolute value of the difference, for example, the threshold value T1, is added to or subtracted from the Vp. Then, when next printing timing (second timing) has arrived, the calculation voltage value is added to or subtracted from the Vp. Since the calculation voltage value is smaller than the absolute value of the difference, the output voltage of the power circuit stabilizes in a short time after the addition or subtraction of the calculation voltage value.

When the difference calculated is less than the threshold value T1 and when printing timing (any of the first timing and the second timing) has arrived, the absolute value of the difference is added to or subtracted from the Vp. Since the absolute value of the difference is smaller than the threshold value T1, the output voltage of the power circuit stabilizes in a short time after the addition or subtraction of the absolute value of the difference.

The output voltage may be changed at the timing described below. As depicted in FIG. 7, the number of channels 11p driven that is mapped to the rank 4 is 300 before output voltage is changed.

The FPGA 72a reads, in advance, the number of channels 11p driven that is mapped to the rank 4 by a predefined number of times of printing, for example, 50 to 300 times of printing. Then, the FPGA 72a determines a period T (see FIG. 9) during which the number of channels 11p driven that is mapped to the rank 4, which has been read in advance, is equal to or less than a half of the predefined number of times of printing (e.g., 150 or less). The FPGA 72a changes the output voltage during the period T obtained.

Since the output voltage is changed during the period T having a small number of channels 11p driven, it is possible to minimalize the influence on density of the image formed on the recording sheet 100.

Second Embodiment

In the following, a printing apparatus according to a second embodiment of the present teaching is described below with reference to FIG. 10. The FPGA 72a determines whether or not the change of output voltage of the power circuit that is mapped to one of the ranks is requested (step S21). When the change of output voltage of the power circuit is not requested (step S21: NO), the FPGA 72a repeats the processing of step S21.

When the change of output voltage of the power circuit is requested (step S21: YES), the FPGA 72a reads, from the controller 7, a jetting frequency F after voltage is changed (step S22). The jetting frequency F is the inverse of a jetting period during which liquid is jetted from the nozzles 11a. The jetting period is time required to jet the liquid from the nozzle 11a by an amount corresponding to one jetting. The jetting frequency F is determined based on printing data transmitted from the external apparatus 9 to the controller 7.

After the step S22, the FPGA 72a reads the current output voltage Vp of the power circuit from the memory 75 (step S23), and reads the post-change target output voltage Va from the memory 75 (step S24). For example, when the output voltage of the power circuit that is connected to 300 channels 11p mapped to the rank 4 is changed from 28.8 V to 29.6 V, the FPGA 72a operates as follows. Namely, the FPGA 72a reads the current output voltage of 28.8 V from the memory 75 (step S23) and reads the post-change target output voltage of 29.6 V from the memory 75 (step S24). For example, when the output voltage of the power circuit that is connected to 300 channels 11p mapped to the rank 4 is changed from 28.8 V to 28.0 V, the FPGA 72a operates as follows. Namely, the FPGA 72a reads the current output voltage of 28.8 V from the memory 75 (step S23) and reads the post-change target output voltage of 28.0 V from the memory 75 (step S24).

The FPGA 72a determines whether the jetting frequency F read in the step S22 is equal to or more than a threshold value T2 (step S25). The threshold value T2 is stored in the memory 75 in advance. The threshold value T2 is determined, for example, based on an equation or relation representing the above proportional relation.

When the jetting frequency F is less than the threshold value T2 (step S25: NO), the FPGA 72a changes the current output value Vp into the target output value Va (step S31) and ends the processing. When the jetting frequency F is equal to or more than the threshold value T2 (step S25: YES), the FPGA 72a calculates a calculation voltage value ΔV (ΔV≥0) (step S26). The calculation voltage value ΔV is calculated, for example, by ΔV_max/(F/T2) when a maximum value of a voltage change value is ΔV_max.

At the next printing timing, the FPGA 72a adds or subtracts the ΔV to or from the Vp (step S27). Specifically, when Va>Vp is satisfied, the FPGA 72a adds the ΔV to the Vp. This changes, for example, the output voltage of the power circuit that is connected to 300 channels 11p mapped to the rank 4, from 28.8 V to 29.6 V. When Va<Vp is satisfied, the FPGA 72a subtracts the ΔV from the Vp. This changes, for example, the output voltage of the power circuit that is connected to 300 channels 11p mapped to the rank 4, from 28.8 V to 28.0 V. The FPGA 72a determines whether the Vp is the Va (step S28). When the Vp is the Va (step S28: YES), the FPGA 72a ends the processing.

When the Vp is not the Va (step S28: NO), the FPGA 72a calculates an absolute value of a difference between the Va and the Vp (step S29) and determines whether the ΔV is larger than the absolute value of the difference (step S30). When the ΔV is equal to or less than the absolute value of the difference (step S30: NO), the FPGA 72a makes the processing return to the step S27. When the ΔV is larger than the absolute value of the difference (step S30: YES), the FPGA 72a changes the Vp into Va (step S31) and ends the processing.

As depicted in FIG. 9, the FPGA 72a may change the output voltage during a period during which the number of channels 11p driven that are mapped to the rank before output voltage is changed, which has been read in advance, becomes equal to or less than a half thereof or a period during which the total number of channels 11p driven that are mapped to the ranks before and after output voltage is changed is the smallest.

In the second embodiment, when the output voltage value of the power circuit is changed from the current output voltage value Vp (the first voltage value) to the target output voltage value Va (the second voltage value), the jetting frequency is compared to the threshold value T2. When the jetting frequency is equal to or more than the threshold value T2, the ΔV (the calculation voltage value) that is smaller than the absolute value of the difference between the Vp and the Va is determined. When the Va is larger than the Vp and when printing timing (the first timing) has arrived, the ΔV is added to the Vp. When the Va is smaller than the Vp and when the printing timing has arrived, the ΔV is subtracted from the Vp. Then, when next printing timing (the second timing) has arrived, the ΔV is added to the Vp or the ΔV is subtracted from the Vp. Since the ΔV is smaller than the voltage value of the difference, the output voltage of the power circuit stabilizes in a short time after addition or subtraction of the ΔV.

When the jetting frequency is less than the threshold value T2, the Vp is changed to the Va. In other words, the absolute value of the difference between the Vp and the Va is added to or subtracted from the Vp. When the jetting frequency is less than the threshold value T2, the difference between the Vp and the Va is small. Thus, the output voltage of the power circuit stabilizes in a short time when the Vp is directly changed to the Va.

The parts or components in the second embodiment that are the same as or equivalent to those of the first embodiment, are designated by the same reference numerals, and any explanation therefor will be omitted as appropriate.

Third Embodiment

A printing apparatus according to a third embodiment of the present teaching is explained below with reference to FIGS. 11A and 11B. The FPGA 72a determines whether the change of output voltage of the power circuit is requested (step S41). When the change of output voltage of the power circuit is not requested (step S41: NO), the FPGA 72a repeats the processing of step S41.

When the change of output voltage of the power circuit is requested (step S41: YES), the FPGA 72a sets a maximum value M of the rank (five in the third embodiment) to a variable n (step S42), and determines whether the change of output voltage of a rank n is requested (step S43). The rank with a large numerical value has an output voltage value that is larger than that of the rank with a small numerical value, and the rank with the large numerical value has a great influence on the density of the image. Thus, the output voltage value of the rank with the large numerical value is changed preferentially.

When the change of the output voltage of the rank n is not requested (step S43: NO), the FPGA 72a subtracts one from the maximum value M (step S53), sets the maximum value M after subtraction to the rank n (step S54), and determines whether the rank n is 0 (step S55). When the rank n is 0 (step S55: YES), the FPGA 72a ends the processing. When the rank n is not 0 (step S55: NO), the FPGA 72a makes the processing return to the step S43.

When the change of output voltage of the rank n is requested in the step S43 (step S43: YES), the FPGA 72a reads the current output voltage Vp of the power circuit from the memory 75 (step S44), and reads the post-change target output voltage Va from the memory 75 (step S45). Then, the FPGA 72a reads the number of channels D of the rank n (step S46, see FIG. 7) and determines whether the number of channels D is equal to or more than a threshold value T3 (step S47). The threshold value T3 is stored in the memory 75 in advance.

For example, when the output voltage of the power circuit that is connected to 300 channels 11p mapped to the rank 4 is changed from 28.8 V to 29.6 V, the FPGA 72a operates as follows. Namely, the FPGA 72a reads the current output voltage of 28.8 V from the memory 75 (step S44), and reads the post-change target output voltage of 29.6 V from the memory 75 (step S45). Then, the FPGA 72a reads the number of channels mapped to the rank 4 (here, 300) (step S46), and determines whether the number of channels read (here, 300) is equal to or more than the threshold value T3 (step S47).

For example, when the output voltage of the power circuit that is connected to 300 channels 11p mapped to the rank 4 is changed from 28.8 V to 28.0 V, the FPGA 72a operates as follows. Namely, the FPGA 72a reads the current output voltage of 28.8 V from the memory 75 (step S44), and reads the post-change target output voltage of 28.0 V from the memory 75 (step S45). Then, the FPGA 72a reads the number of channels mapped to the rank 4 (here, 300) (step S46), and determines whether the number of channels read (here, 300) is equal to or more than the threshold value T3 (step S47).

When the number of channels D is less than the threshold value T3 (step S47: NO), the Vp is changed to the Va (step S52) and the FPGA 72a makes the processing proceed to the step S53. When the number of channels D is equal to or more than the threshold value T3 (step S47: YES), the FPGA 72a calculates the calculation voltage value ΔV (ΔV≥0) (step S48). The calculation voltage value ΔV is, for example, calculated by a relation (the absolute value of the difference between the Va and the Vp)/(the number of channels D/T3).

At the next printing timing, the FPGA 72a adds or subtracts the ΔV to or from the Vp (step S49). Specifically, when Va>Vp is satisfied, the FPGA 72a adds the ΔV to the Vp. This changes, for example, the output voltage of the power circuit that is connected to 300 channels 11p mapped to the rank 4, from 28.8 V to 29.6 V. When Va<Vp is satisfied, the FPGA 72a subtracts the ΔV from the Vp. This changes, for example, the output voltage of the power circuit that is connected to 300 channels 11p mapped to the rank 4 from 28.8 V to 28.0 V. The FPGA 72a determines whether the Vp is the Va (step S50). When the Vp is the Va (step S50: YES), the FPGA 72a makes the processing proceed to the step S53.

When the Vp is not the Va (step S50: NO), the FPGA 72a determines whether the ΔV is larger than the absolute value of the difference between the Va and the Vp (step S51). When the ΔV is equal to or less than the absolute value of the difference between the Va and the Vp (step S51: NO), the FPGA 72a makes the processing return to the step S49.

When the ΔV is larger than the absolute value of the difference between the Va and the Vp (step S51: YES), the Vp is changed to the Va (step S52). Then, the FPGA 72a executes the processing subsequent to the step S53.

As depicted in FIG. 9, the FPGA 72a may change the output voltage during a period during which the number of channels 11p driven that are mapped to the rank before output voltage is changed, which has been read in advance, becomes equal to or less than a half thereof or a period during which the total number of channels 11p driven that are mapped to the ranks before and after output voltage is changed is the smallest.

In the third embodiment, when the output voltage value of a power circuit (a specific power source) that is mapped to the rank n is changed from the Vp (the first voltage value) to the Va (the second voltage value), the number of channels 11p of the power circuit that is mapped to the rank n is compared to the threshold value T3 (a predefined number). When the number of channels 11p is equal to or more than the threshold value T3, the ΔV (the calculation voltage value) that is smaller than the absolute value of the difference between the Vp and the Va is determined. The ΔV is calculated, for example, by a relation (the absolute value of the difference between the Va and the Vp)/(the number of channels D/T3). When the Va is larger than the Vp and when printing timing (the first timing) has arrived, the ΔV is added to the Vp. When the Va is smaller than the Vp and when the printing timing has arrived, the ΔV is subtracted from the Va. Then, when the next printing timing (the second timing) has arrived, the ΔV is added to or subtracted from the Vp. Since the ΔV is smaller than the absolute value of the difference, the output voltage of the power circuit stabilizes in a short time after addition or subtraction of the ΔV.

When the number of channels D is less than the threshold value T3, the Vp is changed to the Va. In other words, the absolute value of the difference between the Vp and the Va is added to or subtracted from the Vp. When the number of channels D is less than the threshold value T3, the difference between the Vp and the Va is small. Thus, the output voltage of the power circuit stabilizes in a short time after the Vp is directly changed to the Va.

The parts or components in the third embodiment that are the same as or equivalent to those of the first or second embodiment, are designated by the same reference numerals, and any explanation therefor will be omitted as appropriate.

Fourth Embodiment

A printing apparatus according to a fourth embodiment of the present teaching is explained with reference to FIGS. 12 to 14.

The FPGA 72a determines whether multiple channels 11p mapped to a predefined rank are requested to change the rank (step S61). When the change of the rank is not requested (step S61: NO), the FPGA 72a repeats the processing of the step S61.

When the change of the rank is requested (step S61: YES), the FPGA 72a reads the ranks before and after change (step S62). For example, the rank 2 is read as the rank before change and the rank 4 is read as the rank after change (see FIGS. 13 and 14). The FPGA 72a reads the channel 11p to be changed (step S63). For example, the FPGA 72a accesses the memory 75 to refer to the nozzle addresses and reads the channel 11p to be changed that is mapped to the rank 2.

The FPGA 72a calculates an absolute value of a difference between the output voltage mapped to the rank after change and the output voltage mapped to the rank before change (step S64). For example, the FPGA 72a calculates the absolute value of the difference between the output voltage mapped to the rank 4 and the output voltage mapped to the rank 2 (see FIGS. 13 and 14). Then, the FPGA 72a calculates the number of channels 11p to be changed based on printing data sent from the external apparatus 9 (step S65) and reads the jetting frequency F of the rank after change (step S66). The FPGA 72a calculates a current change amount ΔI (ΔI≥0) based on the absolute value of the difference between the output voltages calculated, the number of channels 11p to be changed that has been calculated, and the jetting frequency F (step S67). The ΔI is obtained by a formula or relation in proportion to the absolute value of the difference between the output voltages, the number of channels 11p, the jetting frequency F, and the like.

The FPGA 72a determines whether the current change amount ΔI is equal to or more than the threshold value T4 (step S68). The threshold value T4 is stored in the memory 75 in advance. When the current change amount ΔI is less than the threshold value T4 (step S68: NO), the FPGA 72a executes a first mode. In the first mode, the FPGA 72a changes the rank of the channel 11p to be changed, into a target rank (step S69). For example, 300 channels 11p mapped to the rank 2 are changed to have the rank 4 at once (see FIG. 13).

When the current change amount ΔI is equal to or more than the threshold value T4 (step S68: YES), the FPGA 72a executes a second mode to change the rank of the channel 11p to be changed, by one (step S70). For example, as depicted in FIG. 14, 800 channels 11p mapped to the rank 2 are changed to have the rank 3 before being changed to have the rank 4 (see the table before change and the table after change 1 in FIG. 14).

The FPGA 72a determines whether the rank after change is the target rank (step S71). When the rank after change is the target rank (step S71: YES), the FPGA 72a ends the processing. When the rank after change is not the target rank (step S71: NO), the FPGA 72a makes the processing return to the step S70 and changes the rank of the channel 11p to be changed, by one. For example, as depicted in FIG. 14, the channel 11p, of which rank was changed from the tank 2 to the rank 3 in the step S70, is changed to have the rank 4 (see the table after change 1 and the table after change 2 in FIG. 14).

The case in which the output voltage of the power circuit is increased (e.g., the case in which the rank is changed from the rank 2 to the rank 4) is explained in the fourth embodiment. The fourth embodiment, however, can be applied similarly to a case in which the output voltage of the power circuit is decreased (e.g., a case in which the rank is changed from the rank 4 to the rank 2).

As depicted in FIG. 9, the FPGA 72a may change the rank during a period during which the number of channels 11p driven that are mapped to the rank before change, which has been read in advance, becomes equal to or less than a half thereof or a period during which the total number of channels 11p driven that are mapped to the ranks before and after change is the smallest.

In the fourth embodiment, for example, when a channel group connected to the power circuit mapped to the rank 2 is connected to the power circuit mapped to the rank 4, the first mode or the second mode is executed. In the first mode, the channel group is connected to the power circuit mapped to the rank 4. In the second mode, the channel group is firstly connected to the power circuit mapped to the rank 3 and then connected to the power circuit mapped to the rank 4. The output voltage value of the power circuit mapped to the rank 3 is a value between the output voltage value of the power circuit mapped to the rank 2 and the output voltage value of the power circuit mapped to the rank 4. The first mode causes the channel group to be connected directly to the power circuit mapped to the rank 4. The second mode gradually changes the voltage to be applied to the channel group, and the output voltage of the power circuit stabilizes in a short time.

Further, for example, the current change amount ΔI of the channel group to be changed that is mapped to the rank 2 is calculated based on any of the number of channels 11p, the jetting frequency of the channels 11p mapped to the ranks 2 to 4, and the difference between the output voltage value of the power circuit mapped to the rank 2 and the output voltage value of the power circuit mapped to the rank 4. When the current change amount ΔI calculated is less than the threshold value T4, the first mode is executed. When the ΔI is less than the threshold value T4, the current change amount ΔI is small. Thus, the output voltage of the power circuit stabilizes in a short time even when the channel group is connected directly to the power circuit mapped to the rank 4. When the current change amount ΔI is equal to or more than the threshold value T4, the second mode is executed. When the ΔI is equal to or more than the threshold value T4, the current change amount ΔI is large. Thus, when the channel group is connected directly to the power circuit mapped to the rank 4, the output voltage of the power circuit needs a long time for its stabilization. Thus, the output voltage of the power circuit can stabilize in a short time by gradually changing the voltage that is to be supplied to the channel group.

The parts or components in the fourth embodiment that are the same as or equivalent to those of the first to third embodiments, are designated by the same reference numerals, and any explanation therefor will be omitted as appropriate.

The embodiments disclosed above should be considered as exemplary, but not as limitary in each and every aspect. It is possible to mutually combine the technical characteristics described in the respective embodiments, and the scope of those embodiments is intended to include all changes within the scope of the appended claims and an equal scope to the scope of the appended claims.