TECHNICAL FIELD

This relates generally to semiconductor wafer processing and more particularly to the prevention of counter-doping during high temperature processing.

BACKGROUND

Anneals of semiconductor wafers for extended times at temperatures greater than or equal to 1000° C. are frequently required to form high resistance buried diffusions or to form low doping concentration deep n-type diffused wells especially for semiconductor wafers used for high voltage integrated circuit (IC) chips. Semiconductor wafers used to form integrated circuits include silicon, gallium arsenide, and other III-V materials used for integrated circuit manufacture. Most semiconductor wafers are silicon. Epitaxial semiconductor layers can be formed over silicon wafers and over other wafer types. During a high temperature anneal, volatile dopant atoms such as boron or phosphorus may out-diffuse from the walls of the anneal furnace or dopant atoms may out-diffuse from highly doped regions on the semiconductor wafer and counter-dope low doped regions elsewhere on the same semiconductor wafer, or on an adjacent wafer. The counter-doping may change the resistance of the low doped regions sufficiently to cause circuits on the semiconductor wafer to fail.

A cross section of a partially processed semiconductor wafer for manufacturing integrated circuits (ICs) 100 is shown in FIG. 1A. A lightly doped p-type epitaxial layer (P-EPI) 104 overlies a heavily doped p-type substrate (P+SUBSTRATE) 102. The p-type dopant is typically boron.

An n-type well (N WELL) 108 is formed in an upper portion of the P-EPI layer 104. The n-type dopant may be phosphorus or arsenic.

A p-type well (P WELL) 109 may also be formed in the upper portion of the P-EPI layer 104. P WELL 109 may be lightly doped with a dopant concentration slightly greater than the P-EPI layer 104 or may be medium doped with a dopant concentrations substantially higher than the P-EPI layer 104.

A first oxide layer 110 overlies the P-EPI layer 104 and N WELL 108. A second oxide layer 106 underlies the P+SUBSTRATE 102.

Silicon nitride layer 112 covers the oxide layer 106 on the backside of the semiconductor wafer. Silicon nitride is an effective barrier to volatile dopants such as boron and phosphorus. If the silicon nitride layer 112 is damaged by scratches or is defective and has defects prior to the high temperature anneal, out-diffusion of dopant atoms will occur from P+SUBSTRATE 102. Depositing silicon nitride layer 116 on the top side oxide layer 110 prior to a high temperature anneal prevents boron atoms that can diffuse out of the backside of the P+SUBSTRATE 102 from counter-doping N WELL 108 and from adding additional dopant to the P WELL 109 during the high temperature anneal. High temperature anneals {e.g., >=1000 degrees Celsius) are used for various processes such as formation of the diffused N WELL 108.

In other examples, semiconductor wafers with lightly doped regions may become counter-doped by the out-diffusion of volatile dopant atoms from highly doped regions on the same wafer or from a nearby wafer. Improvements are therefore needed.

SUMMARY

In a described example, a semiconductor wafer with a backside silicon nitride layer is encapsulated with a diffusion barrier layer prior to a high temperature anneal. After the high temperature anneal the diffusion barrier layer and the backside silicon nitride layers are stripped. In another described example, the thickness of an oxide layer on the topside of a semiconductor wafer is increased prior to encapsulation with a diffusion barrier silicon nitride layer or with a diffusion barrier silicon oxynitride layer. The use of the increased oxide thickness compensates for any oxide loss that may occur during the subsequent strip of the diffusion barrier layer. The increased oxide thickness is used when oxide thickness is critical to subsequent processing steps such as a photo-lithography process step. After a high temperature anneal the diffusion barrier silicon nitride layer or the diffusion barrier silicon oxynitride layer and a backside silicon nitride layer are stripped.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A through 1C are cross sections of a semiconductor wafer during processing steps according to an embodiment method.

FIG. 2 is a flow diagram of a method embodiment.

FIGS. 3A through 3D are cross sections of a semiconductor wafer during processing steps according to another embodiment.

FIG. 4 is a flow diagram of a method embodiment.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are not necessarily drawn to scale.

If the backside silicon nitride layer 112 in FIG. 1A is scratched, the underlying silicon dioxide layer 106 may be exposed. During a high temperature anneal (e.g. >=1000° C.) boron atoms may out diffuse from the P+SUBSTRATE 102; diffuse through the silicon dioxide layer 106; diffuse through the scratch; and then counter-dope N WELL 108 or additionally dope the P WELL 109. The counter-doping of the N WELL 108 or the additional doping of the P WELL 109 may change the resistance sufficiently to cause the integrated circuits formed on the semiconductor wafer 100 to fail.

The backside silicon nitride layer 112 is deposited using low pressure chemical vapor deposition (LPCVD). A typical furnace recipe for depositing this LPCVD nitride is to flow about 600 sccms of ammonia (NH₃) plus about 80 sccms of dichloro-silane (SiH₂cl₂) at a pressure of about 300 mTorr. The deposition temperature can be about 700° C. Other process conditions can also be used.

One solution for preventing counter-doping of an integrated circuit wafer during annealing at high temperatures (e.g., >=1000° C.) is illustrated in cross sections of semiconductor wafer 100 in FIGS. 1A through 1C and in the flow diagram in FIG. 2.

If semiconductor wafer 100 shown in FIG. 1A is annealed at a high temperature in a furnace in which highly doped n-type wafers have previously been annealed, volatile n-type dopant atoms such as phosphorus may out-diffuse from the walls of the furnace and counter-dope the lightly doped P-EPI region 104 and the P WELL region 109. The change in resistance caused by the counter-doping may cause the integrated circuits formed on the wafer 100 to fail.

If semiconductor wafer 100 is annealed at a high temperature in a furnace in which highly doped p-type wafers have previously been annealed, volatile p-type dopant atoms such as boron may out-diffuse from the walls of the furnace and counter-dope the N WELL 108 region and may additionally dope the P WELL 109. The change in N WELL 108 resistance caused by the counter-doping may cause the integrated circuits formed on the semiconductor wafer 100 to fail. An example is a low threshold voltage PMOS transistor. The change in resistance of the P WELL 109 caused by the additional doping may cause the integrated circuits formed on semiconductor wafer 100 to fail. An example is a low threshold voltage NMOS transistor.

In the embodiments, a solution to prevent counter-doping is to encapsulate the semiconductor wafer with a diffusion barrier layer, such as a silicon nitride layer or a silicon oxynitride layer, prior to the high temperature anneal. The diffusion barrier layer is removed after the high temperature anneal is completed. A silicon nitride diffusion barrier layer is used to illustrate the embodiments. Other diffusion barriers can be used with the embodiments.

In step 202 of the flow diagram in FIG. 2 and in the cross section in FIG. 1B, a diffusion barrier layer 116 is deposited encapsulating semiconductor wafer 100. The diffusion barrier layer 116 may be Si₃N₄deposited with a recipe optimized to improve thickness uniformity across the semiconductor wafer 100 and optimized to minimize or eliminate diffusion barrier layer 116 defects.

The diffusion barrier silicon nitride layer 116 may be deposited with a thickness in the range of about 30 nm to 80 nm. More preferably the diffusion barrier silicon nitride layer 116 may be deposited with a thickness in the range of about 40 nm to 60 nm. In an example embodiment the diffusion barrier silicon nitride layer 116 is deposited with a thickness of about 50 nm.

In a typical diffusion barrier silicon nitride layer deposition recipe the flow rates of NH₃and SiH₂Cl₂are in a ratio of about 10:1. The NH₃flow rate may be in the range of about 600 sccm and 1200 sccm. The deposition pressure may be in the range of about 200 mTorr to about 300 mTorr. The deposition temperature may be in the range of about 695° C. to about 715° C. In an example diffusion barrier silicon nitride layer 116 recipe, the flow of NH₃is about 600 sccms and the flow of SiH₂cl₂is about 60 sccms. The deposition pressure is about 300 mTorr. The deposition temperature is about 700° C. Useful deposition rates can be achieved from about 0.60 nm/min to about 0.75 nm/min. In an example process the deposition rate is about 0.67 nm/min.

In FIG. 2, in step 204 the semiconductor wafer is annealed at a high temperature of greater than or equal to 1000° C.

In step 206 the diffusion barrier layer 116 (FIG. 1B) and the backside nitride layer 112 (FIG. 1B) that encapsulate the wafer are stripped. Dilute hot phosphoric acid (dilH₃PO₄) is typically used to strip the silicon nitride layers.

FIG. 1C is a cross section of the semiconductor wafer 100 after the diffusion barrier layer 116 and the backside nitride layer 112 are removed. Depending upon the selectivity of the selected dilH₃PO₄solution to silicon dioxide, between about 10 nm and 20 nm of topside oxide layer 110 may be etched away during the silicon nitride strip process. The semiconductor wafer 100 is now ready to continue processing in step 208 in FIG. 2.

FIGS. 3A-3B show in cross sectional views an alternative embodiment. When silicon nitride layers are exposed to an ambient containing oxygen in an anneal furnace, the surface of the backside silicon nitride layer 112 may oxidize. Since dilH₃PO₄is very selective to surface oxide 318 (see FIG. 3A), the surface oxide 318 is typically removed prior to stripping a silicon nitride layer 312. The surface oxide layer 318 (FIG. 3A) may be removed with a dilute hydrofluoric (dilHF) deglaze prior to the dilH₃PO₄silicon nitride strip.

A surface layer of oxide 318 may grow on the backside nitride layer 312 prior to deposition of the encapsulating diffusion barrier silicon nitride layer 316 (FIG. 3B). When this occurs, a short dilHF deglaze may be required after the diffusion barrier nitride layer 316 is stripped, to remove the surface oxide 318 and to ensure complete stripping of the backside silicon nitride layer 312. About 15 nm of the topside oxide layer 304 may be etched away by the short dilHF deglaze. The change in thickness of the topside oxide layer 304 may cause problems for subsequent process steps. For example, during a photolithography step, reflections may be sensitive to the thickness of the topside oxide layer 304.

FIGS. 3A through 3D and flow diagram in FIG. 4 illustrate an embodiment process that compensates for the loss of topside oxide layer 310.

Semiconductor wafer 300 in FIG. 3A corresponds to the semiconductor wafer 100 in FIG. 1A. As shown in FIG. 3A and at step 402 of FIG. 4 a layer of compensation oxide 314 with a thickness in the range of about 10 nm to 20 nm is deposited or grown on the topside oxide layer 310 prior to encapsulation with the diffusion barrier silicon nitride 316. The thickness of the compensation oxide layer 314 depends upon the etch rate of the compensation oxide 314. In an example approximately 15 nm of compensation oxide 314 is thermally grown. This oxidation may also form a surface oxide 318 on the backside nitride layer 312.

In step 404 (illustrated in FIG. 3B) a diffusion barrier silicon nitride layer 316 that is described hereinabove is deposited. Typically the diffusion barrier silicon nitride layer 316 is deposited using LPCVD with a recipe optimized to improve across wafer thickness uniformity and to reduce or eliminate diffusion barrier silicon nitride layer 316 defects.

The diffusion barrier silicon nitride layer 316 may be deposited with a thickness in the range of about 30 nm to 80 nm. More preferably the diffusion barrier silicon nitride layer 316 may be deposited with a thickness in the range of about 40 nm to 60 nm. In an example solution the diffusion barrier silicon nitride layer 316 is deposited with a thickness of about 50 nm.

In step 406 the encapsulated semiconductor wafer 300 is annealed at a high temperature equal to or greater than 1000° C.

In step 408 the encapsulating diffusion barrier silicon nitride layer 316 is stripped.

If needed, in step 410 a dilHF deglaze may be performed to remove surface oxide 318 from the backside silicon nitride layer 312. As is illustrated in the cross section in FIG. 3C, the compensation oxide layer 314 may also be etched away during this dilHF deglaze step.

In step 412 an additional dilH₃PO₄strip is performed to remove the backside silicon nitride layer 312. The cross section in FIG. 3D shows semiconductor wafer 300 after completion of the backside silicon nitride layer 312 strip.

The semiconductor wafer is now ready for further processing in step 414.

An additional benefit of depositing and removing the diffusion barrier silicon nitride layer 316 is that the semiconductor wafer 300 has significantly fewer particles and defects than semiconductor wafers that go through the high temperature anneal without the diffusion barrier silicon nitride layer 316. This aspect of the embodiment methods results in higher integrated circuit yield.

Modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims.