CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of co-pending U.S. patent application Ser. No. 15/281,173, filed Sep. 30, 2016, entitled “PERFORM SIGN OPERATION DECIMAL INSTRUCTION,” which is hereby incorporated herein by reference in its entirety.

BACKGROUND

One or more aspects relate, in general, to processing within a computing environment, and in particular, to improving such processing.

Applications executing within a processor of a computing environment control the behavior of the processor. The applications are created using programming languages which are designed to communicate instructions to the processor. There are various types of programming languages, and each language may use one or more types of encodings to represent data.

For example, binary coded decimal (BCD) is a native data type encoding in the programming languages COBOL and PL/I, and is also a supported data type in the DB2 database management system. Through language and class library extensions, other languages, such as C and Java, also support some forms of BCD data types.

One computational BCD type, packed decimal, has an encoding that specifies one decimal digit encoded in every 4 bits of storage except for the least significant 4 bits of the least significant byte where a 4 digit sign code is encoded. The sign code can be any non-numeric 4 bit value covering the hexadecimal values 0xA through 0xF. For example, the value +123 can be encoded in two bytes of storage as hexadecimal 12 3C.

A display BCD type, zoned decimal, shares this type of sign encoding as well. The value +123 in zoned decimal is encoded in three bytes of storage as hexadecimal F1 F2 C3. The sign code overlays the most significant 4 bits of the least significant byte.

The mapping of sign codes to a sign value is as follows:

0xA: +

0xB: −

0xC: + (selected plus encoding)

0xD: − (selected minus encoding)

0xE: +

0xF: + (selected unsigned encoding)

As noted above, certain sign codes are designated as the canonical or selected encodings. This means that although any of these signs are accepted on input, the compiler produced code is to produce the selected encodings on output (according to how the data type was declared—signed variables use 0xC or 0xD, and unsigned variables use 0xF).

Unsigned variables are not “signless”, but instead they can have any (even a minus encoding) on input, but to adhere to language rules, the compiler produced code is to generate an 0xF sign code on output for an expression (including simple moves and before compares, in addition to arithmetic expressions).

To perform a sign operation for an output datum, multiple instructions are used.

SUMMARY

Shortcomings of the prior art are overcome and additional advantages are provided through the provision of a computer-implemented method of facilitating processing in a computing environment. The method includes, for instance, obtaining an instruction for execution. The instruction to perform a sign operation of a plurality of sign operations is configured for the instruction. The instruction is executed. The executing includes selecting at least a portion of an input operand as a result to be placed in a select location. The selecting is based on a control of the instruction. The control of the instruction indicating a user-defined size of the input operand to be selected as the result. A sign of the result is determined based on a plurality of criteria. The plurality of criteria includes a value of the result, obtained based on the control of the instruction, having a first particular relationship or a second particular relationship with respect to a selected value. The result and the sign are stored in the select location to provide a signed output to be used in processing within the computing environment.

Computer program products and systems relating to one or more aspects are also described and claimed herein. Further, services relating to one or more aspects are also described and may be claimed herein.

Additional features and advantages are realized through the techniques described herein. Other embodiments and aspects are described in detail herein and are considered a part of the claimed aspects.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more aspects are particularly pointed out and distinctly claimed as examples in the claims at the conclusion of the specification. The foregoing and objects, features, and advantages of one or more aspects are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1A depicts one example of a computing environment to incorporate and use one or more aspects of the present invention;

FIG. 1B depicts further details of the processor of FIG. 1A, in accordance with an aspect of the present invention;

FIG. 2A depicts another example of a computing environment to incorporate and use one or more aspects of the present invention;

FIG. 2B depicts further details of the memory of FIG. 2A;

FIG. 3A depicts one example of a Vector Perform Sign Operation Decimal instruction, in accordance with an aspect of the present invention;

FIG. 3B depicts one embodiment of controls of an immediate field of the Vector Perform Sign Operation Decimal instruction of FIG. 3A, in accordance with an aspect of the present invention;

FIG. 3C depicts one embodiment of a mask field of the Vector Perform Sign Operation Decimal instruction of FIG. 3A, in accordance with an aspect of the present invention;

FIG. 3D depicts one embodiment of a control of another immediate field of the Vector Perform Sign Operation Decimal instruction of FIG. 3A, in accordance with an aspect of the present invention;

FIG. 4 depicts one example of a table of result sign codes for different sign operations and results, in accordance with an aspect of the present invention;

FIG. 5 depicts one example of processing associated with the Vector Perform Sign Operation Decimal instruction, in accordance with an aspect of the present invention;

FIGS. 6A-6B depict one example of facilitating processing in a computing environment, including execution of the Vector Perform Sign Operation Decimal instruction, in accordance with an aspect of the present invention;

FIG. 7 depicts one embodiment of a cloud computing environment; and

FIG. 8 depicts one example of abstraction model layers.

DETAILED DESCRIPTION

One or more aspects relate to improving processing within a computing environment by providing a capability for replacing multiple instructions to be used to perform a sign operation with a single instruction (e.g., a single architected machine instruction at the hardware/software interface). In one example, the instruction, referred to herein as a Vector Perform Sign Operation Decimal instruction, flexibly and compactly handles various sign setting and exception maintaining/suppressing behaviors.

One embodiment of a computing environment to incorporate and use one or more aspects of the present invention is described with reference to FIG. 1A. In one example, the computing environment is based on the z/Architecture, offered by International Business Machines Corporation, Armonk, N.Y. One embodiment of the z/Architecture is described in “z/Architecture Principles of Operation,” IBM Publication No. SA22-7832-10, March 2015, which is hereby incorporated herein by reference in its entirety. Z/ARCHITECTURE is a registered trademark of International Business Machines Corporation, Armonk, N.Y., USA.

In another example, the computing environment is based on the Power Architecture, offered by International Business Machines Corporation, Armonk, N.Y. One embodiment of the Power Architecture is described in “Power ISA™ Version 2.07B,” International Business Machines Corporation, Apr. 9, 2015, which is hereby incorporated herein by reference in its entirety. POWER ARCHITECTURE is a registered trademark of International Business Machines Corporation, Armonk, N.Y., USA.

The computing environment may also be based on other architectures, including, but not limited to, the Intel x86 architectures. Other examples also exist.

As shown in FIG. 1A, a computing environment 100 includes, for instance, a node 10 having, e.g., a computer system/server 12, which is operational with numerous other general purpose or special purpose computing system environments or configurations. Examples of well-known computing systems, environments, and/or configurations that may be suitable for use with computer system/server 12 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices, and the like.

Computer system/server 12 may be described in the general context of computer system-executable instructions, such as program modules, being executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, and so on that perform particular tasks or implement particular abstract data types. Computer system/server 12 may be practiced in many computing environments, including but not limited to, distributed cloud computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media including memory storage devices.

As shown in FIG. 1A, computer system/server 12 is shown in the form of a general-purpose computing device. The components of computer system/server 12 may include, but are not limited to, one or more processors or processing units 16, a system memory 28, and a bus 18 that couples various system components including system memory 28 to processor 16.

Bus 18 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example, and not limitation, such architectures include Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA) bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

Computer system/server 12 typically includes a variety of computer system readable media. Such media may be any available media that is accessible by computer system/server 12, and it includes both volatile and non-volatile media, removable and non-removable media.

System memory 28 can include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and/or cache memory 32. Computer system/server 12 may further include other removable/non-removable, volatile/non-volatile computer system storage media. By way of example only, storage system 34 can be provided for reading from and writing to a non-removable, non-volatile magnetic media (not shown and typically called a “hard drive”). Although not shown, a magnetic disk drive for reading from and writing to a removable, non-volatile magnetic disk (e.g., a “floppy disk”), and an optical disk drive for reading from or writing to a removable, non-volatile optical disk such as a CD-ROM, DVD-ROM or other optical media can be provided. In such instances, each can be connected to bus 18 by one or more data media interfaces. As will be further depicted and described below, memory 28 may include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of embodiments of the invention.

Program/utility 40, having a set (at least one) of program modules 42, may be stored in memory 28 by way of example, and not limitation, as well as an operating system, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data or some combination thereof, may include an implementation of a networking environment. Program modules 42 generally carry out the functions and/or methodologies of embodiments of the invention as described herein.

Computer system/server 12 may also communicate with one or more external devices 14 such as a keyboard, a pointing device, a display 24, etc.; one or more devices that enable a user to interact with computer system/server 12; and/or any devices (e.g., network card, modem, etc.) that enable computer system/server 12 to communicate with one or more other computing devices. Such communication can occur via Input/Output (I/O) interfaces 22. Still yet, computer system/server 12 can communicate with one or more networks such as a local area network (LAN), a general wide area network (WAN), and/or a public network (e.g., the Internet) via network adapter 20. As depicted, network adapter 20 communicates with the other components of computer system/server 12 via bus 18. It should be understood that although not shown, other hardware and/or software components could be used in conjunction with computer system/server 12. Examples, include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc.

For example, processor 16 includes a plurality of functional components used to execute instructions. As depicted in FIG. 1B, these functional components include, for instance, an instruction fetch component 120 to fetch instructions to be executed; an instruction decode unit 122 to decode the fetched instructions and to obtain operands of the decoded instructions; instruction execution components 124 to execute the decoded instructions; a memory access component 126 to access memory for instruction execution, if necessary; and a write back component 130 to provide the results of the executed instructions. One or more of these components may, in accordance with an aspect of the present invention, be used to perform a sign operation 136, as described further below.

Processor 16 also includes, in one embodiment, one or more registers 140 to be used by one or more of the functional components.

Another embodiment of a computing environment to incorporate and use one or more aspects is described with reference to FIG. 2A. In this example, a computing environment 200 includes, for instance, a native central processing unit (CPU) 202, a memory 204, and one or more input/output devices and/or interfaces 206 coupled to one another via, for example, one or more buses 208 and/or other connections. As examples, computing environment 200 may include a PowerPC processor or a pSeries server offered by International Business Machines Corporation, Armonk, N.Y.; an HP Superdome with Intel Itanium II processors offered by Hewlett Packard Co., Palo Alto, Calif.; and/or other machines based on architectures offered by International Business Machines Corporation, Hewlett Packard, Intel, Oracle, or others.

Native central processing unit 202 includes one or more native registers 210, such as one or more general purpose registers and/or one or more special purpose registers used during processing within the environment. These registers include information that represent the state of the environment at any particular point in time.

Moreover, native central processing unit 202 executes instructions and code that are stored in memory 204. In one particular example, the central processing unit executes emulator code 212 stored in memory 204. This code enables the computing environment configured in one architecture to emulate another architecture. For instance, emulator code 212 allows machines based on architectures other than the z/Architecture, such as PowerPC processors, pSeries servers, HP Superdome servers or others, to emulate the z/Architecture and to execute software and instructions developed based on the z/Architecture.

Further details relating to emulator code 212 are described with reference to FIG. 2B. Guest instructions 250 stored in memory 204 comprise software instructions (e.g., correlating to machine instructions) that were developed to be executed in an architecture other than that of native CPU 202. For example, guest instructions 250 may have been designed to execute on a z/Architecture processor, but instead, are being emulated on native CPU 202, which may be, for example, an Intel Itanium II processor. In one example, emulator code 212 includes an instruction fetching routine 252 to obtain one or more guest instructions 250 from memory 204, and to optionally provide local buffering for the instructions obtained. It also includes an instruction translation routine 254 to determine the type of guest instruction that has been obtained and to translate the guest instruction into one or more corresponding native instructions 256. This translation includes, for instance, identifying the function to be performed by the guest instruction and choosing the native instruction(s) to perform that function.

Further, emulator 212 includes an emulation control routine 260 to cause the native instructions to be executed. Emulation control routine 260 may cause native CPU 202 to execute a routine of native instructions that emulate one or more previously obtained guest instructions and, at the conclusion of such execution, return control to the instruction fetch routine to emulate the obtaining of the next guest instruction or a group of guest instructions. Execution of the native instructions 256 may include loading data into a register from memory 204; storing data back to memory from a register; or performing some type of arithmetic or logic operation, as determined by the translation routine.

Each routine is, for instance, implemented in software, which is stored in memory and executed by native central processing unit 202. In other examples, one or more of the routines or operations are implemented in firmware, hardware, software or some combination thereof. The registers of the emulated processor may be emulated using registers 210 of the native CPU or by using locations in memory 204. In embodiments, guest instructions 250, native instructions 256 and emulator code 212 may reside in the same memory or may be disbursed among different memory devices.

As used herein, firmware includes, e.g., the microcode, millicode and/or macrocode of the processor. It includes, for instance, the hardware-level instructions and/or data structures used in implementation of higher level machine code. In one embodiment, it includes, for instance, proprietary code that is typically delivered as microcode that includes trusted software or microcode specific to the underlying hardware and controls operating system access to the system hardware.

A guest instruction 250 that is obtained, translated and executed is, for instance, a Vector Perform Sign Operation Decimal instruction described herein. The instruction, which is of one architecture (e.g., the z/Architecture), is fetched from memory, translated and represented as a sequence of native instructions 256 of another architecture (e.g., PowerPC, pSeries, Intel, etc.). These native instructions are then executed.

As indicated herein, there are many possible encodings for the various combinations of signed and unsigned variable types and operations (e.g. moves, complement, negation, absolute value, etc.). One challenge for a compiler is how to efficiently generate code to cover the many possible encodings. A related challenge for a hardware design is how to compactly encode all these various possibilities to fit within instruction encoding limits and also to not pollute a fixed set of possible operation encodings in an architecture with many existing and future instructions.

As BCD variables traditionally are operated on by storage to storage (SS) instructions, setting the sign code often involves additional in-memory operations that can slow down modern out-of-order (OOO) processors.

An additional challenge is how to be sensitive to generating compatible results in exceptional cases. For example, one language or environment may dictate that a hardware exception is provided if an input sign code is not legal (e.g., a numeric digit in a sign code position for an unsigned variable), but for strict compatibility in other cases, the illegal encoding is to be ignored and just treated as unsigned (as the value +vs− is not actually in question for unsigned variables).

Many sign setting operations, even for simple moves of a variable to another, use at least two machine instructions: one to move the data, and one or more subsequent instructions to set the sign. Since the sign cannot be set until after the data has been moved, a data dependency is established that can further slow down OOO processors.

As an example, when an unsigned variable is to be widened, one sequence is to use a ZAP instruction for the widening followed by an OI (OR Immediate) or MVN (Move Numerics) to set the sign to 0xF (as ZAP will set only 0xC or 0xD). This is already two instructions. Further, since ZAP validates the input sign codes, even this sequence cannot be used, as an undesired hardware exception may occur if the input sign code is not legal. Instead, an even longer and more expensive sequence is used in order to achieve compatibility for this type of unsigned variable widening behavior.

Thus, in accordance with one or more aspects of the present invention, an instruction (e.g., a single architected machine instruction at the hardware/software interface) is provided to flexibly and compactly handle the various sign setting and exception maintaining/suppressing behaviors. This instruction, referred to herein as the Vector Perform Sign Operation Decimal instruction, has an input and one output operand plus the ability to perform many sign manipulations and settings as part of the move of the data from the input to the output (instead of as a post operation).

In embodiments, the instruction has a flexible sign control and a sign validation control to allow fine tuning of perform sign operation behavior in exception cases of, e.g., invalid sign codes. In a further embodiment, the instruction may include or have access to a control to selectively check the validity of the numeric digits, as well. Other variations are also possible.

The Vector Perform Sign Operation Decimal instruction encoding has several parts that combine to compactly achieve flexible and fine grained sign setting control for a large range of operations and input/output types.

These parts include, for instance:

- 1) Specifying the input and output operands. As examples, the operands are specified in registers; however, an in-memory encoding (e.g., specifying a base+displacement) is also a possible embodiment, as well as other embodiments.
- 2) Result Digits Count (RDC): A number (e.g., 1 to 31 or 1 to 64 depending on maximum allowed sizes) to specify how many of the rightmost digits from the input operand to place in the output operand location. Both truncation and widening operations are possible. An overflow indicator may be raised if significant digits are lost depending on system settings.
- 3) Sign Operation (SO): This part of the instruction encoding determines the particular sign operation being performed. For example, SO can indicate:
  - a simple move is happening so the sign code should be maintained from input to output;
  - that the sign code should be complemented (switched from positive to negative or negative to positive) from input to output;
  - the input sign code should be forced to positive on output regardless of the input sign value (i.e., an absolute value type operation);
  - the input sign code should be forced to negative on output regardless of the input sign value.
- 4) Positive Sign Code (PC): This part of the instruction encoding controls whether the output sign code, for result values that are positive, should be encoded as 0xF (1111 in binary) or 0xC (1100 in binary).
- 5) Input Operand Sign Validation (SV): This part of the instruction encoding controls if sign validation (and a corresponding hardware exception for illegal sign codes) should occur for force positive and force negative sign operations. This control allows users of the perform sign decimal operation to maintain strict exception compatibility in the presence of possible illegal sign encodings.
- This type of control may be used, e.g., when performing binary translation (sometimes called binary optimization) where strict compatibility to the original behavior, even in the presence of illegal code/data, is to be maintained. In one embodiment, the setting SV=0 for force positive and negative sign operations indicates to skip the validity checking, and SV=1 indicates to check for invalid signs (and in this embodiment validity checking occurs for sign operations that inherently use, versus overwrite, the input sign code in some way).
- 6) Condition Code Set (CS): The Vector Perform Sign Operation Decimal instruction also allows for the user to request that condition codes be set based on the final result value. Settings to indicate a result value of zero, less than zero, and greater than zero are provided, as well as an indication if there was overflow (truncation of significant digits) as part of the operation.

In one embodiment, all the above settings can be encoded in just 6 bytes (which also includes the opcode and RXB, described below) of encoding text with several bits remaining for future enhancements.

The result sign code is determined, in one example, by the combination of e.g., the sign operation (SO), second operand sign, the result digits count (RDC), and positive sign code (PC) settings.

The settings and additional details of the Vector Perform Sign Operation Decimal instruction are described below. In one embodiment, the Vector Perform Sign Operation Decimal instruction is part of a vector facility, which provides, for instance, fixed sized vectors ranging from one to sixteen elements. Each vector includes data which is operated on by vector instructions defined in the facility. In one embodiment, if a vector is made up of multiple elements, then each element is processed in parallel with the other elements. Instruction completion does not occur until processing of all the elements is complete. In other embodiments, the elements are processed partially in parallel and/or sequentially.

Vector instructions can be implemented as part of various architectures, including, but not limited to, the z/Architecture, the Power Architecture, x86, IA-32, IA-64, etc. Although embodiments described herein are for the z/Architecture, the vector instruction described herein and one or more other aspects may be based on many other architectures. The z/Architecture is only one example.

In one embodiment in which the vector facility is implemented as part of the z/Architecture, to use the vector registers and instructions, a vector enablement control and a register control in a specified control register (e.g., control register 0) are set to, for instance, one. If the vector facility is installed and a vector instruction is executed without the enablement controls set, a data exception is recognized. If the vector facility is not installed and a vector instruction is executed, an operation exception is recognized.

In one embodiment, there are 32 vector registers and other types of registers can map to a quadrant of the vector registers. For instance, a register file may include 32 vector registers and each register is 128 bits in length. Sixteen floating point registers, which are 64 bits in length, can overlay the vector registers. Thus, as an example, when floating point register 2 is modified, then vector register 2 is also modified. Other mappings for other types of registers are also possible.

Vector data appears in storage, for instance, in the same left-to-right sequence as other data formats. Bits of a data format that are numbered 0-7 constitute the byte in the leftmost (lowest-numbered) byte location in storage, bits 8-15 form the byte in the next sequential location, and so on. In a further example, the vector data may appear in storage in another sequence, such as right-to-left.

One example of a Vector Perform Sign Operation Decimal instruction is described with reference to FIGS. 3A-3D. As shown, the instruction has a plurality of fields, and a field may have a subscript number associated therewith. The subscript number associated with a field of the instruction denotes the operand to which the field applies. For instance, the subscript number 1 associated with vector register V₁denotes that the register in V₁includes the first operand, and so forth. A register operand is one register in length, which is, for instance, 128 bits.

Referring to FIG. 3A, in one embodiment, a Vector Perform Sign Operation Decimal instruction 300 includes opcode fields 302a, 302b indicating a vector perform sign operation decimal operation; a first vector register field 304 used to designate a first vector register (V₁); a second vector register field 306 used to designate a second vector register (V₂); a first immediate field (14) 308; a mask field (M₅) 310; a second immediate field (I₃) 312; and a register extension bit (RXB) field 314, each of which is described below. In one embodiment, the fields are separate and independent from one another; however, in other embodiments, more than one field may be combined. Further information regarding these fields is described below.

Vector register field 304 is used to indicate a vector register that is to store the first operand, the first operand including a modified sign generated by the instruction and a specified number of digits of the second operand. The operand and the result are, e.g., in the signed packed decimal format. In one example, in the signed packed decimal format, each byte contains two decimal digits (D), except for the rightmost byte, which contains a sign (S) to the right of a decimal digit.

The second operand (i.e., the input operand) is contained in the vector register specified using vector register field 306. In one example, each of vector register fields 304, 306 is used with RXB field 314 to designate the vector register.

For instance, RXB field 314 includes the most significant bit for a vector register designated operand. Bits for register designations not specified by the instruction are to be reserved and set to zero. The most significant bit is concatenated, for instance, to the left of the four-bit register designation of the vector register field to create a five-bit vector register designation.

In one example, the RXB field includes four bits (e.g., bits 0-3), and the bits are defined, as follows:

- 0—Most significant bit for the first vector register designation (e.g., in bits 8-11) of the instruction.
- 1—Most significant bit for the second vector register designation (e.g., in bits 12-15) of the instruction, if any.
- 2—Most significant bit for the third vector register designation (e.g., in bits 16-19) of the instruction, if any.
- 3—Most significant bit for the fourth vector register designation (e.g., in bits 32-35) of the instruction, if any.

Each bit is set to zero or one by, for instance, the assembler depending on the register number. For instance, for registers 0-15, the bit is set to 0; for registers 16-31, the bit is set to 1, etc.

In one embodiment, each RXB bit is an extension bit for a particular location in an instruction that includes one or more vector registers. For instance, bit 0 of RXB is an extension bit for location 8-11, which is assigned to, e.g., V₁and so forth. In particular, for vector registers, the register containing the operand is specified using, for instance, a four-bit field of the register field with the addition of its corresponding register extension bit (RXB) as the most significant bit. For instance, if the four bit field is 0110 and the extension bit is 0, then the five bit field 00110 indicates register number 6. In a further embodiment, the RXB field includes additional bits, and more than one bit is used as an extension for each vector or location.

Immediate (I₄) field 308 specifies a fourth operand that includes a number of controls. For instance, I₄field 308 includes the following, as depicted in FIG. 3B:

- Reserved: Bits 0-3 are ignored, but are to contain zeros; otherwise, the program may not operate compatibly in the future.
- Sign Operation (SO) 342: Bits 4-5 specify the sign operation used in determining the result sign code. The result sign code is a function of, e.g., the SO control, the second operand sign, the second operand digits, the RDC control, and the PC bit, as specified in FIG. 4.
- Positive Sign Code (PC) 344: When bit 6 is one, sign code 1111 is used when the result is positive. When bit 6 is zero, sign code 1100 is used when the result is positive.
- Operand 2 Sign Validation (SV) 346: If bit 7 is one and the SO control specifies force positive or force negative, then the second operand sign code is checked for validity. If bit 7 is zero and the SO control specifies force positive or force negative, then the second operand sign code is not checked for validity. When the SO control specifies maintain or complement sign, the second operand sign code is checked for validity, regardless of the SV bit value.

M₅field 310 includes, in one example, the following control, as depicted in FIG. 3C:

- Reserved: Bits 0-2 are ignored, and are to contain zeros; otherwise, the program may not operate compatibly in the future.
- Condition Code Set (CS) 348: When bit 3 is zero, the condition code is not set and remains unchanged. When bit 3 is one, the condition code is set as specified in the resulting condition code section below.

Resulting Condition Code:

When the CS bit is one, the condition code is set as follows, in one example:

0 Result zero; no overflow

1 Result less than zero; no overflow

2 Result greater than zero; no overflow

3 Overflow

When the CS bit is zero, the condition code remains unchanged.

I₃field 312 includes, in one example, the following control, as depicted in FIG. 3D:

- Reserved: Bits 0-2 are reserved, and are to contain zeros. Otherwise, a specification exception is recognized.
- Result Digits Count (RDC) 350: Bits 3-7 contain an unsigned binary number specifying the number of rightmost digits of the second operand to be placed in the first operand. If the magnitude of the second operand is larger than the largest decimal number that can be represented with the specified number of digits, decimal overflow occurs, and if a decimal-overflow mask is one, a program interruption for decimal overflow occurs, in one example. If the RDC field is zero, a specification exception is recognized, in one embodiment.

Although various fields and registers are described, one or more aspects of the present invention may use other, additional or less fields or registers, or other sizes of fields or registers, etc. Many variations are possible. For instance, implied registers may be used instead of explicitly specified registers or fields of the instruction. Further, registers other than vector registers may be used. Additionally, in other embodiments, other digits may be selected, such as the leftmost digits or another subset. Again, other variations are also possible.

In operation of one embodiment of the Vector Perform Sign Operation Decimal instruction, the modified sign and specified number of rightmost digits of the second operand are placed in the first operand location with other digits set to zero. The operand and result are in the signed packed decimal format, in one example.

If the RDC control does not specify enough digits to contain all leftmost nonzero digits of the second operand, decimal overflow occurs. The operation is completed. The result is obtained by ignoring the overflow digits, and if the condition code set (CS) flag is one, condition code 3 is set. If a decimal overflow mask, in, e.g., a program status word, is one, a program interruption for decimal overflow occurs.

If the RDC control specifies less than, e.g., thirty one digits, zeros are placed in the remaining leftmost digits of the first operand.

All digit codes of the second operand are checked for validity, in one example. The sign code of the second operand is checked for validity, unless the sign operation (SO) control specifies the result sign be forced positive or negative, and the operand 2 sign validation (SV) control is zero.

The result sign code is a function of, e.g., the SO control, the second operand sign, the second operand digits, the result digits count (RDC) control, and the positive sign code (PC) control, as specified in FIG. 4. For instance, if SO (400)=00, the value of the digits of the second operand after RDC is applied (402) is nonzero, the second operand sign (V₂) (404) is positive, and PC (406) is one, the resulting sign code (408) is hex F (positive) 410. Additionally, it shows that in this example, a validity check is performed 412 for the input operand sign code.

Although various examples are provided, variations are possible without departing from a spirit of the claimed aspects. For example, values that are included in registers and/or fields used by the instruction may, in other embodiments, be in other locations, such as memory locations, etc. Many other variations are possible.

Further details regarding processing associated with executing a Vector Perform Sign Operation Decimal instruction are described with reference to FIG. 5. The processing is performed by at least one processor.

Referring to FIG. 5, initially the value of the second operand is obtained, STEP 500. In one example, the value of the second operand includes a plurality of digits, and a determination is made as to whether those digits are valid, INQUIRY 502. If the digits are not valid, then processing of the Vector Perform Sign Operation Decimal instruction is complete. However, if the digits are valid, then processing continues with obtaining the result digits count from the I₃field, STEP 504. Further, at least a part of the second operand is selected, STEP 506. For example, the number of rightmost digits indicated in the result digits count are selected. The selected part of the second operand is placed in a select location, STEP 508. In one example, the select location is a register designated using the V₁field. In another example, the select location is in memory or yet another location. Moreover, a sign for the selected part of the second operand is determined, STEP 510. In one example, the sign is determined using a plurality of criteria including, for instance, the sign operation, as specified in the I₄field; the result magnitude after RDC is applied; the sign of the second operand; and the value of the positive sign code specified in I₄. Based on these criteria, a resulting sign code is obtained, as indicated in FIG. 4. This resulting sign code is then placed in the select location along with the specified number of rightmost digits, STEP 512. In one example, the specified number of rightmost digits and the sign code are placed in the sign packed decimal format.

Described herein is a facility for using a single architected instruction to perform a sign operation. This instruction replaces one or more instruction sequences, and improves computer processing and performance. In one example, a capability is provided that sets sign codes for packed decimal numbers compactly and efficiently.

A single instruction (e.g., a single architected instruction) can handle, e.g., the following cases: move of data plus sign setting to 0xC, 0xD or 0xF; truncation of data while optionally setting or preserving the sign; ability to suppress validation for untrusted input data (this is a compatibility option in the binary optimization use case, as an example); sign complementing; and optional condition code setting. Some languages provide a machine exception on overflow, but others (e.g., COBOL) use a condition code for a user-defined action.

The example described above that used the ZAP/OI sequence for an unsigned variable widening is now revisited. This behavior can now be achieved with the Vector Perform Sign Operation Decimal instruction by setting RDC to the desired wider result size, setting SO to force positive, and setting SV to 0 to skip sign validity checking. The desired and fully compatible behavior is now achieved in a single instruction.

Further details regarding facilitating processing in a computing environment, including executing an instruction to perform a sign operation are described with reference to FIGS. 6A-6B.

Referring to FIG. 6A, in one embodiment, an instruction to perform a sign operation of a plurality of sign operations configured for the instruction is obtained by at least one processor, STEP 600, and executed, STEP 602. The executing includes, for instance, selecting at least a portion of an input operand as a result to be placed in a select location, STEP 604. The selecting is based on a control of the instruction (606), the control of the instruction indicating a user-defined size of the input operand to be selected as the result (608). A determination is made of a sign of the result based on a plurality of criteria, STEP 610. The plurality of criteria include, for example, a value of the result, obtained based on the control of the instruction, having a first particular relationship or a second particular relationship with respect to a selected value (612). The result and the sign are stored in the select location to provide a signed output to be used in processing within the computing environment, STEP 614.

As examples, the first particular relationship is equal, the second particular relationship is not equal, and the selected value is zero (616).

Further, in one example, the at least a portion of the input operand includes a number of select digits (e.g., a number of rightmost digits) of the input operand, the number of select digits specified by the control of the instruction (618). Moreover, referring to FIG. 6B, in one embodiment, the control is provided in an immediate field of the instruction (620).

Yet further, in one example, the plurality of criteria further include the sign operation to be performed (622). Further, in another example, the plurality of criteria include at least one criterion selected from a group of criteria including a sign operation to be performed, a sign of the input operand, and a positive sign code control of the instruction (624).

As one example, the plurality of sign operations include maintain, complement, forced positive and forced negative (626).

In a further embodiment, the executing further includes checking validity of a sign of the input operand, based on another control of the instruction indicating validity is to be checked, STEP 628.

Moreover, in one example, the select location is a register, the register being specified using at least one field of the instruction (630). The at least one field includes a register field specifying a register number and an extension field specifying an extension value to be appended to the register number (632).

One or more aspects may relate to cloud computing.

It is understood in advance that although this disclosure includes a detailed description on cloud computing, implementation of the teachings recited herein are not limited to a cloud computing environment. Rather, embodiments of the present invention are capable of being implemented in conjunction with any other type of computing environment now known or later developed.

Cloud computing is a model of service delivery for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g. networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal management effort or interaction with a provider of the service. This cloud model may include at least five characteristics, at least three service models, and at least four deployment models.

Characteristics are as follows:

On-demand self-service: a cloud consumer can unilaterally provision computing capabilities, such as server time and network storage, as needed automatically without requiring human interaction with the service's provider.

Broad network access: capabilities are available over a network and accessed through standard mechanisms that promote use by heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs).

Resource pooling: the provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, with different physical and virtual resources dynamically assigned and reassigned according to demand. There is a sense of location independence in that the consumer generally has no control or knowledge over the exact location of the provided resources but may be able to specify location at a higher level of abstraction (e.g., country, state, or datacenter).

Rapid elasticity: capabilities can be rapidly and elastically provisioned, in some cases automatically, to quickly scale out and rapidly released to quickly scale in. To the consumer, the capabilities available for provisioning often appear to be unlimited and can be purchased in any quantity at any time.

Measured service: cloud systems automatically control and optimize resource use by leveraging a metering capability at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported providing transparency for both the provider and consumer of the utilized service.

Service Models are as follows:

Software as a Service (SaaS): the capability provided to the consumer is to use the provider's applications running on a cloud infrastructure. The applications are accessible from various client devices through a thin client interface such as a web browser (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure including network, servers, operating systems, storage, or even individual application capabilities, with the possible exception of limited user-specific application configuration settings.

Platform as a Service (PaaS): the capability provided to the consumer is to deploy onto the cloud infrastructure consumer-created or acquired applications created using programming languages and tools supported by the provider. The consumer does not manage or control the underlying cloud infrastructure including networks, servers, operating systems, or storage, but has control over the deployed applications and possibly application hosting environment configurations.

Infrastructure as a Service (IaaS): the capability provided to the consumer is to provision processing, storage, networks, and other fundamental computing resources where the consumer is able to deploy and run arbitrary software, which can include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure but has control over operating systems, storage, deployed applications, and possibly limited control of select networking components (e.g., host firewalls).

Deployment Models are as follows:

Private cloud: the cloud infrastructure is operated solely for an organization. It may be managed by the organization or a third party and may exist on-premises or off-premises.

Community cloud: the cloud infrastructure is shared by several organizations and supports a specific community that has shared concerns (e.g., mission, security requirements, policy, and compliance considerations). It may be managed by the organizations or a third party and may exist on-premises or off-premises.

Public cloud: the cloud infrastructure is made available to the general public or a large industry group and is owned by an organization selling cloud services.

Hybrid cloud: the cloud infrastructure is a composition of two or more clouds (private, community, or public) that remain unique entities but are bound together by standardized or proprietary technology that enables data and application portability (e.g., cloud bursting for loadbalancing between clouds).

A cloud computing environment is service oriented with a focus on statelessness, low coupling, modularity, and semantic interoperability. At the heart of cloud computing is an infrastructure comprising a network of interconnected nodes. One such node is node 10 depicted in FIG. 1A.

Computing node 10 is only one example of a suitable cloud computing node and is not intended to suggest any limitation as to the scope of use or functionality of embodiments of the invention described herein. Regardless, cloud computing node 10 is capable of being implemented and/or performing any of the functionality set forth hereinabove.

Referring now to FIG. 7, illustrative cloud computing environment 50 is depicted. As shown, cloud computing environment 50 comprises one or more computing nodes 10 with which local computing devices used by cloud consumers, such as, for example, personal digital assistant (PDA) or cellular telephone 54A, desktop computer 54B, laptop computer 54C, and/or automobile computer system 54N may communicate. Nodes 10 may communicate with one another. They may be grouped (not shown) physically or virtually, in one or more networks, such as Private, Community, Public, or Hybrid clouds as described hereinabove, or a combination thereof. This allows cloud computing environment 50 to offer infrastructure, platforms and/or software as services for which a cloud consumer does not need to maintain resources on a local computing device. It is understood that the types of computing devices 54A-N shown in FIG. 7 are intended to be illustrative only and that computing nodes 10 and cloud computing environment 50 can communicate with any type of computerized device over any type of network and/or network addressable connection (e.g., using a web browser).

Referring now to FIG. 8, a set of functional abstraction layers provided by cloud computing environment 50 (FIG. 7) is shown. It should be understood in advance that the components, layers, and functions shown in FIG. 8 are intended to be illustrative only and embodiments of the invention are not limited thereto. As depicted, the following layers and corresponding functions are provided:

Hardware and software layer 60 includes hardware and software components. Examples of hardware components include mainframes 61; RISC (Reduced Instruction Set Computer) architecture based servers 62; servers 63; blade servers 64; storage devices 65; and networks and networking components 66. In some embodiments, software components include network application server software 67 and database software 68.

Virtualization layer 70 provides an abstraction layer from which the following examples of virtual entities may be provided: virtual servers 71; virtual storage 72; virtual networks 73, including virtual private networks; virtual applications and operating systems 74; and virtual clients 75.

In one example, management layer 80 may provide the functions described below. Resource provisioning 81 provides dynamic procurement of computing resources and other resources that are utilized to perform tasks within the cloud computing environment. Metering and Pricing 82 provide cost tracking as resources are utilized within the cloud computing environment, and billing or invoicing for consumption of these resources. In one example, these resources may comprise application software licenses. Security provides identity verification for cloud consumers and tasks, as well as protection for data and other resources. User portal 83 provides access to the cloud computing environment for consumers and system administrators. Service level management 84 provides cloud computing resource allocation and management such that required service levels are met. Service Level Agreement (SLA) planning and fulfillment 85 provide pre-arrangement for, and procurement of, cloud computing resources for which a future requirement is anticipated in accordance with an SLA.

Workloads layer 90 provides examples of functionality for which the cloud computing environment may be utilized. Examples of workloads and functions which may be provided from this layer include: mapping and navigation 91; software development and lifecycle management 92; virtual classroom education delivery 93; data analytics processing 94; transaction processing 95; and instruction processing 96.

The present invention may be a system, a method, and/or a computer program product at any possible technical detail level of integration. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.

The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.

Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuitry, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++, or the like, and procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.

Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.

These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

In addition to the above, one or more aspects may be provided, offered, deployed, managed, serviced, etc. by a service provider who offers management of customer environments. For instance, the service provider can create, maintain, support, etc. computer code and/or a computer infrastructure that performs one or more aspects for one or more customers. In return, the service provider may receive payment from the customer under a subscription and/or fee agreement, as examples. Additionally or alternatively, the service provider may receive payment from the sale of advertising content to one or more third parties.

In one aspect, an application may be deployed for performing one or more embodiments. As one example, the deploying of an application comprises providing computer infrastructure operable to perform one or more embodiments.

As a further aspect, a computing infrastructure may be deployed comprising integrating computer readable code into a computing system, in which the code in combination with the computing system is capable of performing one or more embodiments.

As yet a further aspect, a process for integrating computing infrastructure comprising integrating computer readable code into a computer system may be provided. The computer system comprises a computer readable medium, in which the computer medium comprises one or more embodiments. The code in combination with the computer system is capable of performing one or more embodiments.

Although various embodiments are described above, these are only examples. For example, computing environments of other architectures can be used to incorporate and use one or more embodiments. Further, different instructions, instruction formats, instruction fields and/or instruction values may be used. Many variations are possible.

Further, other types of computing environments can benefit and be used. As an example, a data processing system suitable for storing and/or executing program code is usable that includes at least two processors coupled directly or indirectly to memory elements through a system bus. The memory elements include, for instance, local memory employed during actual execution of the program code, bulk storage, and cache memory which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution.

Input/Output or I/O devices (including, but not limited to, keyboards, displays, pointing devices, DASD, tape, CDs, DVDs, thumb drives and other memory media, etc.) can be coupled to the system either directly or through intervening I/O controllers. Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modems, and Ethernet cards are just a few of the available types of network adapters.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising”, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below, if any, are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of one or more embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain various aspects and the practical application, and to enable others of ordinary skill in the art to understand various embodiments with various modifications as are suited to the particular use contemplated.