REFERENCE TO RELATED APPLICATION

This reference is being filed as a Continuation Application of patent application Ser. No. 13/551,705, filed 18 Jul. 2012, currently pending.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is related to a regulation circuit, especially to a regulation circuit associated with a synchronous rectifier providing cable compensation for the power converter.

2. Description of the Related Art

FIG. 1 shows a prior art of a power converter. A PWM controller (PWM) 30 generates a switching signal S_PWMto switch a transformer 10 having a primary winding N_Pand a secondary winding N_Svia a power transistor 20 in accordance with a feedback signal V_FBfor regulating the output of the power converter. The primary winding N_Pof the transformer 10 is coupled to receive an input voltage V_IN. The feedback signal V_FBis generated by an opto-coupler 60 in response to the output voltage V_Oof the power converter. The opto-coupler 60 is controlled by an error amplifier 50. The error amplifier 50 generates a signal V_Fcoupled to control the opto-coupler 60. The error amplifier 50 includes a reference signal V_Rsupplied with a positive input terminal of the error amplifier 50 for regulating the output voltage V_O. The output voltage V_Ois coupled to a negative input terminal of the error amplifier 50 via a voltage divider developed by resistors 51 and 52. A capacitor 53 is coupled between the negative input terminal of the error amplifier 50 and an output terminal of the error amplifier 50.

The secondary winding N_Sis coupled to an output terminal of the power converter to generate the output voltage V_O. A rectifier 40 is coupled to one terminal of the secondary winding N_S. An output capacitor 45 is coupled to the other terminal of the secondary winding N_Sand the output terminal of the power converter to generate the output voltage V_O. A resister 62 is coupled from the capacitor 45 and the rectifier 40 to the opto-coupler 60.

Generally, the output cable of the power converter has a voltage drop proportional to its output current. Sensing the output current to offset the voltage drop is an approach for the output cable compensation. However, it will generate a significant power loss while sensing the output current by using a shunt resistor. The present invention provides a method and apparatus to compensate the output voltage without the need of sensing the output current of the power converter by the shunt resistor.

BRIEF SUMMARY OF THE INVENTION

The object of the present invention is to provide a regulation circuit and a method with output cable compensation for the power converter. The regulation circuit and method compensate the output voltage without a shunt resistor to sense the output current of the power converter for reducing power loss.

The regulation circuit with output cable compensation for the power converter according to the present invention comprises a signal generator and an error amplifier. The signal generator generates a compensation signal in accordance with a synchronous rectifying signal. The error amplifier has a reference signal for generating a feedback signal in accordance with an output voltage of the power converter. The compensation signal is coupled to program the reference signal. The feedback signal is coupled to generate a switching signal for regulating an output of the power converter.

A method for the regulation circuit of the power converter according to the present invention comprises receiving the synchronous rectifying signal for generating the compensation signal, compensating the reference signal of the error amplifier of the regulation circuit in accordance with the compensation signal, and generating the feedback signal in accordance with the reference signal and the output voltage of the power converter. The feedback signal is coupled to generate the switching signal for regulating the output of the power converter.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 shows a circuit diagram of a conventional power converter.

FIG. 2 shows a circuit diagram of a preferred embodiment of a power converter in accordance with the present invention.

FIG. 3 shows a circuit diagram of a preferred embodiment of the regulation circuit in accordance with the present invention.

FIG. 4 shows a circuit diagram of a preferred embodiment of the signal generator in accordance with the present invention.

FIG. 5 shows the waveforms of the SR signal S_SRand the pulse signals S₁and S₂of the pulse generator in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2 is a circuit diagram of a preferred embodiment of the power converter having a regulation circuit 100 according to the present invention. The power converter comprises the transformer 10, the power transistor 20, the PWM controller (PWM) 30, the opto-coupler 60, a synchronous rectifying (SR) controller 70, a power transistor 75, and the regulation circuit (REG) 100. The power transistor 20 is coupled from the primary winding N_Pof the transformer 10 to the ground for switching the transformer 10. The PWM controller 30 generates the switching signal S_PWMto switch the power transistor 20 in accordance with the fee dback signal V_FBfor regulating the output (output voltage V_Oand/or the output current I_O) of the power converter.

The opto-coupler 60 is coupled to the secondary winding N_Sof the transformer 10 through the resistor 62. The opto-coupler 60 generates the feedback signal V_FBcoupled to the PWM controller 30 in response to the output voltage V_O. The secondary winding N_Sis coupled to the output terminal of the power converter to generate the output voltage V_O. The output capacitor 45 is coupled to the secondary winding N_Sand the output terminal of the power converter to generate the output voltage V_O. The output voltage V_Ois outputted to the load through the output cable. The output current I_Oof the power converter flows through the output cable.

The power converter has a synchronous rectifying circuit to improve the power efficiency of the power converter. The synchronous rectifying circuit includes the synchronous rectifying controller 70 and the power transistor 75 having a parasitic diode 76. The power transistor 75 is used for a synchronous rectifier to replace the rectifier 40 (shown in FIG. 1) for rectification. A drain terminal of the power transistor 75 is coupled to the secondary winding N_S, and a source terminal of the power transistor 75 is coupled to the output terminal of the power converter. The parasitic diode 76 is coupled between the drain terminal and the source terminal of the power transistor 75. The synchronous rectifying controller 70 generates a synchronous rectifying signal (SR signal) S_SRcoupled to a gate terminal of the power transistor 75 to control the on/off of the power transistor 75.

The detail operation of the synchronous rectifying circuit can be found in the prior art of â€œSynchronous rectification circuit for power convertersâ€ , U.S. Pat. No. 7,440,298. Refer to equation (9) of this prior art, it is,

$\begin{matrix} T_{discharge} = \frac{V_{S}}{V_{O}} Ã— T_{charge} & (1) \end{matrix}$

where the T_chargeis equal to the on-time T_ONof the switching signal S_PWM; T_dischargeis the â€œturn on periodâ€ of the SR signal S_SR. The V_Sis the magnetized voltage that is correlated to the input voltage V_INof the power converter. Thus, the equation (1) can be rewritten as equation (2),

$\begin{matrix} T_{SSR} = \frac{K Ã— V_{I î¢ž î¢ž N}}{V_{O}} Ã— T_{ON} & (2) \end{matrix}$

where K is a constant.

Refer to an output power P_Oof the flyback power converter, it can be expressed as,

$\begin{matrix} P_{O} = V_{O} Ã— I_{O} = \frac{V_{I î¢ž î¢ž N}^{2} Ã— T_{ON}^{2}}{2 Ã— L_{P} Ã— T} & (3) \end{matrix}$

where L_Pis the inductance of the primary winding N_Pof the transformer 10; T is the switching period of the switching signal S_PWM.

In accordance with the equations (2) and (3), if the output voltage V_Ois fixed value, then the period T_SSR(â€œturn on periodâ€ of the SR signal S_SR) is correlated to the output current I_O. In other words, the SR signal S_SRis correlated to the output current I_O. Therefore, the SR signal S_SRcan be used instead of the output current I_Oto control the output voltage V_Ofor the cable compensation.

The regulation circuit 100 is coupled to receive the SR signal S_SRand the signal V_Afor generating the signal V_F. The signal V_Fis future coupled to drive the opto-coupler 60 and generate the feedback signal V_FB. The signal V_Ais produced in accordance with the output voltage V_Ovia the voltage divider developed by the resistors 51 and 52. Therefore, the regulation circuit 100 is used for generating the feedback signal V_FBin accordance with the output voltage V_O. The voltage drop of the output voltage V_Oin the output cable can be compensated by the control of the SR signal S_SR. Further, a resistor 115 is coupled to a terminal R_Pof the regulation circuit 100.

FIG. 3 is a circuit diagram of a preferred embodiment of the regulation circuit 100 according to the present invention. A signal generator (S/I) 200 is coupled to receive the SR signal S_SRfor generating a compensation signal I_COMP. The resistor 115 is coupled to the terminal R_Pof the signal generator 200 to determine the ratio of signal generation. The resistor 115 is used for programming the level of the compensation signal I_COMPin accordance with the SR signal S_SR. An output terminal of a buffer amplifier 110 having a reference voltage V_R1supplied with a positive input terminal of the buffer amplifier 110 is coupled to a resistor 117. The resistor 117 is further coupled to an output terminal of the signal generator 200. A negative input terminal of the buffer amplifier 110 is coupled to the output terminal of the buffer amplifier 110 and the resistor 117. The compensation signal I_COMPand the resistor 117 are utilized to generate a compensation voltage at the resistor 117.

A resistor 165 and a capacitor 150 develop a filter coupled to the output terminal of the signal generator 200 and the resistor 117. The resistor 165 is coupled from the output terminal of the signal generator 200 and the resistor 117 to a terminal of the capacitor 150. The other terminal of the capacitor 150 is coupled to the ground. Through the filter, a reference signal V_REFis generated at the capacitor 150.

V_REF=V_R1+(I_COMPÃ—R₁₁₇)â€ƒâ€ƒ(4)

The capacitor 150 of the filter is used for filtering the reference signal V_REF. According to equation (4), the reference signal V_REFis correlated to the compensation signal I_COMP. Therefore, the compensation signal I_COMPcan program and compensate the reference signal V_REF, and the reference signal V_REFis programmable in response to the output current I_O(as shown in FIG. 2) due to the compensation signal I_COMPis correlated to the SR signal S_SRand the SR signal S_SRis correlated to the output current I_O. Further, according to equation (4), the reference signal V_REFis further correlated to the reference voltage V_R1of the buffer amplifier 110. Therefore, the buffer amplifier 110 is coupled to the compensation signal I_COMPfor generating the reference signal V_REF.

An error amplifier 170 is coupled to receive the reference signal V_REFand the signal V_Ato generate the signal V_Ffor generating the feedback signal V_FB(as shown in FIG. 2). A positive input terminal and a negative input terminal of the error amplifier 170 receive the reference signal V_REFand the signal V_Arespectively. An output terminal of the error amplifier 170 generates the signal V_F. A capacitor 175 is coupled between the negative input terminal of the error amplifier 170 and the output terminal of the error amplifier 170.

FIG. 4 is a circuit diagram of a preferred embodiment of the signal generator 200 according to the present invention. A pulse generator 210 receives the SR signal S_SRand generates pulse signals S₁and S₂in response to the SR signal S_SR. The waveforms of the pulse signals S₁and S₂are shown in FIG. 5. The first pulse signal S₁is enabled when the SR signal S_SRis disabled. Once the first pulse signal S₁is disabled, the second pulse signal S₂is enabled after a delay time. The SR signal S_SRis further coupled to control a charge circuit to charge a capacitor 250 for providing a voltage. The voltage provided by the capacitor 250 is correlated to the SR signal S_SR. The charge circuit includes a current source 230 and a charge switch 231. The current source 230 is coupled between a supply voltage V_CCand the charge switch 231 to charge the capacitor 250 through the charge switch 231. The capacitor 250 is coupled from the charge switch 231 to the ground. The charge switch 231 is controlled by the SR signal S_SR.

The first pulse signal S₁is coupled to control a sample switch 232 for sampling the voltage of the capacitor 250 to a capacitor 270. The sample switch 232 is coupled between the capacitor 250 and the capacitor 270. The capacitor 270 is further coupled to the ground.

The second pulse signal S₂is coupled to control a discharge switch 233 for discharging the capacitor 250. The discharge switch 233 is coupled between the capacitor 250 and the ground. The voltage of the capacitor 270 is correlated to the voltage of the capacitor 250. The capacitor 270 is further coupled to a voltage to current converter to convert the voltage of the capacitor 270 to a current I₃₁₀for generating the compensation signal I_COMP. In other words, the voltage to current converter converts the voltage of the capacitor 250 to the current I₃₁₀for generating the compensation signal I_COMP. The voltage to current converter includes an operational amplifier 300 and a transistor 310. The resistor 115 (at RP terminal) is coupled to the voltage to current converter.

The capacitor 270 is coupled to a positive input terminal of the operational amplifier 300. A negative input terminal of the operational amplifier 300 is coupled to a source terminal of the transistor 310 and the resistor 115 through the RP terminal. The source terminal of the transistor 310 is coupled to the resistor 115 through the RP terminal. The voltage to current converter converts the voltage of the capacitor 270 to the current I₃₁₀at a drain terminal of the transistor 310 in accordance with the resistance of the resistor 115 (at RP terminal). The resistor 115 is utilized to program the current I₃₁₀in accordance with the SR signal S_SRfor programming the level of the compensation signal I_COMP.

A gate terminal of the transistor 310 is controlled by an output terminal of the operational amplifier 300 for producing the current I₃₁₀. The current I₃₁₀is further coupled to a current mirror formed by transistors 311 and 312. The current mirror generates the compensation signal I_COMP. Source terminals of the transistors 311 and 312 are coupled to the supply voltage V_CC. Gate terminals of the transistors 311 and 312 and drain terminals of the transistors 310 and 311 are coupled together. A drain terminal of the transistor 312 generates the compensation signal I_COMP.

Although the present invention and the advantages thereof have been described in detail, it should be understood that various changes, substitutions, and alternations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims. That is, the discussion included in this invention is intended to serve as a basic description. It should be understood that the specific discussion may not explicitly describe all embodiments possible; many alternatives are implicit. The generic nature of the invention may not fully explained and may not explicitly show that how each feature or element can actually be representative of a broader function or of a great variety of alternative or equivalent elements. Again, these are implicitly included in this disclosure. Neither the description nor the terminology is intended to limit the scope of the claims.