CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Divisional of and claims benefit to U.S. patent application Ser. No. 13/779,160, filed Feb. 27, 2013. This application is also related to U.S. patent application Ser. No. 13/779,376, filed Feb. 27, 2013 and U.S. patent application Ser. No. 13/779,210, filed Feb. 27, 2013â€”U.S. Pat. No. 9,351,081â€”a Divisional of which was filed on Apr. 11, 2016 assigned U.S. patent application Ser. No. 15/095,264. Said application are herein incorporated by reference in their entireties.

FIELD

Disclosed embodiments relate to methods of forming capacitive micro-electro-mechanical system (MEMS) sensor devices and MEMS sensor devices therefrom.

BACKGROUND

Known MEMS processes have challenges with producing cost effective small size packaged MEMS sensor devices, as well as defining a robust integration scheme incorporating conventional release layers. In addition, after conventional release the MEMS sensor cell(s) in the MEMS sensor device needs to be vacuum sealed at a low pressure to provide desired high-Q sensor performance which provides further challenges.

SUMMARY

Disclosed embodiments describe solutions to the problems with conventional capacitive micro-electro-mechanical system (MEMS) sensor devices resulting from the use of release layers to seal the MEMS cavity of the sensor cell(s) by adding through-substrate vias (TSVs) (e.g., through-silicon vias in the case of silicon substrates). The TSVs provide access to the fixed electrode and released MEMS electrode both from the bottom side of the MEMS sensor device. The MEMS cavity of each sensing cell is sealed, such as by vacuum diffusion bonding, to another substrate (e.g., wafer) referred to as a third â€œcappingâ€ substrate over the fully released MEMS electrode(s) of the capacitive MEMS sensor device, which eliminates the need for a conventional passivation layer. At the end of the process the completed capacitive MEMS sensor device will itself provide a package.

BRIEF DESCRIPTION OF THE DRAWINGS

Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, wherein:

FIG. 1A is a top view depiction an example capacitive MEMS device shown as a capacitive MEMS element with a single capacitive MEMs sensor cell, with the third capping substrate removed to show underlying features according to an example embodiment, along with a cut line for the cross sectional depictions described below.

FIG. 1B is a cross sectional depiction of an example capacitive MEMS device/element/cell shown in FIG. 1A along the cut line A-Aâ€² shown.

FIG. 1C is a top view depiction of an example capacitive MEMS device shown as a capacitive MEMS element with a tuning fork resonator cell with the third capping substrate removed to show underlying features, according to an example embodiment.

FIG. 1D is a top view depiction of an example capacitive MEMS device shown as a two cell capacitive MEMS element with a tuning fork resonator cell with the third capping substrate removed to show underlying features, according to an example embodiment.

FIGS. 2A-H are cross-sectional diagrams showing processing progression for an example method of forming a capacitive MEMS sensor device, according to an example embodiment.

FIG. 3 is a top view depiction an example capacitive MEMS device including a plurality of capacitive MEMS elements, each capacitive MEMS element including a plurality of the MEMS cell shown in FIGS. 1A and 1B coupled together within each element, according to an example embodiment.

DETAILED DESCRIPTION

Example embodiments are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this disclosure.

Regarding nomenclature used herein, the smallest capacitive MEMS sensor entity is a capacitive MEMS sensor cell. Multiple capacitive MEMS sensor cells can be connected in parallel, such as on the die using an electrically common MEMS electrode 120b (typically by a membrane layer 120 with metal on top) to form a capacitive MEMS sensor element. A capacitive MEMS sensor element can have any number (â‰§1) of capacitive MEMS sensor cells. Typically, the more capacitive MEMS sensor cells in an element the greater the output that element can generate responsive to a given stimulus. A capacitive MEMS sensor array (device/die) can have any number of capacitive MEMS sensor cell elements. One of the electrodes (e.g., top) of the respective CMUT elements can be electrically isolated from the other electrodes (e.g., top) of the other CMUT elements to allow each CMUT element to be connected independently to allow individual addressability. For example, as described herein, the electrically common MEMS electrodes 120b for each capacitive MEMS sensor element can be addressed by a single TSV.

FIG. 1A is a top view depiction an example packaged capacitive MEMS sensor device (die) 100 shown as a capacitive MEMS element with a single capacitive MEMS sensor cell 100a, shown as a disk resonator, according to an example embodiment. The third capping substrate described below is depicted removed or transparent to show underlying features. A cut line A-Aâ€² is shown which is used for some cross sectional depictions described below, including the cross sectional depictions shown in FIG. 1B. Although circular feature geometries are shown (a disk) for the capacitive MEMS sensor cell 100a in FIGS. 1A and 1B, other feature geometries may be used such as rectangular.

The capacitive MEMS sensor device 100/cell 100a includes a first substrate 101 having a top side 102 including a patterned dielectric layer thereon, including as shown in FIG. 1B thick dielectric regions 106 and thin dielectric regions 107 which form the bottom surface of the MEMS cavity 114. Capacitive MEMS sensor cell 100a includes a plurality TSVs including at least a first TSV 111 and a second TSV 112, which as shown in FIG. 1B are exposed on a bottom side 103 of the first substrate 101 and extend a full thickness of the first substrate 101. First TSV 111 and a second TSV 112 are shown including protruding TSV tips 111a and 112a, respectively. The TSVs 111 and 112 include a TSV dielectric liner 131.

Capacitive MEMS sensor cell 100a includes a second substrate providing a membrane layer 120 which is on the thick dielectric regions 106 and over the thin dielectric regions 107. The membrane layer as used herein refers to a semiconductor layer (e.g., silicon) that is defined to form the fixed electrode 120a and MEMS electrode 120b for the capacitive MEMS sensor cell 100a, and can optionally also provide interconnect lines (typically having a metal layer thereon) between the MEMS electrodes 120b of respective MEMS sensor cells within capacitive MEMS sensor elements of capacitive MEMS sensor devices having a plurality of MEMS sensor elements. The membrane layer 120 need not include any integrated circuit elements (e.g., transistors).

The membrane layer 120 includes a fixed portion providing a fixed electrode 120a, and includes enclosing through-holes 123 which release the membrane layer 120 over the MEMS cavity 114 to provide a movable MEMS electrode 120b which functions as a resonating element for the capacitive MEMS sensor cell 100a. The plurality of TSVs also extend a full thickness of the membrane layer 120 including the first TSV 111 which extends through a top side of the MEMS electrode 120b and the second TSV 112 which extends through a top of the fixed electrode 120a. A patterned metal layer 251 including a metal cap 132 is on a top of the first TSV 111 and another metal cap 133 is over the second TSV 112.

As shown in FIG. 1B, packaged capacitive MEMS sensor device 100/capacitive MEMS sensor cell 100a includes a third capping substrate 140 which functions as a cap to seal the MEMS electrode 120b, having a bottom side 142 including a recessed inner cavity 144 and outer protruding portions 146 which frame the inner cavity 144. The third capping substrate 140 is bonded with its bottom side 142 down with the protruding portions 146 bonded (e.g., diffusion vacuum bonded) to the thick dielectric region 106 as shown. The final cavity for the capacitive MEMS sensor cell 100a is thus defined by the third capping substrate 140 and the first substrate 101 (e.g., by 2 wafers during fabrication). The third capping substrate 140 together with the first substrate 101 can vacuum seal the MEMS electrode 120b so that third capping substrate 140 completes the packaged capacitive MEMS sensor device 100.

FIG. 1C is a top view depiction of an example packaged capacitive MEMS sensor device 180 shown as a capacitive MEMS element with a tuning fork resonator capacitive sensor cell 180a with the third capping substrate 140 again removed to show underlying features, according to an example embodiment. The packaged capacitive MEMS sensor device 180/tuning fork resonator capacitive sensing cell 170a includes a MEMS cavity 172 and three (3) electrodes shown as electrode 1 (170a), electrode 2 (170b), 170a and 170b being multi-finger electrodes, and electrodes 3 (for first substrate 101), where the MEMS cavity 172 is a lateral cavity located between the outer edges of electrode 1 (170a) and electrode 2 (170b), while electrode 3 is provided by the first substrate 101. Analogous to packaged capacitive MEMS device/cell 100 shown in FIGS. 1A and 1B, TSV 176 and TSV 177 extend through a top side of their respective electrodes, electrode 1 (170a) and electrode 2 (170b), respectively.

A third electrode (electrode 3) is not always needed for disclosed packaged capacitive MEMS sensor devices. If the capacitive MEMS device is a 2D motion sensor only, the connections provided by two TSV is sufficient for sensor operation. A low resistivity first substrate 101 can be used as a third electrode for devices such as the packaged capacitive MEMS sensor device 180/tuning fork resonator capacitive sensor cell 180a to enable 3D motion detection. For the capacitive MEMS device 100 shown in FIG. 1A and FIG. 1B, a third electrode allows rocking motion or vertical deflection of the MEMS electrode 120b (e.g., a Si disk) to be detected as a change in capacitance between the MEMS electrode 120b and the low resistivity first substrate 101. One can also detect a capacitance change between the first substrate 101 and the underside of electrode 1 (170a), and electrode 2 (170b). An up or down motion would cause the fingers of electrode 1 (170a) and electrode 2 (170b) to flex in a vertical direction.

FIG. 1D is a top view depiction of an example capacitive MEMS device 190 shown as a two cell capacitive MEMS element (comprising cells 190a and 190b) having a tuning fork resonator cell configuration with the third capping substrate 140 removed to show underlying features, according to an example embodiment. The tuning fork resonator capacitive sensing cells 190a and 190b each include their own MEMS cavity 172a and 172b. Capacitive MEMS device 190 has three (3) electrodes shown as electrode 1 (195a), electrode 2 (195b), 195a and 195b being multi-finger electrodes, with optional electrode 3 (from first substrate 101). Electrodes 195a and 195b comprise the membrane layer 120 which may have an optional metal thereon (for low resistance) which couple together the electrodes 195a and 195b for cells 190a and 190b. Analogous to packaged capacitive MEMS device/cell 100 shown in FIGS. 1A-B and MEMS device/cell 180 shown in FIG. 1C, TSV 176 and TSV 177 extend through a top side of their respective electrodes, electrode 1 (195a) and electrode 2 (195b), respectively. Third capping substrate 140 if shown would have its outer protruding portions 146 aligned with the perimeter of thick dielectric region 106 (perimeter of capacitive MEMS device 190), with a recessed inner cavity within.

FIGS. 2A-2H are cross-sectional diagrams showing processing progression for an example method of forming capacitive MEMS devices during different stages of fabrication, according to an example embodiment. Although the capacitive MEMS device is described being formed as a capacitive MEMS element with a single capacitive MEMS sensor cell, disclosed capacitive MEMS devices may be formed having a plurality of interconnected capacitive MEMS elements each having a plurality of capacitive MEMS cells (see FIG. 3 described below).

The embodiment described as shown in FIGS. 2A-H is thus for illustration only and is one particular embodiment which describes formation of a packaged MEMS sensor device having a capacitive MEMS element with a single capacitive MEMS cell 100a. Other techniques for forming disclosed capacitive MEMS devices can be used without departing from the scope of this disclosure, including forming capacitive MEMS sensor devices including a plurality of disclosed capacitive MEMS sensor elements each having a plurality of capacitive MEMS sensor cells. Several sensor elements in parallel can be used to achieve a given frequency over a given area. One can connect the sensor elements in parallel to reduce the impedance (for driving) or connect them in series to increase the impedance (for sensing). One can drive/sense sensor elements differentially to improve common mode signals or mitigate manufacturing asymmetries.

Thick dielectric regions 106, such as comprising a silicon oxide layer, is provided on a top surface 102 of a first substrate 101. First substrate 101 can generally comprise any substrate material, including silicon-based substrates, or other substrates. As disclosed above, for 3D motion detection MEMS sensor embodiments, the first substrate 101 can be a low resistivity bulk silicon substrate (e.g., resistivity â‰¦0.1 Î©-cm such as about 0.01 Î©-cm), which as described above enables the first substrate 101 to be used as practical (low series resistance) third electrode for the MEMS sensor cell(s).

In one particular embodiment, to form thick dielectric regions 106 a thick silicon oxide layer is grown to a thickness of 4.5 Î¼m to 5.5 Î¼m using a high pressure oxidation (HiPOx) process. The use of HiPOx facilitates the rapid growth of thick thermal oxide layers and provides excellent thickness control of typically less than 1%. One particular example set of HiPOx process conditions are temperature of 1000Â° C. at 25 atmospheres pressure in steam for 9.5 hours on virgin first substrates 101 (e.g., silicon wafers), and the alignment marks for photolithography are etched later in the process. However, as an alternative, thick dielectric regions 106 may also comprise conventional thermally grown silicon oxide, or a deposited dielectric layer, including silicon oxide or other dielectric material.

The substrate vendor's laser scribe generally present can be used to ensure a minimum of surface contamination or roughness. Masking and etching of front side alignment marks can follow. Resist strip and a pre-clean process can help ensure a smooth surface for the thick dielectric regions 106 used later in the process for facilitating subsequent wafer bonding of the third capping substrate thereto.

A first masking level â€œCELLETCHâ€ uses thick photoresist in order to support the subsequent etch through the thick dielectric regions 106 (e.g., thick silicon oxide layer) to initially begin to define at least one etched capacitive MEMS sensor cell for each device/die. A plasma etch which is non-polymerizing can be used for etching a first portion of the thick dielectric region 106, such as to etch about 4.65 Î¼m of silicon oxide when thick dielectric regions 106 comprise silicon oxide and have a thickness of about 5 Î¼m to 5.3 Î¼m. A sidewall slope of Ëœ80Â° is generally desirable and can be achieved from the natural resist erosion. The remaining portion of the thick dielectric region 106 (e.g., 0.5 Î¼m silicon oxide) after plasma etch can be removed by wet etch that provides etch selectivity relative to the substrate material (e.g., Si) to avoid damaging the top surface 102 of the first substrate 101.

About 50% of the top surface 102 of the first substrate 101 (e.g., a wafer) will generally be open (exposed) during the etch of the thick dielectric region. The resist is then stripped (e.g., a wet strip process). Following an appropriate pre-oxidation clean, in an oxidation step a thin (e.g., 0.3 Î¼m) sensor cell oxide and post oxide can be grown. For effective subsequent bonding of the third capping substrate 140 described below, the post oxide surface roughness should generally be less than about 3 â„«.

FIG. 2A shows a cross sectional depiction after bonding (e.g., vacuum fusion bonding) of a second substrate shown as a SOI wafer 115 having a handle (wafer) 116, a buried dielectric layer (generally referred to in the art as a â€œburied oxide layerâ€ or â€œ(BOX) layerâ€ ) 117 and membrane layer 120 (e.g., generally referred in the art as an â€œactive layerâ€ ) to the thick dielectric region 106 of the first substrate 101. In one particular embodiment the handle comprise silicon and is 500 Î¼m to 750 Î¼m thick, the membrane layer 120 is 15 Î¼mÂ±0.5 Î¼m (e.g., about 14 Î¼m) thick, and the buried dielectric layer 117 is 1.0 Î¼m to 2.0 Î¼m thick. The membrane layer 120 is bonded to the thick dielectric regions 106 of the first substrate 101.

The handle 116 represents any suitable semiconductor wafer formed from any suitable material(s), such as undoped or lightly-doped (n or p-doped) silicon. The buried dielectric layer 117 represents any suitable layer(s) of electrically insulative material(s), such as a silicon oxide layer. The membrane layer 120 represents any suitable layer(s) of substrate material(s), for example, moderately-doped silicon, such as having a resistivity of about 5 to 10 Î©-cm. For interconnection purposes between cells or elements, the membrane layer 120 can include a metal layer thereon which renders the pathway provided a low resistivity pathway.

For embodiments where the capacitive MEMS sensor device includes a plurality of MEMS sensor die, the membrane layer 120 can be heavily doped and/or include a metal layer thereon to permit low resistance connections between sensor cells in multi-cell capacitive MEMS elements to be made by connection provided at least in part by the membrane layer 120 (see FIG. 1D described above). For example, membrane layer 120 can have a resistivity of â‰¦0.1 Î©-cm, such as about 0.01 Î©-cm. In other embodiments, the membrane layer 120 can have a resistivity of up to about 100 Î©-cm. Proper known bonding procedures including cleans and plasma pre-treatments can be used.

The bonding can comprise vacuum fusion wafer bonding. For vacuum fusion wafer bonding, as is commonly known in the art, attributes which ensure good wafer bonding include the bonding surfaces being smooth with a surface roughness typically less than 3 A. Grown thermal oxide and silicon substrates generally satisfy this requirement. Prior to bonding the surfaces can be treated with an RCA clean (SC-1, where SC stands for Standard Clean, with a 1:1:5 solution of NH₄OH (ammonium hydroxide)+H₂O₂(hydrogen peroxide)+H₂O (water) at 75 or 80Â° C. typically for 10 minutes. The second RCA clean step is a short immersion in a 1:50 solution of HF+H₂O at 25Â° C., in order to remove the thin oxide layer and some fraction of ionic contaminants. The third and last step RCA clean (called SC-2) is performed with a 1:1:6 solution of HCl+H₂O₂+H₂O at 75 or 80Â° C. This treatment effectively removes the remaining traces of metallic (ionic) contaminants. A N₂plasma activation and a DI water rinse can follow. The vacuum bonding is typically performed at a pressure less than 8Ã—10⁵mbar. As a final step the bonded surfaces are annealed in N₂for several hours, such a 4 hour 1050Â° C. N₂anneal.

The handle 116 is then removed after bonding, such as by backgrinding the handle 116 to about a 150 Î¼m post-backgrind target, performing a second 4 hour 1050Â° C. anneal after backgrinding prior to a wet etch of the handle remaining after backgrind, and then wet etching the remaining handle. The handle remaining after backgrind when the handle 116 comprises silicon can be etched in a wet silicon etch, such as using a hydroxide (e.g., KOH or TMAH), stopping on the buried dielectric layer 117. Mask and etching plates from membrane layer 120 can be used to form at least one MEMS electrode 120b over the alignment marks to reopen the alignment marks and enable proper alignment for subsequent process steps. Since the membrane layer 120 is generally a relatively thick layer for etching (e.g., about 14 Î¼m thick), a Bosch etch can compensate for resist erosion during the etch of the membrane layer 120. As known in the art, the Bosch process, also known as pulsed or time-multiplexed etching, alternates repeatedly between two modes/phases to achieve nearly vertical etched structures.

However, in the fabrication method, the SOI wafer 115 can be replaced by a alternative second substrate such as a standard bulk silicon substrate to reduce cost, where the standard substrate material can be bonded to the thick dielectric region 106 on the first substrate 101. In this alternate embodiment, after bonding, the second substrate material can be thinned by backgrind and polishing to the desired target membrane thickness, such as 14 Î¼mÂ±5 Î¼m thick.

FIG. 2B shows a cross sectional depiction after the mask level â€œTSVHOLEâ€ (Mask #2) and formation of a TSV holes to form embedded vias 219 beginning from the top side of the membrane layer 120. Embedded vias 219 in one particular embodiment can be 30 Î¼m in diameter and 150 Î¼m deep. The resist 217 should be thick enough to support etching through the stack (e.g., 1.1 Î¼m buried dielectric layer 117 plus 14 Î¼m membrane layer 120 plus 5.15 Î¼m thick dielectric layer 106 plus 130 Î¼m thick first (e.g., silicon) substrate 101, to blind etch the embedded vias referred 219 which can also be referred to as to as TSV holes. Separate etch tools may be used for the oxide and Bosch silicon etches.

The resist 217 is then stripped and a TSV dielectric liner 131 (e.g. a dielectric oxide 0.5 Î¼m thick) is deposited or is thermally grown within the embedded vias 219. A diffusion barrier metal layer can be formed and added onto on the TSV dielectric liner 131 to frame the TSVs and protect against escape of the subsequently deposited TSV filler material (167, see FIG. 2C) into the semiconductor (e.g., silicon) in the case of highly mobile metal TSV filler materials, such as copper. For example, in one particular embodiment, following formation of the dielectric liner 131, a 0.0875 Î¼m Ta/TaN diffusion barrier metal layer then a 1.5 Î¼m Cu seed layer 233 (see FIG. 2C) is deposited for copper filled TSV embodiments. The seed layer 233 can, for example, represent a copper and titanium seed layer.

A Mask â€œCUMOLDâ€ (Mask #3) can exclude copper (or other metal) plating over the MEMS sensor cell(s) of each MEMS sensor device. Negative resist can be used to ensure the TSVs are resist-free after masking. The mask can be helpful since the MEMS electrode 120b (e.g. a Si plate) may be deflected by several microns and the subsequent copper chemical mechanical polishing (CMP) step in the case of copper filled TSVs may not fully remove the copper over the MEMS sensor cells.

FIG. 2C shows a cross sectional depiction after electroplating a metal such as copper (e.g., Ëœ15 Î¼m thick) to provide a TSV filler material 167 onto a seed layer 233 (a Cu seed layer for Cu) to fill the embedded vias/TSV holes 219 lined with dielectric liner 131 and a diffusion barrier metal layer and resist strip to form TSVs 112 and 111 having TSV filler material 167 therein. Although the dielectric liner 131 is shown along the full length of the TSVs 111 and 112 including on the thick dielectric region 106, in the case of a thermally formed dielectric liner 131 (e.g., silicon oxide), as opposed to a deposited dielectric liner 131, the dielectric liner 131 will not grow on the thick dielectric region 106 and thus not be on the thick dielectric region 106. The diffusion barrier metal layer (e.g., for copper TSV filler material 167) is not shown for simplicity. A TSV Cu CMP process can be used to remove the copper (or other TSV filler material) â€œnail headsâ€ over the TSVs 112, 111 and lateral to the nail heads. A TSV filler material anneal can follow.

A second TSV copper CMP can be used to remove all the remaining copper and diffusion barrier metal layer (e.g., Ta/TaN). A wet strip may be used to clear residue over the sensor cell. The dielectric liner 131 along with the buried dielectric layer 117 stopping on the MEMS electrode 120b (e.g. a Si plate) are then removed.

FIG. 2D shows a cross sectional depiction after depositing metal layer 251, such as 0.5 Î¼m AlCu. This metal layer 251 will provide the MEMS electrode (e.g., Si plate) 120b metallization thereon and connect to the TSV structures. A mask level â€œALTOPâ€ (Mask #4) having resist 256 shown in FIG. 2D is used to define the metal layer 251 over the capacitive MEMS sensing cells. The ALTOP critical dimensions (CDs) can be 1 Î¼m/side smaller than the final MEMS electrode 120b (e.g. a Si plate) dimension. Patterning the metal layer 251 before patterning the membrane layer 120 to form the MEMS electrode 120b (e.g. a Si plate) helps avoid both the metal layer 251 and resist step coverage issues. A wet etch can be used to etch the metal layer 251 from the field area. The resist 256 is then stripped.

FIG. 2E shows a cross sectional depiction after a mask level â€œPLATESIâ€ (Mask #5) uses a resist pattern 257 to completely encapsulate the patterned metal layer 251. The plate mask can be about 1 Î¼m/side larger than the metal layer 251 (ALTOP) mask. The depiction in FIG. 2E is after etching the membrane layer 120 to form the MEMS electrode 120b (e.g. a Si plate) and to separate the capacitive MEMS sensor cells for capacitive MEMS sensor devices having a plurality of capacitive MEMS sensor cells. Regarding separation, assuming the size of a capacitive MEMS sensor cell is defined as the dimension of the inner cavity 144 of the third (capping) substrate 140, the capacitive MEMS sensor cells in adjacent capacitive MEMS sensor elements can be separated by the etching of the membrane layer 120 by a distance of 30 Î¼m to 70 Î¼m (typically at least 5 Î¼m), for example, to ensure robust wafer bonding with good vacuum integrity. The etch of the membrane layer 120 generally stops on the thick dielectric layer 106 as shown and also etches through the membrane layer 120 to form the MEMS electrode 120b (e.g. a Si plate) releasing the MEMS electrode 120b which functions as an oscillator. A Bosch etch can be used with a short cycle to minimize side wall scalloping. The etch should not generally be reentrant. All of the metal layer 251 will be covered with resist during this operation.

The resist pattern 257 is then stripped. A final alloy at 400Â° C. in N₂+H₂for 30 minutes can then be performed.

FIG. 2F shows a cross sectional depiction after the mask level â€œcavityâ€ (Mask #6) including resist pattern (cavity mask) 258 which can be applied to a third capping substrate (e.g., wafer) 140, and used to vacuum cap each capacitive MEMS sensing cell. This masking level will define a unique cavity for each capacitive MEMS sensing cell for each MEMS device/die on the MEMS wafer. The inner cavities 144 in the third capping substrate (e.g., wafer) 140 can be 20 Î¼m deep etched cavities in one particular embodiment to form a cavity wafer 280 having inner cavity 144 and outer protruding portions 146. A Bosch etch can be used for the cavity etch. After the cavity etch the resist pattern 258 can be wet stripped to ensure a clean surface for wafer bonding.

FIG. 2G shows a cross sectional depiction after vacuum bonding the MEMS wafer stack (first substrate 101 with membrane layer 120 thereon including fixed electrode 120a and MEMS electrode 120b, with TSVs 111, 112) to the cavity wafer 280, followed by exposing the tips 111a and 112a of TSVs 111, 112, respectively. In the case of vacuum bonding, after vacuum bonding the resulting MEMS sensor cell(s) 100a have their own vacuum sealed cavity including an upper vacuum cavity provided by inner cavity 144 and MEMS cavity 114. A 4 hour 400Â° C. anneal can be used for the vacuum bonding. Backgrinding can be used to thin the first substrate 101 from the bottom side 103 to almost reach the embedded TSVs.

In one embodiment, the backgrind can remove all backside films and about 550 Î¼m of the first substrate 101 leaving about 175 Î¼m. Etching the first substrate (e.g., Si) 101 to expose the tips 111a and 112a of the TSVs 111, 112 can leave about 100 Î¼m of the first substrate 101 (e.g., Si). One can utilize a XeF plasma etch or wet Si etch. The dielectric liner 131 (e.g., a silicon oxide liner) and the barrier metal layer (if present) are then etched from the tips 111a and 112a of the TSVs 111 and 112. A plasma etch of the dielectric liner 131 and barrier metal will leave dielectric (e.g., oxide) spacers on the sidewalls of the TSVs 111 and 112.

The resulting bonded wafer having vacuum bonded cavity wafer 280 (e.g., third capping substrate (e.g., wafer) 140 725 Î¼m thick with inner cavities 144) on the MEMS wafer stack can then be diced which directly provides packaged capacitive MEMS sensor devices/die. Optional back side metal can be a process step which enables contacts to the bottom side 103 of the first substrate 101 to utilize the first substrate 101 as an electrode for embodiments having a third electrode, such as 3-D sensing applications as described above. The backside metal flow can replace the dielectric liner 131 and barrier metal etch processes.

For backside metal processing, backside metal layer 259 is deposited, such as 1000 â„« Ti+2800 â„« Ni+1500 â„« Ag in one particular embodiment. The bottom side 103 of the first substrate 101 should be clean before deposition. A pre-sputter etch of about 300 â„« can be used for cleaning the surface. A mask level â€œTSVEXPâ€ (Mask #7) can be used protect the backside metal layer 259 while it is stripped from the tips 111a and 112a of the TSVs 111 and 112.

The backside metal flow can begin after the TSV tip exposure process step. The backside metal layer 259 (e.g., TiNiAg) is etched from the tips of the TSVs 111 and 112. The dielectric liner 131 and the barrier metal layer (for copper filled TSVs) are then etched from the tips of the TSVs 111 and 112. A plasma etch of the dielectric liner 131 and barrier metal will leave dielectric (e.g., oxide) spacers on the sidewalls of the TSVs 111 and 112. The resist is then stripped.

FIG. 2H shows a cross sectional depiction after optional backside metal 259 pattern formation. The resulting bonded wafer having a vacuum bonded cavity wafer 280 (e.g., 725 Î¼m thick third capping substrate (e.g., wafer) 140 with inner cavities 144) on the MEMS wafer stack having a backside metal layer 259 can then be diced which directly provides packaged capacitive MEMS sensor devices/die.

FIG. 3 is a top view depiction an example capacitive MEMS sensor device (die) 300 including a plurality of capacitive MEMS sensor elements 301-306, with each capacitive MEMS sensor element including four of the capacitive MEMS sensor cells shown in FIGS. 1A and 1B shown as 100a-100d coupled together, according to an example embodiment. Although the capacitive MEMS sensor device 300 is shown having six capacitive MEMS sensor elements each having four capacitive MEMS sensor cells 100a-100d, disclosed capacitive MEMS sensor devices can have any number of capacitive MEMS sensor elements, and each capacitive MEMS sensor element can have any number of capacitive MEMS sensor cells. As described above, the top electrodes can be separate for the capacitive MEMS sensor elements 301-306 allowing separate addressing of the respective elements using a single TSV for each element. The respective capacitive MEMS sensor elements can be driven/sensed differentially to improve common mode signals or mitigate manufacturing asymmetries.

In a typical sensing operation, a dc bias voltage is applied to one or more MEMS electrodes 120b through TSV 111. The TSV 112 can be referenced to ground. The mechanical movement of the MEMS electrode 120b is detected capacitively between TSV 111 and TSV 112. Standard biasing circuits can be used to DC couple the bias voltage between the fixed electrode 120a and MEMS electrode 120b and AC couple the sensing or driving signal thereto. If the first substrate 101 is not part of the signal path for capacitive detection, there is generally no need for a low resistivity (e.g., 0.01 Î©-cm) first substrate 101.

It is noted generally all thicknesses and dimensions can be adjusted to fit specific applications. There are also a variety of alternate embodiments. For example, the protruding TSV tips for the TSVs are optional. Substantially flush TSV tips can be used with a redirect layer (RDL) for connecting the TSVs to pads lateral to the TSVs. The RDL layer can be formed on a dielectric film on the bottom side 103 of the first substrate 101 (e.g., a silicon wafer). If the TSV tips are flush with surface of the bottom side 103 (e.g., Si), they would be slightly recessed after a thin oxide (e.g., Ëœ5,000 A thick) was deposited and patterned to re-expose the TSVs.

Disclose embodiments provide several significant advantages. By including TSVs and sealing the fully released MEMS structures with a bonded cap (e.g., vacuum fusion bonded cap), there is no need to use a sacrificial release layer or seal release holes with a plasma deposited capping layer. In addition, the MEMS electrode 120b for resonating is formed from a single crystal material (e.g., single crystal silicon). Disclosed embodiments enable small die and packages along with reduced cost since the capacitive MEMS sensor device/die provides its own package.

SOI defined structures, such as the membrane layer 120 for forming the MEMS electrodes 120b generally have good thickness uniformity for device matching for sensor array arrangements, and provide very good matching for resonators, filters, etc. Disclosed fusion bonding provides a superior hermetic seal and better vacuum as compared to the seal obtained from conventional release layers. The third capping substrate being generally a thick wafer (e.g., a thick Si wafer) will provide good mechanical isolation.

Disclosed embodiments can be used to form semiconductor die that may integrated into a variety of assembly flows to form a variety of different devices and related products. Those skilled in the art to which this disclosure relates will appreciate that many other embodiments and variations of embodiments are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of this disclosure.