BACKGROUND

1. Technical Field

The present disclosure relates to a signal amplifier circuit for USB ports.

2. Description of Related Art

Universal serial bus (USB) technology is broadly applied as a solution to serial communications. The USB 3.0 specification was published on Nov. 12, 2008. The USB 3.0 specification's main goals were to increase the data transfer rate (up to 5 Gbit/s), to decrease power consumption, to increase power output, and to be backwards-compatible with USB 2.0. USB 3.0 includes a new, higher speed bus called super speed in parallel with the USB 2.0 bus. The signals usually tend to attenuate in USB 3.0 during transmission for a long distance on printed circuit boards. Therefore, the quality of the signals is affected.

Therefore there is a need for improvement in the art.

BRIEF DESCRIPTION OF THE DRAWINGS

Many aspects of the embodiments can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.

FIG. 1 is a block diagram of an embodiment of a signal amplifier circuit for USB port.

FIG. 2 is a circuit diagram of the signal amplifier circuit of FIG. 1.

DETAILED DESCRIPTION

The disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to â€œanâ€ or â€œoneâ€ embodiment in this disclosure are not necessarily to the same embodiment, and such references mean â€œat least one.â€

FIG. 1 illustrates a block diagram of a signal amplifier circuit for USB ports in accordance with one embodiment. The signal amplifier circuit includes a USB controller 100, an amplifier circuit 200, and a USB port 300. The amplifier circuit 200 amplifies differential signals transmitted between the USB controller 100 and the USB port 300. In one embodiment, the USB port 300 is a USB 3.0 port.

FIG. 2 illustrates a circuit diagram of the signal amplifier circuit in accordance with one embodiment. The USB controller 100 includes a super speed transmitter differential pair SSTX+, SSTXâˆ’, a super speed receiver differential pair SSRX+, SSRXâˆ’, and two first differential signal receiving and transmitting terminals D+, Dâˆ’. The amplifier circuit 200 includes two first input terminals RX1+, RX1âˆ’, two second input terminals RX2+, RX2âˆ’, two first output terminals TX1+, TX1âˆ’, and two second output terminals TX2+, TX2âˆ’. The USB port 300 includes two first differential signal receiving terminals 301, 302, two first differential signal transmitting terminals 303, 304, and two second differential signal receiving and transmitting terminals 305, 306. The super speed transmitter differential pair SSTX+, SSTXâˆ’ are electrically connected to the first input terminals RX1âˆ’, RX1+. The super speed receiver differential pair SSRX+, SSRXâˆ’ are electrically connected to the second output terminals TX2âˆ’, TX2+. The first output terminals TX1âˆ’, TX1+ are electrically connected to the first differential signal receiving terminals 301, 302. The second input terminals RX2âˆ’, RX2+ are electrically connected to the first differential signal transmitting terminals 303, 304. The first differential signal receiving and transmitting terminals D+, Dâˆ’ are electrically connected to the second differential signal receiving and transmitting terminals 305, 306.

The amplifier circuit 200 includes a first amplifier U1 and a second amplifier U2. The first amplifier U1 is electrically connected to the first input terminals RX1âˆ’, RX1+ and the first output terminals TX1âˆ’, TX1+. The second amplifier U2 is electrically connected to the second input terminals RX2âˆ’, RX2+ and the second output terminals TX2âˆ’, TX2+. In one embodiment, the first differential signal receiving and transmitting terminals D+, Dâˆ’ and the second differential signal receiving and transmitting terminals 305, 306 support the USB 2.0 specification. The super speed transmitter differential pair SSTX+, SSTXâˆ’ and the super speed receiver differential pair SSRX+, SSRXâˆ’ support the USB 3.0 specification.

In operation, the data of USB 3.0 specification stored in the USB controller 100 is transmitted to the first amplifier U1 from the super speed transmitter differential pair SSTX+, SSTXâˆ’ to the first input terminals RX1âˆ’, RX1+. The data of USB 3.0 is amplified by the first amplifier U1 and is then transmitted to the USB port 300 from the first output terminals TX1âˆ’, TX1+ to the first differential signal receiving terminals 301, 302. The data of USB 3.0 specification from the USB port 300 is transmitted to the second amplifier U2 via the second input terminals RX2âˆ’, RX2+. The data of USB 3.0 is amplified by the second amplifier U2 and is then transmitted to the USB controller 100 from the second output terminals TX2âˆ’, TX2+ to the super speed receiver differential pair SSRX+, SSRXâˆ’. The data of USB 2.0 specification stored in the USB controller 100 is transmitted to the USB port 300 from the first differential signal receiving and transmitting terminals D+, Dâˆ’ to the second differential signal receiving and transmitting terminals 305, 306. The data of USB 2.0 specification from the USB port 300 is transmitted to the USB controller 100 via the second differential signal receiving and transmitting terminals 305, 306 to the first differential signal receiving and transmitting terminals D+, Dâˆ’.

Even though numerous characteristics and advantages of the present disclosure have been set forth in the foregoing description, together with details of the structure and function of the disclosure, the disclosure is illustrative only, and changes may be made in detail, especially in the matters of shape, size, and arrangement of parts within the principles of the disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.