BACKGROUND

The present invention relates generally to integrated circuit memory devices and, more particularly, to port enable signal generation for gating a memory array device output.

As will be appreciated by those skilled in the art, in a domino Static Random Access Memory (SRAM), the individual cells do not employ sense amplifiers to sense the differential voltage on the bit line pairs coupled to the cross-coupled inverters that store the data. Rather, for a domino SRAM, the local bit line is precharged, discharged, and the discharge is detected. The local bit line, the means to precharge the local bit line, and the detector define a dynamic node of the domino SRAM. An output latch, such as a jam latch or keeper latch is used to capture data output from a domino SRAM. The jam latch temporarily holds the data so that a subsequent device or circuit can read the data.

In order to prevent fast arriving data from the array from being written into the output latch (and corrupting the previous cycle's data), a port enable signal may be generated for controlling a transmission gate coupled between the array output and the output latch. More specifically, the port enable signal is a domino signal that is used as the gate signal for one or more transmission gates in order to gate the array output to the output latch. Since an early array output (for example, from fast read or write through) could corrupt the output latch contents or cause an undesirable power increase (fighting the restore before evaluate), gating with the port enable signal allows subsequent logic using the output latch contents to have an expanded sample time. On the other hand, another way to prevent fast write data from being written to the output latch may be to use a read enable signal to gate off write data. However, gating off write data would still not prevent a fast cell's read data from causing hold time problems (latch corruption or power increase) at the latch.

SUMMARY

In an exemplary embodiment, a method of generating a dynamic port enable signal for gating memory array data to an output node includes generating a programmable leading edge clock signal derivation of an input dynamic clock signal; generating a programmable trailing edge clock signal derivation of the input dynamic clock signal, wherein the leading edge clock signal derivation and the trailing edge clock signal derivation are independently programmable with respect to one another; and gating the generated programmable leading and trailing edge clock signal derivations with a static input enable signal so as to generate the port enable signal such that, when inactive, the port enable signal prevents early memory array data from being coupled to the output node.

In another embodiment, a circuit for generating a dynamic port enable signal for gating memory array data to an output node includes a first dynamic transistor stack, the first dynamic transistor stack having a programmable leading edge clock signal derivation of an input dynamic clock signal, a programmable trailing edge clock signal derivation of the input dynamic clock signal, and a static input enable signal as inputs thereto, wherein the leading edge clock signal derivation and the trailing edge clock signal derivation are independently programmable with respect to one another; the first dynamic transistor stack having an intermediate output node, an inverted value of which defines the dynamic port enable signal, with the dynamic port enable signal being generated by the leading edge clock signal derivation, the trailing edge clock signal derivation and the static input enable signal; wherein the port enable signal, when inactive, prevents early memory array data from being coupled to the output node.

In another embodiment, a memory array output control circuit, includes a transmission gate that selectively couples an array output bit line to an output latch, the transmission gate controlled by a dynamically generated port enable signal; a port enable generation circuit that generates the port enable signal, the port enable generation circuit comprising a first dynamic transistor stack, the first dynamic transistor stack having a programmable leading edge clock signal derivation of an input dynamic clock signal, a programmable trailing edge clock signal derivation of the input dynamic clock signal, and a static input enable signal as inputs thereto, wherein the leading edge clock signal derivation and the trailing edge clock signal derivation are independently programmable with respect to one another; and the first dynamic transistor stack having an intermediate output node, an inverted value of which defines the port enable signal, with the port enable signal being generated by the leading edge clock signal derivation, the trailing edge clock signal derivation and the static input enable signal; wherein the port enable signal, when inactive, prevents early memory array data from the array output bit line from being captured at the output latch.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

Referring to the exemplary drawings wherein like elements are numbered alike:

FIG. 1 is a schematic diagram of a memory array output control circuit employing a port enable signal generated in accordance with an embodiment of the invention;

FIG. 2 is a schematic diagram of a circuit for generating the dynamic port enable signal of FIG. 1 with individually controllable rising and falling edges;

FIG. 3 is a schematic diagram of a pair of delay blocks for generating both programmable rising and falling edge clock signals used as inputs to the circuit of FIG. 2;

FIG. 4 is a schematic diagram illustrating the operation of the delay blocks in further detail; and

FIG. 5 is a timing diagram illustrating the operation of the memory array output circuit with the programmable port enable signal.

DETAILED DESCRIPTION

Disclosed herein is a method and apparatus for generating a programmable port enable signal that gates a memory array device output to a latch. The ability to generate a programmable dynamic pulse that works well across all process corners is a significant feature that is desirable for many applications. Briefly stated, the embodiments herein utilize two separate programmable delay blocks to provide independent, dual edge programmability. An additional feature disclosed herein is a chopper device configured within the port enable generation circuit domino stack that reduce the required hold time on a static input signal that is used to gate the port enable signal. Although a more conventional chopper could be used to generate the entire port enable pulse, such an approach would only utilize the leading edge of the input clock pulse, and thus the resulting port enable signal would not track the clock pulse as the pulse expands or shrinks with variations in process, temperature, and power supplies. As will be set in further detail below, the dual edge programmable port enable signal generated by the techniques disclosed herein prevent fast data from the array from being written into the output latch.

Referring initially to FIG. 1, there is shown a schematic diagram of a memory array output control circuit 100 employing a port enable signal generated in accordance with an embodiment of the invention. As is shown, the output control circuit includes a transmission gate TG, comprising parallel connected NFET (n-type field effect transistor) and PFET (p-type field effect transistor) devices, that selectively couples a global bit line (GBL) array output to one or more pull up PFET transistors PL. In the simplified schematic of FIG. 1, pull up PFET PL is coupled to an output node 102 and output (jam) latch 104. The jam latch holds data from a prior cycle, until such time as the output latch 104 is reset or precharged to a logic low (0) state by the reset_before_evaluate signal, in accordance with p-type domino circuit topology. It will be appreciated, however, that the principles herein are equally applicable to n-type domino circuit topology.

At the beginning of the cycle, when the port enable signal is deactivated (low), the transmission gate TG is off, which isolates the GBL/array output from the output circuit. In addition, a restore PFET PR precharges the gate of the pull up PFET PL high, preventing it from conducting and charging the output node 102. During this time, the reset_before_evaluate signal pulses high to reset the output latch 104 to a logic low (0) state. Once the programmable port enable signal fires (high) the transmission gate TG is conductive, and the array data is sampled and written into the latch 104. In the case where the array data is logic 1 (opposite that of the logic 0), a pull down device (not shown in FIG. 1) pulls down the voltage on the GBL/array output, in turn activating PL, and charging output node 102 high and writing a logic 1 into the latch 104. Conversely, when the array data is logic 0, the voltage on the GBL/array output remains high so as not to activate PL, and the output latch 104 retains its reset (logic 0) state.

Again, it will be appreciated that the memory array output control circuit 100 of FIG. 1 is a simplified example of such a device to illustrate how a port enable signal is used in this context. For example, where redundancy is utilized, the array output circuit 100 may also include another transmission gate in parallel to TG to provide steering capability.

Referring now to FIG. 2, there is shown a schematic diagram of a circuit 200 for generating the dynamic port enable signal of FIG. 1 with individually controllable rising and falling edges, in accordance with a further embodiment of the invention. In essence, the port enable signal is generated by ANDing logical derivations of a dynamic clock signal (which activates high during a read) with a static input signal, Static_In (i.e., a byte enable signal). Here, the logical derivations of the dynamic clock signal are represented as Clk_LE (a programmed leading edge clock signal) and Clk_TE (a programmed trailing edge clock signal). The dynamic clock signal is generated using dummy predecoders in order to provide better tracking with the word line predecoder path.

The dynamic port enable signal generation circuit 200 includes a first dynamic transistor stack 202 and a second dynamic transistor stack 204. At the beginning of the cycle, the dynamic clock (and hence Clk_LE and Clk_TE) is low, thus PFETs P1 and P2 in the first stack 202 maintain an intermediate dynamic node 206 at logic high. The port enable signal, being the inverted value of the intermediate dynamic node 206, is also low. When the dynamic clock goes high, both Clk_LE and Clk_TE go high, and the Static_In data is sampled. If Static_In is also high, the intermediate dynamic node 206 falls through conductive NFETs N1, N2 and N3 in the first stack 202, causing the port enable signal to rise. In the case of N2, it will be noted that the gate input (clk_b) thereto is the output of an odd numbered inverter delay stage 208. While clk_b is the logical opposite of Clk_LE, the delay stage 208 does not instantaneously change from 1 to 0 when Clk_LE goes high.

As a result, the signal clk_b acts as a chopping signal effectively shutting off the evaluate stack (i.e., first stack 202) before Clk_LE falls. This allows the hold time of Static_In to be set to clk_b fall instead of Clk_LE fall. In other words, the chopper device, N2, effectively shortens the hold time of Static_In. Then, at the end of the cycle, when the dynamic clock falls, Clk_LE will fall first, followed by Clk_TE. Because the Clk_LE and Clk_TE PFETs (P1 and P2) are stacked, the later of the two falling edges (i.e., Clk_TE) ultimately controls the falling edge of the port enable signal. Thus, it will be seen that since the rising edge of Clk_LE controls the rising edge of the port enable signal, while the falling edge of Clk_TE controls the falling edge of the port enable signal, then the port enable signal is now programmable on both edges. Furthermore, since the leading edge and the falling edge of the dynamic clock signal are used to generate the port enable signal, it is able to track with the word line across various corners.

In order to prevent collisions and to hold a logic state on the intermediate dynamic node 206, the second dynamic transistor stack 204 includes a plurality of gated NFET and PFET devices. For example, keeper NFET N4 and PFET P3 are gated by the port enable signal, keeper NFET N5 is gated by Clk_TE, and keeper PFET P4 is gated by clk_b. In addition, another PFET P5 is coupled to Static_In to reduce the effects of charge sharing on the dynamic node 206, in the event where Clk_LE and clk_b are both high, but Static_In stays low.

Another consideration of the above described port enable generation circuit is to skew the inverter delay stage 208 towards the rising edge of clk_b so that the clk_b rise does not gate the next cycle's port enable rise. For example, if the duty cycle of Clk_LE is relatively high (e.g., high for 80 picoseconds (ps) and low for only 10 ps before going back high again), the port enable should fire in back to back cycles, assuming Static_In is high. When the current cycle's Clk_LE falls, it triggers clk_b to rise, setting up to the next cycle's Clk_LE rise; thus, if the Clk_LE fall to Clk_b rise delay is too long (e.g., 20 ps), then the port enable rise in the second cycle would be triggered by a late clk_b rise, instead of the Clk_LE rise as desired. In other words, the inverter delay stage 208 is set such that the chopper path is reset in time for the next cycle's Clk_LE.

In addition, Static_In is setup to Clk_LE. The presence of the chopper device means only that the hold time (not the setup time) of Static_In is set to clk_b. In the beginning of a cycle, Clk_LE=0, and clk_b=1. Assuming for example that in a previous cycle, Static_In is set to 1, and then the port enable fired in the previous cycle. Assuming further that is not desired for port enable to fire in the current cycle, then Static_In has to be set to 0. However, if the Static_In low signal comes in after Clk_LE rises, the domino stack will pull down and cause a false port enable to fire. Accordingly, Static_In is set up to Clk_LE and is set before Clk_LE rises.

FIG. 3 is a schematic diagram of a pair of delay blocks 302a, 302b for generating both programmable rising and falling edge clock signals (Clk_LE, Clk_TE) used as inputs to the circuit 200 of FIG. 2. As is shown, a first delay block 302a receives the dynamic clock signal (Dyn_Clk), as well as a first set of programmable bits (F1_LE, F2_LE, F3_LE) as inputs thereto. The first set of programmable bits may originate from, for example scan latches. Depending upon the values of this first set of bits, the pull down strength of an inverter included in the first delay block 302a is altered, thus resulting in a programmable falling edge of an intermediate output signal 304. In order to create, therefore, a programmable leading edge clock signal derivation of the dynamic clock signal Dyn_Clk, the intermediate output signal 304 is inverted with inverter 306, thereby resulting in Clk_LE. As will be illustrated in further detail below, where the F1_LE, F2_LE, F3_LE inputs are all high, the first programmable delay block 302 and inverter 306 generates a faster rising edge for Clk_LE. Where the F1_LE, F2_LE, F3_LE inputs are all low, the first programmable delay block 302 and inverter 306 generates a slower rising edge for Clk_LE, with programmable values in between the two extremes.

As further illustrated in FIG. 3, the intermediate output signal 304 is also coupled to a second delay block 302b, which operates similar to the first delay block 302a. Since the second delay block 302b is another inverter stage, its output (Clk_TE) is logically equivalent to Dyn_Clk, and acts as a programmable falling edge derivative of the dynamic clock. More significantly, it will be noted that the second delay block 302b has a second set of programmable bits (F1_TE, F2_TE, F3_TE) as inputs thereto, which are independent from the first set of programmable bits. Similar to the rising edge signal, where if the F1_TE, F2_TE, F3_TE inputs are all high, the falling edge of Clk_TE occurs sooner, and where if the F1_TE, F2_TE, F3_TE inputs are all low, the falling edge of Clk_TE occurs later.

FIG. 4 is a schematic diagram illustrating the operation of the delay blocks 302a, 302b in further detail. The delay block receives an input signal (In) and produces an inverted output signal (Out). As can be seen, since there are no devices coupled between PFET P6 and the logic high power supply rail, the state of the programmable bits F1, F2 and F3 do not affect the pull up time (i.e., the rising edge) of the output signal. However, located between NFET N6 and the logic low power supply rail, the delay block includes a plurality of footer NFET devices (N7, N8, N9 and N10). NFET N7 is arranged in an always on state, while the gates of N8, N9 and N10 are respectively controlled by the programmable bits F1, F2 and F3. Thus, in the scenario where F1, F2 and F3 are all 0, the programmed falling edge of the output signal is the slowest, as the output has to discharge through internal nodes 402 and 404, via the series combination of N6, N11, N12 and N7. N11 and N12 are also respectively in series with N9 and N10, and are gated by the input signal to the delay block.

Also included in the delay block are PFETs P7 and P8, which prevent keeper PFETS P9 and P10, respectively, from opposing the discharge of internal nodes 402 and 404 during a rising input signal where F2 and F3 are programmed to 0. In the slow scenario (F2 and F3=0), P9 and P10 maintain the internal nodes at logic high when the input signal is so as to allow for a slower discharge of the output when the input signal transitions high.

In the scenario where F1, F2 and F3 are all 1, parallel discharge paths are created for the output node, thus the programmed falling edge of the output signal is the fastest.

Finally, FIG. 5 is a timing diagram illustrating the operation of the memory array output circuit with the dual programmable edge port enable signal. As described above, both edges of port enable signal are programmable, as reflected by the shaded regions at the rising and falling edges of the signal. In addition, the hold time of Static_In input is determined by the falling edge of clk_b rather than the falling edge of Clk_LE, resulting in a shorter hold time. A comparison between the memory latch output, both with and without the generated port enable signal is also demonstrated in FIG. 5. Without such a port enable signal, the current cycle latched output data 502, Latch Out (No PE), is corrupted at 504 by early arriving Array Out data 506 since this data is not gated. In contrast, with the presence of the port enable signal as generated herein, the same early arriving Array Out data 506 does not corrupt the current cycle latched output data 508, Latch Out (PE) due to the inactive port enable signal at that time.

It will be noted that if the rising edge of Port Enable is after the rising edge of the array output (506 of FIG. 5), it will gate the data launch out of the array. Since the leading edge of port enable can set the time when the data is launched out of the array and it also affects the evaluate time of the dynamic node (102 of FIG. 1), it is desirable to have the leading edge be programmable. Since the trailing edge of port enable is used to block the next cycle's fast read or write through data from corrupting the latched result of the current cycle and it also affects the evaluate time of the dynamic node (102 of FIG. 1), it is desirable to have the trailing edge be programmable.

While the invention has been described with reference to a preferred embodiment or embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.