CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the priority benefit of Italian patent application number TO2009A000977, filed on Dec. 11, 2009, entitled â€œCircuit for Generating a Reference Electrical Quantity,â€ which is hereby incorporated by reference to the maximum extent allowable by law.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a circuit for generating a reference electrical quantity.

2. Discussion of the Related Art

As is known, the majority of electronic devices requires a respective current source, which should be able to supply a reference current as constant as possible in regard to the temperature shifts and to variations in the supply voltage of the electronic devices themselves. In fact, the more the reference current supplied by a current source is stable, the more the overall performance of the electronic device that uses said reference current is stable.

Likewise, it should be noted that numerous electronic devices necessitate a reference voltage, which must also be as constant as possible in regard to temperature shifts and to variations in the supply voltage. For this purpose, various types of reference-voltage sources are known, such as for instance the so-called â€œbandgap circuitsâ€ , which are able to deliver a reference voltage generally close to 1.22 V.

In particular, circuits are known that, in order to reduce the dependence upon temperature, generate a reference current and/or a reference voltage on the basis of a current I_PTATand a current I_NTAT. In detail, the current I_PTATis generated so as to be directly proportional to the temperature with a positive temperature coefficient, whereas the current I_NTATis generated so as to be proportional to the temperature, but with a negative temperature coefficient.

By way of example, FIG. 1 shows a voltage and current generator circuit 1, which enables generation of both the reference current and the reference voltage. Said voltage and current generator circuit 1 comprises a first self-biasing circuit 2 and a second self-biasing circuit 4 and moreover comprises a voltage output stage 6 and a current output stage 8. The first self-biasing circuit 2 and the second self-biasing circuit 4, as likewise the voltage output stage 6 and the current output stage 8, are connected between a supply terminal N_DD, which can be appropriately connected to a supply voltage V_DD, and ground.

In greater detail, the first self-biasing circuit 2 comprises a first biasing transistor T₁and a second biasing transistor T₂, of a P-channel MOS type, which are connected to form a first current mirror. In particular, the source terminals of the first and second biasing transistors T₁, T₂are connected to the supply terminal N_DD, whilst the gate terminals of the first and second biasing transistors T₁, T₂are connected to one another; moreover, the second biasing transistor T₂is diode-connected; i.e., it has its drain terminal connected to its gate terminal. In what follows, to indicate the gate terminals of the first and second biasing transistors T₁, T₂reference is made to the node N_PTAT.

The first self-biasing circuit 2 further comprises a first resistor R_Aand a first bipolar transistor T_bjt1and a second bipolar transistor T_bjt2.

In particular, in the example shown in FIG. 1, the first and second bipolar transistors T_bjt1, T_bjt2are of an npn type. The collector terminals of the first and second bipolar transistors T_bjt1, T_bjt2are connected, respectively, to the drain terminals of the first and second biasing transistors T₁, T₂. In addition, the base terminals of the first and second bipolar transistors T_bjt1, T_bjt2are connected to one another, and the first bipolar transistor T_bjt1is diode-connected; i.e., it has its respective base terminal connected to its respective collector terminal. Again, the emitter terminal of the first bipolar transistor T_bjt1is connected to ground, whilst the emitter terminal of the second bipolar transistor T_bjt2is connected to the first resistor R_A, which is moreover connected to ground.

The second self-biasing circuit 4 comprises a third biasing transistor T₃and a fourth biasing transistor T₄of a P-channel MOS type, which are connected to form a second current mirror. In particular, the source terminals of the third and fourth biasing transistors T₃, T₄are connected to the supply terminal N_DD, whilst the gate terminals of the third and fourth biasing transistors T₃, T₄are connected to one another; moreover, the fourth biasing transistor T₄is diode-connected. In what follows, to indicate the gate terminals of the third and fourth biasing transistors T₃, T₄reference is made to the node N_NTAT.

The second self-biasing circuit 4 further comprises a second resistor R_B, a third bipolar transistor T_bjt3, and a fifth biasing transistor T₅. In particular, the fifth biasing transistor T₅is of an N-channel MOS type; moreover, in the example shown in FIG. 1, the third bipolar transistor T_bjt3is of an npn type.

The drain terminal of the fifth biasing transistor T₅is connected to the drain terminal (and hence also to the gate terminal) of the fourth biasing transistor T₄. Instead, the gate terminal and the source terminal of the fifth biasing transistor T₅are connected, respectively, to the drain terminal of the third biasing transistor T₃and to the base terminal of the third bipolar transistor T_bjt3.

In addition, the collector terminal of the third bipolar transistor T_bjt3is connected to the drain terminal of the third biasing transistor T₃and hence also to the gate terminal of the fifth biasing transistor T₅, whilst the emitter terminal of the third bipolar transistor T_bjt3is connected to ground. Finally, the second resistor R_Bis connected between ground and the base terminal of the third bipolar transistor T_bjt3.

The voltage output stage 6 comprises an output resistor R_OUTand a first sum transistor T_s1and a second sum transistor T_s2, both of a P-channel MOS type. The source terminals of said first and second sum transistors T_s1, T_s2are connected to the supply terminal N_DD, whilst the gate terminals are connected, respectively, to the node N_NTATand to the node N_NTAT, and the drain terminals are connected to one another; consequently, the first and second sum transistors T_s1, T_s2concur to form, respectively, the aforementioned first and second current mirrors. The output resistor R_OUTis instead connected between ground and the drain terminals of the first and second sum transistors T_s1, T_s2.

The current output stage 8 comprises a third sum transistor T_s3and a fourth sum transistor T_s4, both of a P-channel MOS type. The source terminals of said third and fourth sum transistors T_s3, T_s4are connected to the supply terminal N_DD, whilst the gate terminals are connected, respectively, to the node N_PTATand to the node N_NTAT, and the drain terminals are connected to one another and define an output node N_OUT. Consequently, the third and fourth sum transistors T_s3, T_s4concur to form, respectively, the aforementioned first and second current mirrors.

In greater detail, the first, second, third and fourth biasing transistors T₁-T₄are the same (but for the inevitable tolerances) and hence are characterized by one and the same aspect ratio W/L, which as is known indicates, given a generic MOS transistor, the ratio between the width and the length of the corresponding channel. Instead, the first, second, third, and fourth sum transistors T_s1-T_s4are such that the aspect ratios are, respectively, Î³Â·W/L, Î±Â·W/L, Î´Â·W/L, and ÎµÂ·W/L, where Î±, Îµ, Î³, Î´ are mirror ratios, described hereinafter.

Operatively, it may be shown that, when the supply voltage V_DDis present on the supply terminal N_DD, in the collector terminal of the second bipolar transistor T_bjt2there circulates a current I_C2, which is equal to the current that circulates in the first biasing transistor T₁. Said current I_C2is hence equal to the sum of the currents I_C1, I_B1and I_B2, which are the currents that circulate, respectively, in the collector terminal of the first bipolar transistor T_bjt1, in the base terminal of the first bipolar transistor T_bjt1, and in the base terminal of the second bipolar transistor T_bjt2. Said current I_C2functions as current I_PTAT, which is substantially independent of the supply voltage V_DD. In fact, assuming that the first and second bipolar transistors T_bjt1, T_bjt2have respective parameters 13 high, and hence assuming that the currents I_B1and I_B2are negligible as compared to the current I_PTATitself, the current I_PTATis equal to the current that flows in the emitter terminal of the second bipolar transistor T_bjt2. Consequently, we have

$\begin{matrix} I_{PTAT} = \frac{V_{be î¢ž î¢ž 1} - V_{be î¢ž î¢ž 2}}{R_{rA}} = \frac{1}{R_{rA}} Â\cdot \frac{kT}{q} Â\cdot \ln î¢ (\frac{A_{2}}{A_{1}}) & (1) \end{matrix}$

where R_rAis the resistance of the first resistor R_A, V_be1is the voltage present between the base terminal and the emitter terminal of the first bipolar transistor T_bjt1, V_be2is the voltage present between the base terminal and the emitter terminal of the second bipolar transistor T_bjt2, q is the charge of the electron, k is the Boltzmann constant, T is the temperature expressed in Kelvin, and A₁and A₂are, respectively, the areas of the base-emitter junctions of the first and second bipolar transistors T_bjt1, T_bjt2, which are referred to for reasons of brevity also as the areas of the first and second bipolar transistors T_bjt1, T_bjt2, and for which the relation A₂>A₁applies.

A voltage V_be3, i.e., a voltage equal to the base-emitter voltage of the third bipolar transistor T_bjt3, is set up across the second resistor R_B. Said voltage V_be3is imposed on the second resistor R_Bby the feedback loop defined by the third bipolar transistor T_bjt3and by the fifth biasing transistor T₅. In this way, the voltage across the second resistor R_Bis substantially independent of the voltage V_GSpresent between the gate terminals and source terminals of the third and fourth biasing transistors T₃, T₄. Consequently, the voltage across the second resistor R_Bis substantially independent of the supply voltage V_DD. In addition, it may be shown that in the fourth and fifth biasing transistors T₄, T₅there circulates a current that functions as current I_NTAT, which is substantially independent of the supply voltage V_DD. In fact, assuming that the third bipolar transistor T_bjt3has a parameter 13 high, and hence that the current I_B3circulating in the base terminal of the third bipolar transistor T_bjt3is negligible as compared to the current I_NTAT, the current I_NTATis given by the equation

$\begin{matrix} I_{NTAT} = \frac{V_{be î¢ž î¢ž 3}}{R_{rB}} & (2) \end{matrix}$

where R_rBis the value of resistance of the second resistor R_B.

The currents I_PTATand I_NTATare then added up inside the voltage output stage 6 and the current output stage 8, respectively, with the mirror ratios Î³ and Î±, and Î´ and Îµ.

It follows that, on the output resistor R_OUTof the voltage output stage 6, there is a reference voltage V_REF

V_REF=(Î±I_NTAT+Î³I_PTAT)Â·R_rOUTâ€ƒâ€ƒ(3)

where R_rOUTis the resistance of the output resistor R_OUT.

Likewise, by connecting a hypothetical load to the output node N_OUT, the current output stage 8 supplies, on said hypothetical load, a reference current I_REFof

I_REF=ÎµI_NTAT+Î´I_PTATâ€ƒâ€ƒ(4)

As mentioned previously, the temperature coefficients of the currents I_PTATand I_NTATare, respectively, positive and negative, as emerges from Eqs. (1) and (2). In fact, the current I_PTATis directly proportional to the temperature T because the difference V_be1âˆ’V_be2is in turn directly proportional to the temperature T, given that the relation A₂>A₁applies. Instead, the behaviour of the current I_NTATwith respect to the temperature T is determined by the voltage V_be3, which, as is known, varies with the temperature with a coefficient of approximately âˆ’2 mV/Â°K.

It follows that, on the basis of Eqs. (3) and (4), it is possible to determine appropriate values of the mirror ratios Î±, Îµ, Î³, Î´ such that the reference voltage V_REFand the reference current I_REFare, to a first approximation, constant with respect to the temperature T.

In order to enable optimal operation of the voltage and current generator circuit 1, and, in particular, in order to enable the operation described previously, recourse is usually had to a first start-up circuit and a second start-up circuit (which are not shown), connected, respectively, to the first self-biasing circuit 2 and the second self-biasing circuit 4. In particular, the first and second start-up circuits perform the function of biasing the first self-biasing circuit 2 and the second self-biasing circuit 4 in respective points of equilibrium such that Eqs. (1) and (2), and hence also Eqs. (3) and (4), yield non-zero results.

In greater detail, it may be shown that the first and second self-biasing circuits 2, 4 each have a pair of possible points of equilibrium. In particular, the first self-biasing circuit 2 has a respective useful point of equilibrium where the difference V_be1âˆ’V_be2is non-zero, and a respective zero point of equilibrium where the difference V_be1âˆ’V_be2is zero. Likewise, the second self-biasing circuit 4 has a respective useful point of equilibrium where the voltage V_be3is non-zero, and a respective zero point of equilibrium where the voltage V_be3is zero.

Assuming connection of the supply terminal N_DDto the supply voltage V_DDat an instant t₀, and assuming that for t<t₀the voltage and current generator circuit 1 has not been supplied, the first and second self-biasing circuits 2, 4 are biased, in the absence of start-up circuits, in the respective useful point of equilibrium or else in the respective zero point of equilibrium, in a way that is in itself not predictable. The function of the first and second start-up circuits is precisely that of enabling, subsequent to the instant t₀, biasing of the first and second self-biasing circuits 2, 4 in the respective useful points of equilibrium. This done, the first and second start-up circuits turn off, without any longer interfering with operation of the voltage and current generator circuit 1.

Examples of start-up circuits are shown and described in â€œLow power startup circuits for voltage and current reference with zero steady state currentâ€ , International Symposium on Low Power Electronics and Design 2003, Aug. 25-27, Seoul, Korea. However, there is no further description of any start-up circuit herein in so far as the present invention is irrespective of the details of implementation of the start-up circuits themselves.

Thanks to the use described of the currents I_PTATand I_NTAT, the voltage and current generator circuit 1 enables electrical quantities to be obtained that have a high stability in regard to temperature shifts. However, since the voltage and current generator circuit 1 comprises two self-biasing circuits, it entails the use of two start-up circuits and hence is characterized by a high circuit complexity, a considerable current consumption, and a considerable occupation of area. In particular, the latter characteristic is due not only to the presence of the third bipolar transistor T_bjt3but also to the presence of the third and fourth biasing transistors T₃, T₄, which usually have a large area in order to enable better mirroring the current I_NTAT. In addition, the presence of two self-biasing circuits causes the voltage and current generator circuit 1 to be sensitive to the inevitable tolerances introduced by technological processes that enable formation of the first and second self-biasing circuits. Consequently, the performance of the voltage and current generator circuit 1 can be inferior to what may be theoretically expected on account of process asymmetries in the formation of components belonging to different self-biasing circuits, such as, for example, the first and third bipolar transistors T_bjt1, T_bjt3.

SUMMARY OF THE INVENTION

An aim of the present invention is to provide a circuit for generating a reference electrical quantity that will enable at least partial solution of the drawbacks of the known art.

According to at least one embodiment, there is provided a circuit for generating a reference electrical quantity, comprising a first bipolar transistor and a second bipolar transistor, the emitter terminal of the first bipolar transistor being connected to a first line at reference potential, the base terminals of the first and second bipolar transistors being connected to one another and to a common node a first resistor, connected between the emitter terminal of the second bipolar transistor and the first line at reference potential a first mirror circui, connected between a second line at reference potential and the first and second bipolar transistors and configured for receiving a first current which is a function of the current in the first resistor, and generating a first mirrored current a second mirror circuit, configured for receiving a second current and generating a second mirrored current and a first output stage, configured for generating the reference electrical quantity as a function of said first and second mirrored currents, and a second resistor connected between the first line at reference potential and the common node, said second current being a function of the current in the second resistor.

According to another embodiment, the generator circuit further comprises a follower transistor of a MOS type, having a gate terminal connected to the collector terminal of the first bipolar transistor, and a first conduction terminal connected to the common node.

According to another embodiment, said first mirror circuit comprises a first biasing transistor and a second biasing transistor having respective control terminals connected to one another, said first biasing transistor moreover having a first conduction terminal and a second conduction terminal, connected, respectively, to the second line at reference potential and to the collector terminal of said first bipolar transistor, said second biasing transistor moreover having a first conduction terminal and a second conduction terminal, connected, respectively, to the second line at reference potential and to the collector terminal of said second bipolar transistor, said second biasing transistor being diode-connected, the second bipolar transistor being configured so as to supply the first current through its own collector terminal.

According to another embodiment, said second mirror circuit comprises a diode-connected mirror transistor having a first conduction terminal and a second conduction terminal, respectively connected to the second line at reference potential and to a second conduction terminal of the follower transistor, the follower transistor being configured so as to supply the second current through its own second conduction terminal.

According to another embodiment, said first mirror circuit further comprises a first sum transistor having a control terminal and a first conduction terminal and a second conduction terminal, respectively connected to the control terminal of said second biasing transistor, to the second line at reference potential and to an output resistor, and said second mirror circuit further comprises a second sum transistor having a control terminal and a first conduction terminal and a second conduction terminal, respectively connected to the control terminal of said mirror transistor, to the second line at reference potential, and to said output resistor, in such a way that, in use, said first and second mirrored currents flow, respectively, through said first and second sum transistors.

According to another embodiment, said second biasing transistor and said first sum transistor have respective dimensions such as to define a first mirror ratio, and wherein said mirror transistor and said second sum transistor have respective dimensions such as to define a second mirror ratio.

According to another embodiment, said first and second bipolar transistors have, respectively, a first area and a second area, said first and second resistors having, respectively, a first resistance and a second resistance, said first and second resistances, said first and second areas, and said first and second mirror ratios being such as to reduce possible variations of a voltage present on said output resistor due to variations of said first and second currents caused by temperature shifts.

According to another embodiment, said first mirror circuit further comprises a third sum transistor having a control terminal and a first conduction terminal and a second conduction terminal, respectively connected to the control terminal of said second biasing transistor, to the second line at reference potential, and to an output node, and said second mirror circuit further comprises a fourth sum transistor having a control terminal and a first conduction terminal and a second conduction terminal, respectively connected to the control terminal of said mirror transistor, to the second line at reference potential, and to said output node, in such a way that, in use, a third mirrored current and a fourth mirrored current flow, respectively, through said third and fourth sum transistors.

According to another embodiment, said second biasing transistor and said third sum transistor have respective dimensions such as to define a third mirror ratio, and wherein said mirror transistor and said fourth sum transistor have respective dimensions such as to define a fourth mirror ratio.

According to another embodiment, said first and second resistances, said first and second areas, and said third and fourth mirror ratios are such as to reduce possible variations of a current supplied to said output node due to variations of said first and second currents caused by temperature shifts.

According to another embodiment, the generator circuit further comprises at least one from among: a first additional transistor connected in series to said first biasing transistor, a second additional transistor connected in series to said first sum transistor, a third additional transistor connected in series to said second sum transistor, a fourth additional transistor connected in series to said third sum transistor, and a fifth additional transistor connected in series to said fourth sum transistor.

According to another embodiment, said second area is greater than said first area.

According to another embodiment, said first mirror circuit further comprises a third sum transistor having a control terminal and a first conduction terminal and a second conduction terminal, respectively connected to the control terminal of said second biasing transistor, to the second line at reference potential and to an output node, and said second mirror circuit further comprises a fourth sum transistor having a control terminal and a first conduction terminal and a second conduction terminal, connected, respectively, to the control terminal of said mirror transistor, to the second line at reference potential, and to said output node in such a way that, in use, a first mirrored current and a second mirrored current flow, respectively, through said third and fourth sum transistors.

According to another embodiment, there is provided a method for generating a reference electrical quantity, comprising the steps of providing a first bipolar transistor and a second bipolar transistor receiving a first current and generating a first mirrored current, said first current being a function of the current in a first resistor, connected to the emitter terminal of the second bipolar transistor and to a first line at reference potential, the emitter terminal of the first bipolar transistor being connected to the first line at reference potential, the base terminals of the first and second bipolar transistors being connected to one another and to a common node receiving a second current and generating a second mirrored current and generating the reference electrical quantity as a function of said first and second mirrored currents wherein said step of receiving a second current comprises receiving the current in a second resistor connected between the first line at reference potential and the common node.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the invention, embodiments thereof are now described, purely by way of non-limiting example and with reference to the attached drawings, wherein:

FIG. 1 shows a circuit diagram of a circuit for generating a reference current and a reference voltage according to the known art; and

FIGS. 2 and 3 show circuit diagrams of embodiments of the present circuit for generating a reference electrical quantity.

FIG. 2 shows a circuit for generating a reference electrical quantity, designated as a whole by 10, and referred to hereinafter, for reasons of brevity, as the source circuit 10.

DETAILED DESCRIPTION

The source circuit 10 is described in what follows, the present description being limited to the differences alone of the source circuit 10 with respect to the voltage and current generator circuit 1 illustrated in FIG. 1. In addition, components of the source circuit 10 that are already present in the voltage and current generator circuit 1 are designated in the same way, except where otherwise specified.

In detail, the source circuit 10 comprises the first self-biasing circuit, here designated by 12, but does not have the second self-biasing circuit 4. In addition, the source circuit 10 comprises at least one between the voltage output stage 6 and the current output stage 8; in this connection, described by way of example in what follows is one embodiment, present in which are both the voltage output stage 6 and the current output stage 8.

In greater detail, the first self-biasing circuit 12 comprises the first and second resistors R_A, R_B, the first and second biasing transistors T₁, T₂, and the first and second bipolar transistors T_bjt1, T_bjt2. In addition, the first self-biasing circuit 12 comprises a mirror transistor T_mand a follower transistor T_f.

In detail, the second resistor R_Bis connected between ground and the base terminals of the first and second bipolar transistors T_bjt1, T_bjt2, which define a common node N_C.

The mirror transistor T_mis a P-channel MOS transistor. In particular, the source terminal of the mirror transistor T_mis connected to the supply terminal N_DD, whilst the gate terminal defines the node N_NTAT, and hence is connected to the gate terminals of the second and fourth sum transistors T_s2, T_s4. In addition, the mirror transistor T_mis diode-connected; i.e., its drain terminal is connected to its gate terminal.

The follower transistor T_fis an N-channel MOS transistor. In particular, the drain terminal of the follower transistor T_fis connected to the drain terminal (and hence also to the gate terminal) of the mirror transistor T_m. The gate terminal of the follower transistor T_fis connected to the drain terminal of the first biasing transistor T₁, and hence also to the collector terminal of the first bipolar transistor T_bjt1. The source terminal of the follower transistor T_fis instead connected to the common node N_C, and hence to the base terminals of the first and second bipolar transistors T_bjt1, T_bjt2, and to the second resistor R_B.

As regards the resistances R_rA, R_rB, R_rouTof the first and second resistors R_A, R_Band of the output resistor R_OUT, the following relations apply:

R_rB=nÂ·R_A, R_rOUT=mÂ·R_rAâ€ƒâ€ƒ(5)

with n and m not necessarily integers.

Operatively, the current that flows in the follower transistor T_ffunctions as current I_NTAT, which is mirrored by the mirror transistor T_mand by the second and fourth sum transistors T_s2, T_s4. In practice, the mirror transistor T_mfunctions as reading branch of the second current mirror, performing the function that in the voltage and current generator circuit 1 was performed by the fourth biasing transistor T₄.

In addition, the follower transistor T_ffunctions as source follower since the voltage on its own gate terminal follows the voltage on its own source terminal; consequently, in the small-signal regime, the first bipolar transistor T_bjt1is diode-connected. In other words, the follower transistor T_fenables current uncoupling of the base terminals of the first and second bipolar transistors T_bjt1, T_bjt2from the current that flows in the first biasing transistor T₁. Again, in other words, thanks to the presence of the follower transistor T_f, as well as of the first and second biasing transistors T₁, T₂, the currents I_C1and I_C2that flow in the collector terminals of the first and second bipolar transistors T_bjt1T_bjt2are the same, notwithstanding the fact that the second resistor R_Bis connected to the base terminals of the first and second bipolar transistors T_bjt1, T_bjt2themselves. In fact, the current I_NTATthat flows in the follower transistor T_fis equal to the sum of the currents I_RB, I_B1, I_B2that flow in the second resistor R_Band in the base terminals of the first and second bipolar transistors T_bjt1, T_bjt2, respectively.

On the basis of what has been described, it follows that once again Eq. (1) applies, and moreover, assuming that the currents I_B1, I_B2are negligible as compared to the current I_RB, the current I_NTATis equal to the current I_RB.

Consequently, the following equation applies:

$\begin{matrix} I_{NTAT} = \frac{V_{be î¢ž î¢ž 1}}{R_{rB}} = \frac{V_{be î¢ž î¢ž 1}}{n Â\cdot R_{rA}} & (6) \end{matrix}$

In particular, the resistance R_rBcan be sized in such a way that the currents I_B1, I_B2are negligible as compared to the current I_RBalso in the case where the first and second bipolar transistors T_bjt1, T_bjt2have parameters 13 that are not particularly high.

On the basis of Eqs. (1) and (6), we moreover have

$\begin{matrix} \begin{matrix} V_{REF} = î¢ž (Î± î¢ž î¢ž I_{NTAT} + Î³ î¢ž î¢ž I_{PTAT}) Â\cdot R_{rOUT} \\ = î¢ž m Â\cdot (\frac{Î±}{n} Â\cdot V_{be î¢ž î¢ž 1} + Î³ Â\cdot \frac{kT}{q} Â\cdot \ln î¢ (\frac{A_{2}}{A_{1}})) \end{matrix} & (7) \\ \begin{matrix} I_{REF} = î¢ž É› î¢ž î¢ž I_{NTAT} + Î´ î¢ž î¢ž I_{PTAT} \\ = î¢ž \frac{1}{R_{rA}} Â\cdot (\frac{É›}{n} Â\cdot V_{be î¢ž î¢ž 1} + Î´ Â\cdot \frac{kT}{q} Â\cdot \ln î¢ (\frac{A_{2}}{A_{1}})) \end{matrix} & (8) \end{matrix}$

In practice, the reference voltage V_REFand the reference current I_REFdepend upon the temperature T both because the temperature T itself appears explicitly in Eqs. (7) and (8) and because, as is known, the voltage V_be1varies with the temperature with a coefficient of approximately âˆ’2 mV/K. In practice, it is possible to size the source circuit 10 in such a way that the reference voltage V_REFand the reference current I_REFare constant with respect to possible temperature shifts; i.e., they have a zero temperature coefficient. For this purpose, the degrees of freedom represented by the mirror ratios Î±, Îµ, Î³, Î´, as well as by the coefficient n and by the areas A₁and A₂of the first and second bipolar transistors T_bjt1, T_bjt2are available. For example, it is possible to size appropriately the coefficient n, the mirror ratios Î± and Î³, and the areas A₁and A₂of the first and second bipolar transistors T_bjt1, T_bjt2in such a way as to annul the temperature coefficient of the reference voltage V_REF. Next, it is possible to size the mirror ratios Îµ and Î´ appropriately in such a way as to annul the temperature coefficient of the reference current I_REF.

As regards, in particular, the reference voltage V_REF, it does not depend upon the absolute value of resistance of any resistor of the source circuit 10, but rather depends upon the ratios between resistance values; consequently, it does not call for operations of calibration, nor is it affected by possible variations occurring during the technological processes of formation of the source circuit 10. In addition, the reference voltage V_REFcan be established as desired by appropriately choosing the coefficient m irrespective of the choice of the mirror ratios Î±, Îµ, Î³, Î´, of the coefficient n and of the areas A₁, A₂. In particular, the reference voltage V_REFcan assume an arbitrary value comprised between ground and V_DDâˆ’|V_DSx|, where:

âˆ’V_DD>V_be1+|V_DS1|+|V_GSth|, where V_DS1is a (negative) voltage between the drain and source terminals of the first biasing transistor T₁such as to keep in saturation the first biasing transistor T₁, whilst V_GSthis a threshold voltage of the follower transistor T_f; and

âˆ’V_DSXis a (negative) voltage between the drain and source terminals of the first and second sum transistors T_s1, T_s2such as to keep said first and second sum transistors T_s1, T_s2in saturation.

As regards, instead, the reference current I_REF, this depends upon the absolute value of the resistance R_rA, which may depend upon the temperature. However, it is possible to determine the values of the mirror ratios Îµ, Î´ and the value of the coefficient n so as to compensate for the dependence upon the temperature of the resistance R_rA. In addition, to eliminate the dependence of the reference current I_REFupon possible tolerances on the absolute value of the resistance R_rA, and in particular upon a deviation between the nominal value and the effective value of the resistance R_rA, it is possible to determine the values of the mirror ratios Îµ and Î´, and the value of the coefficient n as a function of said tolerances, after prior measurement of the effective value of the resistance R_rA.

It should be moreover noted that, even though the possibility has been described of determining the mirror ratios Î±, Îµ, Î³, Î´ and the coefficient n in such a way that the reference voltage V_REFand the reference current I_REFwill have a zero temperature coefficient, it is likewise possible to determine the mirror ratios Î±, Îµ, Î³, Î´ and the coefficient n in such a way that the reference voltage V_REFand the reference current I_REFhave respective arbitrary temperature coefficients. In other words, it is possible to size the source circuit 10 in such a way that the reference voltage V_REFand the reference current I_REFhave a desired dependence upon temperature.

Purely by way of example, it is possible to assume A₂/A₁=2, n=m=1, R_rA=10 kÎ©, Î±=Îµ=1, Î³=Î´=33.4.

As illustrated in FIG. 3, it is moreover possible to insert one or more additional transistors. Said additional transistors can be of a P-channel MOS type and have the respective gate terminals connected to an additional N+ terminal, which is in turn biased at a cascode voltage V+ by means of an appropriate additional biasing circuit (not shown).

For example, it is possible to insert a first additional transistor T₁₊ between the first biasing transistor T₁and the first bipolar transistor T_bjt1. Said first additional transistor has its source and drain terminals connected, respectively, to the drain terminal of the first biasing transistor T₁and to the collector terminal of the first bipolar transistor T_bjt1.

The presence of the first additional transistor T₁₊ enables optimization of the performance of the first current mirror, and hence of the first and second biasing transistors T₁, T₂. In fact, designating by V_DS2the voltage between the drain and source terminals of the second biasing transistor T₂, in a way in itself known it is possible to design the additional biasing circuit in such a way that the cascode voltage V+ is a function of the supply voltage V_DD. In particular, the cascode voltage V+ can be a function of the supply voltage V_DDaccording to a law such that the voltages V_DS1, V_DS2are the same, or at least have an equal dependence upon the supply voltage V_DD. In this way, the first current mirror is of a cascode type and hence has improved behavior with respect to variations in the supply voltage V_DD.

In a similar way, a second additional transistor T₂₊ and a third additional transistor T₃₊ can be inserted between the output resistor R_OUTand, respectively, the first and second sum transistors T_s1, T_s2. Again, a fourth additional transistor T₄₊ and a fifth additional transistor T₅₊ can be inserted between the output node N_OUTand, respectively, the third and fourth sum transistors T_s3, T_s4. In practice, the second, third, fourth, and fifth additional transistors T₂₊-T₅₊ are arranged in series with the first, second, third, and fourth sum transistors T_s1-T_s4, respectively.

The advantages that the source circuit 10 affords emerge clearly from the foregoing discussion. In particular, the source circuit 10 enables the reference voltage V_REFand/or the reference current I_REFto be obtained by using just one self-biasing circuit, with evident advantages in terms of reduction of current consumption, reduction of circuit complexity, and higher integrability. The latter advantage is due to the reduction of the area occupied, obtained precisely by means of elimination of the second self-biasing circuit 4. In addition, the presence of just one self-biasing circuit involves the use of just one start-up circuit. In this connection, the source circuit 10 can be connected to a start-up circuit of a known type.

As further advantage, the reference voltage V_REFsupplied by the source circuit 10 does not depend upon the absolute value of resistance of any resistor of the source circuit 10, and can moreover be established as desired by an appropriate choice of the coefficient m, irrespective of the choice of the mirror ratios Î±, Îµ, Î³, Î´ and of the coefficient n.

Finally, it is evident that modifications and variations may be made to the source circuit 10 described and illustrated herein, without thereby departing from the sphere of protection of the present invention, as defined in the annexed claims.

For example, instead of the output resistor R_OUTit is possible to use a resistive divider, i.e., a plurality of resistors connected in series, in order to generate a plurality of different reference voltages.

In addition, instead of the first and second biasing transistors T₁, T₂, and of the first and third sum transistors T_s1, T_s3, it is possible to use different circuits, provided that they enable mirroring of the current I_PTAT. Likewise, instead of the mirror transistor T_mand the second and fourth sum transistors T_s2, T_s4, it is possible to use different circuits, provided that they enable mirroring of the current I_NTAT.

Finally, the first and second biasing transistors T₁, T₂, as well as the first, second, third, and fourth sum transistors T_s1-T_s4can be of a type different from what has been described and illustrated.

Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.