BACKGROUND

1. Technical Field

The present disclosure relates to a fully differential demodulator with variable gain and to a method for demodulating a signal.

2. Description of the Related Art

As is known, demodulators find an extremely wide range of applications in numerous sectors of electronics and telecommunications. Just to provide an example, in addition to the well-known uses for transmission and reception of electromagnetic signals, demodulators are used in read chains of microelectromechanical gyroscopes. In these devices, a first movable mass is set in oscillation along an axis at a pre-determined frequency and draws in the oscillatory motion a second mass, which is constrained to the first mass so as to have one relative degree of freedom. When the gyroscope undergoes a rotation about a given axis at an angular velocity, the second mass is subjected to a Coriolis force as a result of the drawing action and moves according to the relative degree of freedom. The displacement of the second mass can be detected and transduced into electrical signals amplitude-modulated in a way proportional to the angular velocity, with a carrier at the oscillation frequency of the first mass. The use of a demodulator enables the modulating signal to be obtained and hence tracing back to the instantaneous angular velocity.

Known demodulators perform a multiplication between the modulated signal and the carrier signal in order to bring the modulating signal back into baseband. They are rather complex devices that require the use of various operational amplifiers, filters and sophisticated synchronization circuits. In particular, discrete-time analog demodulators are frequently particularly complex because driving thereof requires a large number of timing signals appropriately synchronized with the carrier frequency. Consequently, not only is design difficult, but also the practical implementation can pose serious problems. For this reason, currently available demodulators, especially discrete-time analog demodulators, are not suitable for use in applications that, like microelectromechanical gyroscopes, call for extremely low levels of consumption and small overall dimensions.

BRIEF SUMMARY

The present disclosure provides a demodulator and a method of demodulation that overcome the drawbacks outlined above.

According to the present disclosure, a demodulator and a method for demodulating a signal are provided.

In accordance with the present disclosure, a demodulator for an amplitude-modulated input signal defined by a carrier signal having a carrier frequency modulated by a modulating signal is provided. The demodulator includes an amplifier stage having a gain and structured to receive the amplitude-modulated input signal; and a gain-control stage coupled to the amplifier stage and configured to vary the gain of the amplifier stage according to the carrier frequency of the carrier signal.

In accordance with another aspect of the present disclosure, the gain control stage is coupled to at least one controllable capacitive network for modifying a variable capacitance with a periodic signal equal to the carrier frequency.

In accordance with the present disclosure, a method for demodulating a signal is provided, the method including receiving an amplitude-modulated input signal, defined by a carrier signal at a carrier frequency and a modulating signal; and amplifying the input signal with a gain that is varied according to the carrier frequency of the carrier signal.

In accordance with the present disclosure, a circuit is provided that includes a variable gain amplifier stage adapted to receive an amplitude modulated signal and to generate an output signal having a gain; and a gain control stage coupled to the variable gain amplifier stage, the gain control stage adapted to receive as input a carrier signal of the amplitude modulated signal and to generate a gain control signal to control the gain of the variable gain amplifier stage in response to a frequency of the carrier signal and to bring the amplitude modulated signal into a baseband in the output signal.

In accordance with the present disclosure, a gyroscopic apparatus is provided that includes a gyroscope device generating a modulated signal, the gyroscope device comprising two microstructure movable masses and a read interface, the modulated signal comprising a discrete-time analog voltage given by a product of a modulating signal and a carrier signal having a carrier frequency, the carrier frequency comprising a mechanical resonance frequency of the two movable masses and an amplitude modulation that is proportional to an angular velocity of the gyroscope device; and a demodulator of the discrete-time analog type, the demodulator comprising: a variable gain amplifier stage adapted to receive an amplitude modulated signal and to generate an output signal having a gain; and a gain control stage coupled to the variable gain amplifier stage, the gain control stage adapted to receive as input a carrier signal of the amplitude modulated signal and to generate a gain control signal to control the gain of the variable gain amplifier stage in response to a frequency of the carrier signal and to bring the amplitude modulated signal into a baseband in the output signal.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

For a better understanding of the disclosure, some embodiments thereof are now described, purely by way of a non-limiting example and with reference to the attached drawings, wherein:

FIG. 1 is a simplified block diagram of an electronic apparatus incorporating a demodulator according to a first embodiment of the present disclosure;

FIG. 2 shows graphs that illustrate quantities regarding the demodulator of FIG. 1;

FIG. 3 is a simplified circuit diagram of the demodulator of FIG. 1;

FIGS. 4a and 4b show a first portion of the demodulator of FIG. 1 in respective different operating configurations;

FIGS. 5a and 5b show a second portion of the demodulator of FIG. 1 in respective different operating configurations;

FIG. 6 shows graphs that illustrate quantities regarding the demodulator of FIG. 1;

FIG. 7 is a more detailed circuit diagram of the demodulator of FIG. 1;

FIG. 8 is a simplified circuit diagram of a demodulator according to a second embodiment of the present disclosure; and

FIG. 9 shows graphs that illustrate quantities regarding the demodulator of FIG. 8.

DETAILED DESCRIPTION

FIG. 1 is a schematic illustration of an electronic apparatus 1 comprising a device 2, which generates a modulated signal S_M, and a demodulator 3 coupled to the device 2 for demodulating the modulated signal S_Mand generating a corresponding output signal S_Oin baseband. The modulated signal S_Mis given by the product of a modulating signal S_Mâ€² (not illustrated) and a carrier signal S_CRhaving a carrier frequency f_CR:

S_M=S_Mâ€²S_CR=S_Mâ€² sin 2Ï€f_CRtâ€ƒâ€ƒ(1)

In one embodiment, in which the electronic apparatus 1 is a microelectromechanical gyroscope, the device 2 is a microstructure, in itself known and not shown in detail, having two movable masses (one for driving and one for detection) and provided with a read interface. The modulated signal S_Mdetected by the read interface is in this case a discrete-time analog voltage. The carrier frequency is a mechanical resonance frequency of the microstructure, and the amplitude modulation is proportional to an angular velocity of the gyroscope.

The demodulator 3 is of a discrete-time analog type and is based upon the use of switched-capacitor circuits. Signal inputs 3a, 3b of the demodulator 3 are connected to outputs of the device 2 for receiving the modulated signal S_M. A further output of the device 2 supplies the carrier signal S_CRto a demodulation input 3c of the demodulator 3. The output signal S_Ois supplied on outputs 3d, 3e of the demodulator 3.

The demodulator 3 has a variable-gain amplifier stage 4 and a control stage 5 for controlling the gain G of the amplifier stage 4.

In the embodiment of the disclosure described herein, the amplifier stage 4 is of a fully differential switched-capacitor type. Inputs of the amplifier stage 4 are coupled to the signal inputs 3a, 3b for receiving the modulated signal S_M.

The control stage 5 receives from the device 2 the carrier signal S_CRand uses it for varying the gain G of the amplifier stage 4 according to a zero-mean discrete sinusoid, at the carrier frequency f_CRand synchronous with the carrier signal S_CRitself, as shown in FIG. 2.

The gain G is used as a demodulating quantity. The output signal S_O, in fact, is proportional both to the modulated signal S_Mand to the gain G of the amplifier stage 4, which, by the action of the control stage 5, is a sinusoid at the carrier frequency f_CR. In practice, the processing of the modulated signal S_Mperformed by the demodulator 3 is equivalent to a multiplication by the carrier signal S_CR, and hence the resulting signal, i.e., the output signal S_O, is brought back into baseband.

FIG. 3 illustrates in greater detail the demodulator 3. The amplifier stage 4 comprises an operational amplifier 6, with negative feedback obtained by two capacitive-type feedback networks 7, and controllable capacitive input networks 10. Each feedback network 7 is connected between a respective input and a respective output of the operational amplifier 6, between which an inverting action is exerted. Both of the feedback networks 7 have a feedback capacitance C_FB. The operational amplifier 6 moreover uses a common-mode line 8, supplying a common-mode voltage V_CM. A reset switch 9 is set between the inputs of the operational amplifier 6.

The controllable capacitive networks 10 are connected each between a respective signal input 3a, 3b of the demodulator 3 and a respective input of the operational amplifier 6. In addition, the controllable capacitive networks 10 have an equal variable capacitance C_V, which can assume in sequence a plurality of discrete values, as explained in greater detail hereinafter, and are controlled by the synchronization device 13 through of a plurality of timing signals B₀-B_N. The modulus of the gain G of the operational amplifier 6 is equal to C_V/C_FB.

The control stage 5 comprises a zero circuit 11, a sign-inverting circuit 12 and a synchronization device 13.

The zero circuit 11 and the sign-inverting circuit 12 are cascaded between the operational amplifier 6 and the outputs 3d, 3e of the demodulator 3. Both are controlled by the synchronization device 13, respectively, through a zero signal Z and a sign-inversion signal SGN, and have two respective operating configurations. In particular, in a first operating configuration (FIG. 4a) the inputs of the zero circuit 11 are directly connected to respective outputs in such a way that incoming signals can transit unaltered. In a second operating configuration (FIG. 4b), the outputs are decoupled from the inputs and are connected to the common-mode line 8. In this way, a zero signal is supplied at output, irrespective of the signal present at input. As shown in FIG. 5a, the sign-inverting circuit 12 has a first input 12a, a second input 12b, a first output 12c, and a second output 12d. In the first operating configuration of the sign-inverting circuit 12, the first input 12a and the second input 12b are connected to the first output 12c and to the second output 12d, respectively. The incoming signals can thus pass without being modified. In the second operating configuration (FIG. 5b), instead, the first input 12a and the second input 12b are connected to the second output 12d and to the first output 12c, respectively. In practice, the connections between the inputs and the outputs of the sign-inverting circuit 12 are inverted, and consequently the output signals have the same amplitude, but opposite sign with respect to the incoming signals.

The synchronization device 13 comprises a comparator 15, a delay block 17, and a timing signal generator 18.

The comparator 15 receives at input the carrier signal S_CRand generates at output a binary timing signal CK, which switches at each half-period of the carrier signal S_CR(in practice, at instants of zero-crossing thereof, FIG. 6). The timing signal CK is hence synchronous with the carrier signal S_CR, and its period T_CKis equal to 1/f_CR.

The delay block 17 receives the timing signal CK and generates a delayed timing signal CK₉₀, 90Â° out of phase, which is used to obtain possible quadrature components superimposed on the modulated signal S_M.

The timing signal generator 18, for example a logic unit, receives the timing signal CK and the delayed timing signal CK₉₀and generates the timing signals B₀-B_Nso as to modify the gain G of the amplifier stage 4 an integer number M of times for each period T_CK, synchronously with the timing signal CK (i.e., M control cycles of the gain G are carried out for each period T_CKof the timing signal CK, FIGS. 2 and 6; the control cycles of the gain G hence have a period equal to T_CK/M). In addition, the timing signal generator 18 supplies the zero signal Z, the sign-inversion signal SGN, a reset signal RES, and a sampling-control signal CDS, which are respectively supplied to the zero circuit 11, to the sign-inverting circuit 12, to the reset switch 9, and to the feedback networks 7. The timing signals B₀-B_Nand the zero signal Z are generated by the timing signal generator 18 using an internal counter (known and not shown herein), whereas switching of the sign-inversion signal SGN is caused directly by the variations of the timing signal CK.

During operation of the demodulator 3, the timing signals B₀-B_Nare applied to the controllable capacitive networks 10 for selecting, at each control cycle of the gain G, values of the variable capacitance C_Vaccording to a sinusoid of frequency equal to the carrier frequency f_CR. The values of the variable capacitance C_Vselected in each control cycle of the gain G are given by:

C_V(J)=C_FBsin(2Ï€t_J/T_CK)â€ƒâ€ƒ(2)

where t_Jis the initial instant of the generic J-th control cycle of the gain G (see also FIG. 2). The zero circuit 11 is normally in the first operating configuration (FIG. 4a) and is brought into the second operating configuration (FIG. 4b) by the zero signal Z for the duration of one control cycle of the gain G at each half-period of the timing signal CK. In these conditions, the zero circuit 11 prevents the transmission of signals and sets the gain G to zero. As a result of the sign-inversion signal SGN, moreover, the sign-inverting circuit 12 switches between its first and second operating configurations (FIGS. 5a and 5b, respectively) at each half-period of the timing signal CK, in effect changing the sign of the gain G. Consequently, in the generic J-th control cycle of the gain G, the gain G is given by

G(J)=C_V(J)/C_FB=sin(2Ï€t_J/T_CK)=sin(2Ï€f_CRt_J)â€ƒâ€ƒ(3)

since the timing signal CK is synchronous with the carrier signal S_CR(T_CK=1/f_CR).

The output signal S_Ois the product of the gain G of the amplifier stage 4 and the modulated signal S_M

S_O=S_MG(J_J)=S_Mâ€²S_CRG(J)=S_Mâ€² sin²(2Ï€f_CRt_J)â€ƒâ€ƒ(4)

As previously mentioned, then, the gain G is used as demodulating quantity for the modulated signal S_M, which already contains the carrier signal S_CR, and the output signal S_Ois brought back into the baseband.

A detailed diagram of the demodulator 3 is illustrated in FIG. 7.

The controllable capacitive networks 10 each comprise a plurality of respective control capacitors 20, which can be selectively connected between the signal inputs 3a, 3b of the demodulator 3 and the inputs of the operational amplifier 6. Each control capacitor 20 is provided with two enable switches 21, simultaneously controlled by a respective timing signal B₀-B_Nand arranged one upstream and one downstream of the control capacitor 20 itself. In addition, the terminals of each control capacitor 20 are selectively connectable to the common-mode line 8 through two wait switches 22, which are controlled in phase opposition with respect to the enable switches 21 by corresponding inverted timing signals B_0N-B_NN.

The inverted timing signals B_0N-B_NNcan be supplied directly by the generator of timing signals 18, or else can be derived from the corresponding timing signals B₀-B_Nusing conventional logic inverters (not shown herein). In the embodiment described herein, the control capacitors 20 have respective capacitances C₀-C_Ndefined by Eq. (2), where J=0, 1, . . . , N, and the timing signals B₀-B_Nare configured to select in sequence a single control capacitor 20 for each control cycle of the gain G of the amplifier stage 4.

With reference also to FIG. 6, after the zero signal Z has brought the zero circuit 11 into its first operating configuration (FIG. 4a), the control capacitor 20 having lowest capacitance C₀is inserted, while all the others are connected with both terminals to the common-mode line 8. In the subsequent control cycles of the gain G, control capacitors 20 with always increasing capacitance C_Jare inserted selectively and in sequence, until the carrier signal S_CRreaches the peak value and the control capacitor 20 of maximum capacitance C_Nis inserted (first quarter of period). Then, the control capacitors 20 are again inserted in reverse order (i.e., in decreasing order of capacitance) until the carrier signal S_CRis set to zero. In this way, in practice, each control capacitor 20 is used four times for each cycle of the timing signal CK (the control capacitor 20 with maximum capacitance C_Nis used twice).

With reference once again to FIG. 7, the zero circuit 11 comprises two enable switches 24, each connected between a respective input and a respective output and controlled simultaneously by means of a negated zero signal ZN. In addition, the outputs of the zero circuit 11 are selectively connectable to the common-mode line 8 through respective zero switches 25, controlled simultaneously by the zero signal Z. In the first operating configuration, the enable switches 24 are closed, in such a way that the inputs and the respective outputs of the zero circuit 11 are connected directly. The zero switches 25 are instead open. Instead, in the second operating configuration, the enable switches 24 are open, and the zero switches 25 are closed. The signal supplied by the zero circuit 11 is hence zero, given that both of its outputs are at the common-mode voltage V_CM.

The sign-inverting circuit 12 comprises two forward-connection switches 27 and two reverse-connection switches 28, respectively controlled by the sign-inversion signal SGN and by a negated sign-inversion signal SGNN. The forward-connection switches 27 are connected one between the first input 12a and the first output 12c and the other between the second input 12b and the second output 12d of the sign-inverting circuit 12 (in the embodiment described herein, the outputs 12c, 12d of the sign-inverting circuit 12 coincide with the outputs 3d, 3e of the demodulator 3). The reverse-connection switches 28 are, instead, connected one between the first input 12a and the second output 12d and the other between the second input 12b and the first output 12c of the sign-inverting circuit 12. In practice, the forward-connection switches 27 and the reverse-connection switches 28 are controlled in phase opposition for inverting the connections between the inputs 12a, 12b and the outputs 12c, 12d of the sign-inverting circuit 12 during passage from the first to the second operating configuration (illustrated in FIGS. 5a and 5b).

Each of the feedback networks 7 comprises a feedback capacitor 30, having the feedback capacitance C_FB. First terminals of the feedback capacitors 30 are connected to respective inputs of the operational amplifier 6. First offset-sampling switches 31 and feedback switches 32, controlled in phase opposition through the sampling-control signal CDS and, respectively, a negated sampling-control signal CDSN, enable connection of second terminals of the feedback capacitors 30 alternately to the common-mode line 8 and to respective outputs of the operational amplifier 6. Each feedback network 7 further comprises a second offset-sampling switch 33, connected between the respective input and the respective output of the operational amplifier 6. The second offset-sampling switches are controlled by the sampling-control signal CDS.

The reset switch 9 fixes the terminals of the operational amplifier 6 to the common-mode voltage, in such a way that the operational amplifier 6 itself will work in the linear area. The first and second offset-sampling switches 31, 33 and the feedback switches 32 are controlled so as to implement the correlated double sampling (CDS) technique at each interval of control of the gain G of the amplifier stage 4. In order to balance all the nodes of the operational amplifier 6 to the common-mode voltage V_CM, in a first step, the reset switch 9 and the first and second offset-sampling switches 31, 33 are closed, while the feedback switches 32 are open. Next, the reset switch 9 is opened, so that only the signal contribution due to offset of the operational amplifier 6 and to flicker noise is stored in the feedback capacitors 30. Finally, the first and second offset-sampling switches 31, 33 are opened, and, after a brief decoupling interval, the feedback switches 32 are closed to enable amplification of the entire signal supplied to the operational amplifier 6. However, the contribution of the offset and of the flicker noise, previously stored in the feedback capacitors 30, is now subtracted, and hence only the useful signal is supplied on the outputs of the operational amplifier 6.

The disclosed circuit advantageously enables demodulators of a simple structure, with reduced occupation of area, and with low levels of consumption to be obtained. The demodulator according to the disclosure requires, in fact, just one operational amplifier and, since the demodulation is obtained by varying the gain of the amplification stage, no further circuits such as multipliers are necessary. In addition, the control capacitors can be used four times for each cycle of the carrier signal S_CRand of the timing signal CK. Consequently, M/4 control capacitors and (M/4)+3 timing signals are sufficient for demodulation. The overall dimensions due to the control capacitors is hence contained, and also the synchronization and driving operations can be performed in a simple way. The demodulator according to the disclosure is particularly suitable for being implemented by means of (discrete-time analog) switched-capacitor circuits.

A second embodiment is illustrated in FIG. 8, where parts that are the same as those already shown are designated by the same reference numbers.

In this case, a demodulator 103 comprises the amplifier stage 4, with the operational amplifier 8, the feedback networks 7 and controllable capacitive networks 110, and a control stage 105, which includes the zero circuit 11, the sign-inverting circuit 12, and the synchronization device 13. In this case, the sign-inverting circuit 12 is set between the inputs 103a, 103b of the demodulator 103 and the controllable capacitive networks 110, albeit having the same structure and operating in the same way already described with reference in particular to FIGS. 3, 5a, 5b and 7.

The controllable capacitive networks 110 are each connected between a respective output of the sign-inverting circuit 12 and a respective input of the operational amplifier 6 and are controlled by the synchronization device 13 in such a way that their variable capacitance C_Vâ€² assumes a plurality of values according to a zero-mean discrete sinusoid and to the carrier frequency f_CR, as indicated by Eq. (2).

The controllable capacitive networks 110 each comprise a plurality of respective control capacitors 120, selectively connectable between the sign-inverting circuit 12 and respective inputs of the operational amplifier 6. Each control capacitor 120 is equipped with two enable switches 121, controlled simultaneously by a respective timing signal B₀â€²-B_Pâ€² and set one upstream and one downstream of the control capacitor 20 itself. In addition, the terminals of each control capacitor 120 are selectively connectable to the common-mode line 8 through two wait switches 122, which are controlled in phase opposition with respect to the enable switches 121 by means of corresponding negated timing signals B_0Nâ€²-B_PNâ€². In the embodiment described here, in particular, the timing signals B₀â€²-B_Pâ€² and the negated timing signals B_0Nâ€²-B_PNâ€² are configured so as to select, in different cycles of control of the gain G, just one control capacitor 120 or else a number of control capacitors 120 in parallel in each controllable capacitive network 110. In this way, it is possible to reduce both the number of control capacitors 120 necessary and their capacitances, which can be added together. There is thus a further reduction also in the overall dimensions. Purely by way of example, a possible timing diagram of the controllable capacitive networks 110 is given in FIG. 9, in the case where four control capacitors 120 and as many timing signals B₀â€²-B_Pâ€² (P=3) are present.

Finally, it is clearly evident that modifications and variations may be made to the demodulator and to the method of demodulation described herein, without thereby departing from the scope of the present disclosure, as defined in the annexed claims. In particular, the demodulator could be of a continuous-time analog type.

The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet, are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.

These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.