BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a random data generator, and more particularly, to a digital frequency jittering circuit that utilizes the random data generator for varying a switching frequency of a power supply, and a related method thereof.

2. Description of the Prior Art

A primary problem that plagues a conventional switching power supply is the electromagnetic interference (EMI) effect. It is well known that the EMI generated by the switching power supply can cause problems for communications devices in the vicinity of the power supply. Additionally, the high frequency signal of EMI will be coupled to a component of the AC mains signal that will be provided to other devices. Furthermore, the radiated EMI by the power supply can interfere with wireless radio and wireless television transmissions that are carried by other entities. It is well known that to reduce the negative effects of the electromagnetic interference (EMI) of a switching power supply one can scatter the power of a predetermined frequency by utilizing a prior art frequency jittering means. The effect of the scattered power depends upon the range that the predetermined frequency to be scattered within an operating frequency range. For instance, a wider irregular range of the predetermined frequency to be scattered within the operating frequency range results in a smaller EMI being generated in the switching power supply. In other words, when the power is distributed over the wider frequency range, the EMI effect is alleviated. Therefore, generating the irregular scattered range of the predetermined frequency within the operating frequency range is a critical factor in lowering the effect of the EMI of the switching power supply.

Please refer to FIG. 1. FIG. 1 illustrates a prior art frequency jittering generator 10. The frequency jittering generator 10 utilizes a state transition logic circuit 12 to generate a pseudo random value. Thepseudo random value is then transmitted to an output logic circuit 14 to generate an output signal, and the output signal is then sampled by a sampling unit 16 that is controlled by a clock signal. An output logic circuit 14 will generate a group of binary output signals for being converting into an oscillating signal with a frequency that corresponds to the group of binary output signals by utilizing a digital to frequency converter 18. Because state transition logic circuit 12 is derived from a predetermined rational equation, and the predetermined rational equation will generate a sequential output as the random value, the oscillating signal that is obtained from the sampled binary output signal is a regulated sequential jittering signal in a long term. Accordingly, the frequency jittering generator 10 does not effectively overcome the EMI effect of the switching power supply.

It is apparent that new and improves methods and devices are needed to solve the above-mentioned problems.

SUMMARY OF THE INVENTION

An objective of the present invention is therefore to provide a digital frequency jittering circuit that utilizes a random data generator for varying a switching frequency of a power supply, and a related method thereof.

According to an embodiment of the present invention, a random data generator is disclosed. The random data generator includes an oscillator, a delay module, and a phase error detecting module. The oscillator is for generating an oscillating signal. The delay module, coupled to the oscillator, is for delaying the oscillating signal by a first delay amount to generate a first delayed signal and delaying the oscillating signal by a second delay amount to generate a second delayed signal, wherein the first delay amount is not equal to the second delay amount. The phase error detecting module, coupled to the delay module, is for detecting an phase error between the first and the second delayed signals to generate a random data.

According to an embodiment of the present invention, a digital frequency jittering circuit is disclosed. The digital frequency jittering circuit includes a random data generator for varying a switching frequency of a power supply. The digital frequency jittering circuit includes a random data generator, an analog to digital functional module, and a digital to analog functional module. The random data generator includes an oscillator. The oscillator generates an oscillating signal having the switching frequency. A delay module, coupled to the oscillator, is for delaying the oscillating signal by a first delay amount to generate a first delayed signal and delaying the oscillating signal by a second delay amount to generate a second delayed signal, wherein the first delay amount is not equal to the second delay amount. A phase error detecting module, coupled to the delay module, is for detecting an phase error between the first and the second delayed signals to generate a random data. The analog to digital functional module, coupled to the random data generator, is for converting the random data into a digital random value. The digital to analog functional module, coupled to the oscillator and the analog to digital functional module, is for varying the switching frequency of the oscillating signal according to the digital random value.

According to an embodiment of the present invention, a random data generating method is disclosed. The method includes generating an oscillating signal; delaying the oscillating signal by a first delay amount to generate a first delayed signal and delaying the oscillating signal by a second delay amount to generate a second delayed signal, wherein the first delay amount is not equal to the second delay amount; and detecting an phase error between the first and the second delayed signals to generate a random data.

According to an embodiment of the present invention, a method for varying a switching frequency of a power supply is disclosed. The method includes generating an oscillating signal; delaying the oscillating signal by a first delay amount to generate a first delayed signal and delaying the oscillating signal by a second delay amount to generate a second delayed signal, wherein the first delay amount is not equal to the second delay amount; detecting an phase error between the first and the second delayed signals to generate a random data; converting the random data into a digital random value; and varying the switching frequency of the oscillating signal according to the digital random value.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating a prior art frequency jittering generator.

FIG. 2 is a diagram illustrating a digital frequency jittering circuit for varying a switching frequency with random generator of a power supply according to an embodiment of the present invention.

FIG. 3 is a timing diagram of the oscillating signal, the first delayed signal, the second delayed signal, and the random data shown in FIG. 2.

FIG. 4 is a frequency domain diagram illustrating the shift cycling operating of the digital frequency jittering circuit of FIG. 2.

FIG. 5 is a flow chart illustrating a method for varying a switching frequency of a power supply according to the digital frequency jittering circuit shown in FIG. 1.

DETAILED DESCRIPTION

Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, consumer electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms â€œincludingâ€ and â€œcomprisingâ€ are used in an open-ended fashion, and thus should be interpreted to mean â€œincluding, but not limited to . . . â€ The terms â€œcoupleâ€ and â€œcouplesâ€ are intended to mean either an indirect or a direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

Please refer to FIG. 2. FIG. 2 illustrates a diagram of a digital frequency jittering circuit 100 for varying a switching frequency f_oscof a power supply (i.e., a switching power) according to an embodiment of the present invention. The digital frequency jittering circuit 100 comprises a random data generator 102, an analog to digital functional module 104, and a digital to analog functional module 106. In which random data generator 102 comprises an oscillator 1022 for generating an oscillating signal S_outhaving the switching frequency f_osc; a delay module 1024, coupled to oscillator 1022, for delaying oscillating signal S_outby a first delay amount Î”t₁to generate a first delayed signal S_d1and delaying oscillating signal S_outby a second delay amount Î”t₂to generate a second delayed signal S_d2, wherein the first delay amount Î”t₁is not equal to the second delay amount Î”t₁; and a phase error detecting module 1026, coupled to delay module 1024, for detecting an phase error Î”Ï† between the first and the second delayed signals S_d1, S_d2to generate a random data S_r. Furthermore, analog to digital functional module 104, coupled to random data generator 102, is for converting random data S_rinto a digital random value S_p. Digital to analog functional module 106, coupled to oscillator 1022 and analog to digital functional module 104, is for varying switching frequency f_oscof oscillating signal S_outaccording to digital random value S_p.

In random data generator 102, oscillator 1022 is implemented by a ring oscillator. Please note that, the oscillator can be any type of controllable oscillating circuit. The delay module 1024 comprises a first delay circuit 1027 (e.g., a delay chain) for delaying the oscillating signal S_outwith the first delay amount Î”t₁equal to 540 degrees, and a second delay circuit 1028 (e.g., an inverter) delays oscillating signal S_outwith the second delay amount Î”t₂equal to 180 degrees. Please note that, the first delay amount Î”t₁is not limited to 540 and can be any degree that capable to extract the jitter between two consequential clocks of the oscillating signal S_out, such as 180+360*N, wherein N=0, 1, 2 . . . . The phase error detecting module 1026 comprises an exclusive OR (XOR) gate to perform an XOR operation upon the first and the second delayed signals S_d1, S_d2to generate the random data S_r. It should be noted that the present invention is not limited to the above disclosed configuration. For example, the delay module 1024 can adopt other circuit components to provide different delay amounts. These and other examples all fall within the scope of the present invention.

The analog to digital functional module 104 comprises a phase-error power accumulator 1042, which is for accumulating the power of the random data to generate an output voltage V_c; in which phase-error power accumulator 1042 comprises a capacitor C_c, a resistor R, a first switch S₁and a second switch S₂. The first switch S₁is coupled to a first predetermined voltage V_ddand capacitor C_c, for selectively allowing the first predetermined voltage V_ddto charge capacitor C_caccording to random data S_r; while the second switch S₂is coupled to capacitor C_cand a second first predetermined voltage V_gnd1, for selectively allowing capacitor C_cto discharge through the second predetermined voltage V_gnd1according to a first reset signal S_k1. The analog to digital functional module 104 also comprises a comparator 1044 coupled to phase-error power accumulator 1042 and a reference voltage V_gnd2, for comparing output voltage V_cwith reference voltage V_gnd2and generating a latch signal V_pwhen output voltage V_cexceeds reference voltage V_gnd2; and a counter 1046, coupled to comparator 1044, for calculating a counter value N and outputting counter value N as digital random value S_pto digital to analog functional module 106 when receiving latch signal V_p, where when the digital to analog functional module 106 completes varying switching frequency f_oscof oscillating signal S_oututilizing digital random value S_p, digital to analog functional module 106 outputs a second reset signal S_k2to counter 1046 to reset counter value N to an initial value N_min.

The digital to analog functional module 106 comprises a control circuit 1062, coupled to counter 1046, for sequentially outputting a plurality of control values X₁-X_naccording to digital random value S_p; and a digital to analog converter 1064, coupled to control circuit 1062 and oscillator 1022, for converting the control values X₁-X_ninto a plurality of control voltages (V_c1-V_c3) respectively to control the oscillator 1022 to vary switching frequency f_oscof oscillating signal S_out.

According to the embodiment of the present invention, for simplicity, the control voltages (V_c1-V_c3) of oscillator 1022 are fixed at the beginning, thus, ideally, switching frequency f_osc(i.e., period T) of oscillating signal S_outis also fixed. However, periods T₁, T₂, T₃, . . . of switching frequency f_oscof oscillating signal S_outare slightly different because of the inherently jitter within oscillating signal S_out. Please refer to FIG. 3. FIG. 3 illustrates a timing diagram of the oscillating signal S_out, the first delayed signal S_d1, the second delayed signal S_d2, and random data S_r. Therefore, after oscillating signal S_outpasses through the first delay circuit 1027 and the second delay circuit 1028 with delay amounts Î”t₁=3T(540 degrees) and Î”t₂=T(180 degrees) respectively, the jittering within oscillating signal S_outwill generate a slight overlap at time t_a, t_b, t_c, t_dof the first delayed signal S_d1and the second delayed signal S_d2. Accordingly, when the first delayed signal S_d1and the second delayed signal S_d2are inputted to the phase error detecting module 1026 (exclusive OR (XOR) gate), random data S_r(pulses) will be generated at the time t_a, t_b, t_c, t_das shown in FIG. 3. Furthermore, each pulse width of the pulses of random data S_ris dependent on the phase error at time t_a, t_b, t_c, t_d, that is, Î”Î¦_a, Î”Î¦_b, Î”Î¦_cand Î”Î¦_d.

Then, the pulses of random data S_rWill turn on the first switch S₁to charge capacitor C_cat the time intervals of each pulse width. Thus, the larger the time intervals of the pulse width, the longer the charging time to the capacitor C_c. Please note that, because the jitter within oscillating signal S_outis an unpredictable effect, therefore the pulse width of each pulse of random data S_rcan be regarded as a random value that will consequently cause the charged energy (output voltage V_c) at a first node M₁of capacitor C_cto be random. Anyway, the charged energy at a first node M₂of capacitor C_cis accumulated according to random data S_runtil output voltage V_cexceeds reference voltage V_gnd2. Then, comparator 1044 generates latch signal V_p, for example, at t_pin this embodiment to counter 1046. It should be noted that, latch signal V_pis also a random signal. Furthermore, according to the embodiment of the present invention, counter 1046 is designed to keep in a counting state before output voltage V_cexceeds reference voltage V_gnd2; whenever counter 1046 receives latch signal V_p, counter 1046 will stop counting and latch the counter value N, and output the counter value N to control circuit 1062 of digital to analog functional module 106. Then, control circuit 1062 outputs the respective control values X₁-X_nto digital to analog functional module 106 to convert digital random value S_pinto control voltages V_c1-V_c3. Please note that, whenever a latch signal V_pis generated, second switch S₂discharges the first node M₁of capacitor C_cto the second predetermined voltage V_gnd1according to the first reset signal S_k1.

Please refer to FIG. 2 again, a control clock VCLK is further coupled to control circuit 1062 and counter 1046 for controlling a shift cycling operating of digital frequency jittering circuit 100. Please refer to FIG. 4. FIG. 4 illustrates a frequency domain of the shift cycling operating of digital frequency jittering circuit 100 of FIG. 2. In FIG. 4, the initial switching frequency f_osc, of oscillating signal S_outis restricted in a fixed frequency boundary (f_minto f_max), in which the minimum frequency f_minand the maximum frequency f_maxcorrespond to the minimum counter value N_minand the maximum counter value N_maxof counter 1046, respectively. Therefore, when latch signal V_platches counter 1046 at a counter value between N_minand N_max, for the example, at counter value of N₁, then counter value N₁will be sent to control circuit 1062 and digital random value S_pcorresponding to counter value N₁will be sent to digital to analog converter 1064. Accordingly, digital random value S_pchanges the initial oscillating condition (control voltages V_c1-V_c3) of oscillator 1022 that will shift switching frequency f_oscof oscillating signal S_outinto an initial oscillating frequency f_osc1. Meanwhile, control circuit 1062 sequentially outputs a plurality of increasing control values X₁-X_nto digital to analog converter 1064 according to control clock V_CLK, in which control value X₁is corresponding to counter value N₁, and X₁is corresponding to counter value N_max. When control value reach the maximum control value X_n, control circuit 1062 will shift the control value back to X₁â€², which is corresponding to counter value N_minas shown in FIG. 4. Again, control circuit 1062 sequentially outputs a plurality of increasing control values X₁â€²-X_nâ€² to digital to analog converter 1064 according to control clock V_CLKand X_nâ€² is the control value X₁-1 as shown in FIG. 4. Accordingly, X₁to X_nand X₁â€² to X_nâ€² represent sequential values that will result in the shift cycling operating of digital frequency jittering circuit 100 as shown in FIG. 4. Furthermore, digital to analog functional module 106 converts each control value (X₁to X_nand X₁â€² to X_nâ€²) into control voltages V_c1-V_c3. In other word, each control value (X₁to X_nand X₁â€² to X_nâ€²) will induce control voltages V_c1-V_c3inputted to the ring oscillator (i.e., the oscillator 1022 shown in FIG. 2) that will increase switching frequency f_oscof oscillating signal S_outfrom f_osc1to f_maxand f_minto f_osc1â€², respectively, as shown in FIG. 4. According to the present invention, after control circuit 1062 outputs the last control value X_nâ€² to digital to analog converter 1064 (switching frequency f_oscof oscillating signal S_outis f_osc1â€²), control circuit 1062 will control digital to analog functional module 106 to sustain at the last control value X_nâ€², and output the second reset signal S_k2to counter 1046 to reset counter value N₁to the initial value N_min. The switching frequency f_oscof oscillating signal S_outwill also sustain at f_osc1â€². Then, shift cycling operating of digital frequency jittering circuit 100 can be restarted. Therefore, according to the embodiment of the present invention, the initial switching frequency f_osc1of oscillating signal S_outare randomly distributed between f_minand f_max, and For a long time, the switching frequency f_oscof oscillating signal S_outwill randomly distributed between f_minand f_max. Therefore, the present invention is able to enhance EMI (i.e., electromagnetic interference) protection of switching power. Please note that, control circuit 1062 of the present invention is not limited sequentially outputs a plurality of increasing control values to digital to analog converter 1064, but also can be designed as sequentially outputs a plurality of decreasing control values to digital to analog converter 1064 that according to the requirement of designer.

Please refer to FIG. 5. FIG. 5 illustrates a method for varying a switching frequency of a power supply according to digital frequency jittering circuit 100 in FIG. 1. The method comprises the steps as shown below:

Step 502: Generate an oscillating signal S_outhaving the switching frequency f_osc;

Step 504: Delay oscillating signal S_outby a first delay amount Î”t₁to generate a first delayed signal S_d1and delay oscillating signal S_outby a second delay amount Î”t₂to generate a second delayed signal S_d2, wherein the first delay amount Î”t₁is not equal to the second delay amount Î”t₂;

Step 506: Detect a phase error Î”Ï† between the first and the second delayed signals S_d1, S_d2to generate a random data S_r, and allow the first predetermined voltage V_ddto charge capacitor C_caccording to random data S_r;

Step 508: Check if the output voltage V_cexceeds reference voltage V_gnd2. When output voltage V_cexceeds reference voltage V_gnd2, go to step 510; otherwise, go to step 506;

Step 509: Generate a latch signal V_p;

Step 510: Latch counter value N as random value S_p; and

Step 512: Vary switching frequency f_oscof oscillating signal S_outaccording to digital random value S_p, and after a shift cycling operating of digital frequency jittering circuit 100, go to step 502.

In step 504, delay amounts Î”t₁=3T (540 degrees) and Î”t₂=T (180 degrees), in which T is period of oscillating signal S_out. In step 512, the method sequentially outputs a plurality of increasing control values X₁-X_nand then X₁â€² to X_nâ€² to vary switching frequency f_oscof oscillating signal S_outthat will complete a shift cycling operating of digital frequency jittering circuit 100.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.