FIELD OF THE INVENTION

The present invention relates in general to DC-DC converters and subsystems thereof, and is particularly directed to a new and improved multi-phase DC-DC converter of the type that employs single-ended current sensing for current-sharing control of the operation of the respective power channels/phases of the DC-DC converter. In addition to coupling primary sensed currents sensed relative to the phase nodes of power stages of the respective phases to differential measurement and control circuitry of a supervisory controller, additional, secondary sensed currents, associated with the primary currents, are fed back from output nodes of all channels by way of reduced circuitry complexity auxiliary resistor networks to the supervisory controller. This enables the controller to more completely take into account the influence of the currents of each channel on every other channel, whereby phase-balanced control of all converter channels is achieved, irrespective of symmetry of the integrated circuit layout of the different phases of the converter.

BACKGROUND OF THE INVENTION

A multi-phase DC-DC converter uses a supervisory multi-channel controller to regulate the power delivered by multiple phases or power channels of the converter to an output node feeding a load. As a non-limiting example, FIG. 1 diagrammatically illustrates a conventional dual-phase DC-DC converter, which contains two power channels 100 and 200, that drive an output node OUT with an output voltage Vo. The output voltage is regulated by a supervisory controller 500, which monitors output currents ISEN1 and ISEN2 sensed at current sensing ports coupled to phase nodes 125 and 225 of respective power switching stages 120 and 220 of the two channels, and uses this current information to precisely control the pulse widths of associated streams of pulse width modulation (PWM) waveforms applied by respective PWM generators 10 and 20 to drivers 110 and 210 that control switching times of switching devices (e.g., MOSFETs) of the output power switching stages 120 and 220. The PWM waveforms are sequenced and timed such that the interval between rising edges (or in some implementations, falling edges) thereof is constant, for the purpose of equalizing the currents delivered by the two power channels. (The sum of the current measurements may also be also used to precisely regulate the output resistance in a method commonly known as droop regulation or load-line regulation.)

More particularly, in the two-phase DC-DC converter architecture of FIG. 1, the first power switching stage 120 is shown as including an upper power semiconductor switch (e.g., MOSFET) 121, and a lower power semiconductor switch (e.g., MOSFET) 122 having the source-drain paths thereof coupled in series between an input voltage (Vin) supply terminal 123 and a reference voltage (ground) terminal 124. The control or gate input of the upper MOSFET switch 121 is coupled to a first output 111 of the first channel driver 110, while the control or gate input of lower MOSFET switch 122 is coupled to a second output 112 of the first channel driver. The common or phase node 125 between the upper and lower MOSFET switches 121 and 122 provides a voltage V1P, and is coupled by way of an output inductor (Lo) 126 to the output node OUT, to which a first phase/channel output voltage V1N from the first power channel is applied. An output current sense resistor 127 (having a resistor value Rs) is coupled between the phase node 125 and a current sense node 129 by way of which a measure ISEN1 of the output current of the first channel is derived for application to the controller 500. A capacitor (Cs) 128 is coupled between current sense node 129 and the output node OUT.

In a like manner, the second power switching stage 220 contains an upper power semiconductor switch (MOSFET) 221, and a lower power semiconductor switch (MOSFET) 222 having the source-drain paths thereof coupled in series between the input voltage (Vin) supply terminal 123 and the reference voltage (ground) terminal 124. The control or gate input of upper MOSFET switch 221 is coupled to a first output 211 of the second channel driver 210, while the control or gate input of lower MOSFET switch 222 is coupled to a second output 212 of the second channel driver. The common or phase node 225 between the upper and lower MOSFET switches 221 and 222, which provides a voltage V2P, is coupled by way of an output inductor (Lo) 226 to the output node OUT, to which a second phase/channel output voltage V2N from the second power channel is applied. An output current sense resistor 227 (having a resistor value Rs) is coupled between the phase node 225 and a current sense node 229 by way of which a measure ISEN2 of the output current of the second channel is derived for application to the controller 500. A capacitor (Cs) 228 is coupled between current sense node 229 and the output node OUT.

To control the operation of the first power channel 100, controller 500 includes a first difference amplifier 510, which has a first, non-inverting (+) input 511 coupled to the first channel's current sense node 129, so as to receive a measure of the first sensed current ISEN1, and a second, inverting input (âˆ’) 512 coupled to receive a voltage representative of the average I_AVGof the first and second currents ISEN1 and ISEN2 as produced by an averaging circuit 515. Averaging circuit 515 includes a summing unit 516 coupled to the two current sensed nodes 129 and 229 from which the sensed currents ISEN1 and ISEN2 are supplied. The output of summing unit 516 is coupled to a divide-by-two divider 517, which outputs a voltage representative of the average current value I_AVGof the two sense currents ISEN1 and ISEN2. The output 513 of difference amplifier 510 is used to provide a first correction voltage ICOR1 representative of the difference between the first channel's sensed current ISEN1 and the average I_AVGof the two sensed currents.

For controlling the operation of the second power channel 200, controller 500 includes a second difference amplifier 520, which has a first, non-inverting (+) input 521 thereof coupled to the second channel's current sense node 229, so as to receive a measure of the second sensed current ISEN2, and a second, inverting input (âˆ’) 522 coupled to receive the voltage representative of the average output I_AVGof averaging circuit 515. The output 523 of difference amplifier 520 is used to provide a second correction voltage ICOR2 representative of the difference between the second channel's sensed current ISEN2 and the average I_AVGof the two sensed currents.

The first correction voltage ICOR1 is coupled to a first (âˆ’) input 541 of a subtraction unit 540, which has a second (+) input 542 coupled to receive an error voltage generated at the output 553 of an error amplifier 550. Error amplifier 550 generates an error voltage representative of the difference between a reference voltage Vref coupled to a first, non-inverting (+) input 551 thereof, and the output voltage Vo that is fed back from the output node OUT to a second, inverting (âˆ’) input 551 thereof, and couples this error voltage to second (+) inputs 542 and 562 of respective subtraction units 540 and 560. Subtraction unit 560 has a first (âˆ’) input coupled to receive the second correction voltage ICOR2 at the output 523 of difference amplifier 520. The output 543 of subtraction unit 540 serves as the control input for the PWM modulator 10 of the first power channel 100, while the output 563 of subtraction unit 560 serves as the control input for the PWM modulator 20 of the second power channel 200.

In operation, any difference between the output voltage Vo sensed at the output terminal OUT and the reference voltage Vref produces an error voltage at the output of error amplifier 550. This error voltage constitutes a principal control metric for adjusting the PWM waveforms produced by PWM modulators 10 and 20 of the respective power channels/phases 100 and 200. Since it monitors the currents ISEN1 and ISEN2 sensed at the outputs of the two power channels 100 and 200, controller 500 is able to determine any imbalance in these currents for the two channels, by comparing each channel's sensed current with the average value I_AVGOf the sensed currents for both phases. Any difference between a sensed current for a respective channel i and the average I_AVGof the sensed currents for the two channels results in a correction voltage ICORi that is used to offset or modify the error voltage produced by error amplifier 550, and thereby the pulse widths of the PWM waveforms generated by the PWM generators 10 and 20, so as to equalize the currents delivered by the two power channels.

Now although the output current monitoring and imbalance correction mechanism employed in the converter architecture of FIG. 1 is intended to effectively equalize the currents delivered by the two power channels, it can do so provided that the circuitry layouts of the respective power channels of the converter are symmetric with respect to one another. Otherwiseâ€”namely, in the case of a non-symmetric circuit layoutâ€”the output voltage V1N for the first channel/phase will not equal the output voltage V2N for the second channel/phase, resulting in a current imbalance between the different channels, and preventing the controller from equalizing the currents in the two power channels.

This lack of symmetry in the power channel circuit layouts of a multi-phase DC-DC converterâ€”which is not uncommon as the number of power channels increases, and can be expected to be the case where the converter employs an odd number of channels/phasesâ€”is due principally to the fact that the distances from the controller to the most remote power channels increase substantially as the number of phases/channels increases. This makes it very difficult for the designer to preserve signal integrity of the current-sense lines, due to the fact that these lines typically traverse long distances through a noisy environment from the output current monitoring nodes and the controller, and the fact that the signals transmitted on the current-sense lines are voltage signals proportional to current, and voltage signals are prone to corruption from capacitively-coupled noise.

SUMMARY OF THE INVENTION

In accordance with the present invention, the above-described circuitry layout asymmetry-based current imbalance problem in a multi-phase DC-DC converter is effectively obviated by a new and improved multi- or M-phase DC-DC converter architecture, where M corresponds to two or more phases, that incorporates auxiliary resistor networks to feed back voltages representative of secondary sensed currents derived from the output nodes for each phase, and associated with the primary currents, to the converter's supervisory controller, in addition to coupling thereto primary currents sensed relative to the common nodes of the respective phases. This enables the controller to more completely take into account the influence of the currents of each channel on every other channel, whereby phase-balanced control of all converter channels is achieved, irrespective of symmetry of the integrated circuit layout of the different phases of the converter.

To this end, similar to the dual-phase DC-DC converter of FIG. 1, which contains two phases or power channels, the M-phase converter architecture of the present invention includes M power channels, respective switched power stages of which are driven by associated channel drivers. Each of these M the power stages contains an upper power MOSFET switch and a lower power MOSFET switch having the source-drain paths thereof coupled in series between an input voltage supply terminal and a reference potential terminal. The control or gate input of the upper MOSFET switch is coupled to a first output of an associated driver for that stage, while the control or gate input of the lower MOSFET switch is coupled to a second output of the driver for that stage.

The common/phase nodes between the upper and lower MOSFET switches of the M respective power stages, at which voltages V1P, V2P, . . . , VMP are provided, are coupled to respective output inductors, which supply respective phase/channel output voltages V1N, V2N, . . . , VMN to the converter's output node. The common nodes are further coupled through first resistors to associated primary current sense nodes ISEN1, ISEN1, . . . , ISENM, which are respectively coupled to first through Mth inputs ISEN1, ISEN2, . . . , ISENM inputs of the converter's controller.

In addition, each of the M power channels includes a plurality of Mâˆ’1 auxiliary current sense coupling resistors, that are coupled to sense secondary currents associated with the primary currents sensed in the other Mâˆ’1 phases. Each of the primary and secondary resistors has the same resistance value. The Mâˆ’1 auxiliary current sense resistors of a respective ith power channel are coupled between the output node of that ith power channel at which a respective output voltage ViN is provided, and the current sense input ports of the controller for the other Mâˆ’1 phases. Thus, the M-phase converter architecture of the invention includes a total of M primary current sense resistors, respectively coupled to M phase nodes at which voltages V1P-VMP are provided, and an additional M*(Mâˆ’1) secondary current sense resistors coupled to M output nodes at which voltages V1N-VMN are provided.

Since each of the secondary current sense resistors has the same value of resistance Rs as the primary current sense resistors, the values of the sensed output currents fed back to the controller's M input ports ISEN1-ISENM will be defined in accordance with an average of the respective voltages to which the current sense resistors for each sensed current are coupled. This corresponds to one-Mth of the sum of the respective voltages, so that ISEN1=(1/M)*(V1P+V2N+ . . . +VMN); ISEN2=(1/M)*(V2P+V1N+V3N+ . . . +VMN); and ISENM=(1/M)*(VMP+V1N+ . . . +V(Mâˆ’1)N).

For controlling the respective power channels of the M-phase converter, the controller IC includes M difference amplifiers that are connected substantially as in the conventional converter of FIG. 1, except that the I_AVGreference for the M difference amplifiers is produced by the output of a divide-by-M divider within an averaging circuit, the front end of which sums the M sensed currents ISEN1-ISENM that are fed back from the M primary current sense resistors and the M*(Mâˆ’1) secondary current sense resistors of each power stage, described above. The outputs of the M difference amplifiers provide M correction voltages ICOR1-ICORM, that are respectively representative of differences between the M sensed currents ISEN1-ISENM and the average I_AVGof the N sensed currents. These M correction voltages ICOR1-ICORM are subtracted in M subtraction units from an error voltage generated at the output of the error amplifier. The outputs of these subtraction units serve as control inputs for respective PWM modulators of the M power channels.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 diagrammatically illustrates the architecture of a conventional dual phase DC-DC converter employing single ended current sensing for current-sharing control of the power delivered by two power channels to a load;

FIG. 2 diagrammatically illustrates the architecture of a dual-phase DC-DC converter employing single ended current sensing for current-sharing control in accordance with the invention, which incorporates auxiliary resistor networks to couple secondary current sense ports of both power channels/phases to the converter's supervisory controller;

FIGS. 3 and 4 diagrammatically illustrate the architecture of a three-channel/phase DC-DC converter employing single ended current sensing for current-sharing control in accordance with the invention, which incorporates auxiliary resistor networks to couple multiple secondary current sense ports of each of the power channels/phases to the differential measurement and control circuitry of the supervisory controller;

FIG. 5 diagrammatically illustrates an alternative integrated circuit implementation of the primary and auxiliary current sense resistors networks that are employed to couple monitored currents at the outputs of the respective power stages of the power channels of the three-phase converter of FIGS. 3 and 4 to the supervisory controller therefor; and

FIG. 6 diagrammatically illustrates the architecture of an M-phase DC-DC converter employing single ended current sensing for current-sharing control in accordance with the invention, which incorporates auxiliary resistor networks to couple secondary current sense ports of all power channels/phases to the converter's supervisory controller.

DETAILED DESCRIPTION

Before describing the new and improved multi-phase DC-DC converter architecture in accordance with the present invention, it should be observed that the invention resides primarily in a modular arrangement of conventional power supply circuits and electronic signal processing circuits and components therefor. In a practical implementation that facilitates packaging in a hardware-efficient equipment configuration, these modular arrangements may be readily implemented as field programmable gate array (FPGA)-, or application specific integrated circuit (ASIC)-based chip sets. Consequently, the configuration of such an arrangement of circuits and components and the manner in which they are interfaced with one another have, for the most part, been illustrated in the drawings by readily understandable block diagrams, which show only those specific details that are pertinent to the present invention, so as not to obscure the disclosure with details which will be readily apparent to those skilled in the art having the benefit of the description herein. The block diagram illustrations within the various Figures are primarily intended to show the major components of a DC-DC converter according to the invention in a convenient functional grouping, whereby the present invention may be more readily understood.

Attention is now directed to FIG. 2, which is a block diagram of a two-channel or dual-phase DC-DC converter that incorporates auxiliary resistor networks to feed back secondary sensed currents derived from the output nodes of each channel to the differential measurement and control circuitry of the converter's supervisory controller. It should be noted that the invention is not limited to this or any particular number of power channels/phases; a two phase/channel architecture has been illustrated to reduce the complexity of the drawings. The invention is also applicable to multi-phase converter architectures that include three or more phases, as will be described.

As can be seen from a comparison of the dual-phase DC-DC converter architecture of FIG. 2 with that of FIG. 1, the architecture of FIG. 2 for the most part corresponds to the converter architecture shown in FIG. 1, but additionally includes an augmentation thereof, in that a first auxiliary (secondary) current sense coupling resistor 127â€², associated with the current ISEN2 sensed in the second phase/channel 200, has been incorporated into the current sense network circuitry of the first phase/channel 100, and a second auxiliary (secondary) current sense coupling resistor 227â€² associated with the primary current ISEN1 sensed in the first phase/channel 100, has been incorporated into the current sense network circuitry of the second phase/channel 200. The values (Rs) of the auxiliary current sense-coupling resistors 127â€² and 227â€² are the same as those (Rs) of resistors 127 and 227. The architectures of the DC-DC converters of the two Figures are otherwise the same. As such, for purposes of conciseness, a description of the like portions of the two Figures will not be repeated here. Instead, attention may be directed to the above description of FIG. 1 for a description of its like components in FIG. 2.

In the dual-phase DC-DC converter architecture of FIG. 2, a first end of the auxiliary current sense resistor 127â€² of the first power channel 100 is coupled to the V1N voltage output of the first power stage 120 delivered to the output node OUT, while a second end thereof is coupled to the ISEN2 input of the controller 500, to which the ISEN2 current sense port/node 229 of the second power channel 200 is coupled. Since the value Rs of the auxiliary current sense resistor 127â€² is the same as that (Rs) of current sense resistor 227, the current ISEN2 applied to the controller's input port ISEN2 will be defined in accordance with an average of a primary sensed current based upon the voltage V2P to which the resistor 227 is coupled, and a secondary sensed current based upon the voltage V1N to which the resistor 127â€² is coupled. In the present example of a two channel converter, this average is proportional to one-half the sum of the respective voltages V2P and V1N; namely, ISEN2=0.5*(V2P+V1N)/Rs.

In a complementary manner, a first end of the auxiliary current sense resistor 227â€² of the second power channel 200 is coupled to the V2N voltage output of the first power stage 220 delivered to the output node OUT, while a second end thereof is coupled to the ISEN1 input of the controller 500, to which the ISEN1 current sense port/node 129 of the first power channel 100 is coupled. As in the case of the first power channel, since the value Rs of the auxiliary current sense resistor 227â€² is the same as that (Rs) of current sense resistor 127, the current ISEN1 applied to the controller's input port ISEN1 will be defined in accordance with an average of a primary sensed current based upon the voltage V1P to which resistor 127 is coupled, and a secondary sensed current based upon the voltage V2N to which resistor 2271 is coupled. In the present example of a two channel converter, this average is proportional to one-half the sum of the respective voltages V2P and V1N; namely, ISEN2=0.5*(V2P+V1N)/Rs.

From inspection, it can be seen that (V1Pâˆ’V1N)=(V2Pâˆ’V2N), so that the feed back connections from the auxiliary current sense resistors 127â€² and 227â€² effectively provides a differential sensing effect for the controller 500, without having to employ a differential amplifier per channel that entails more complexity and cost. Thus, through the addition of relatively simple auxiliary circuitry (resistor network), the present invention ensures that the converter's supervisory controller is able to independently control the pulse widths of the PWM waveforms for the two different phases/channels 100 and 200 in a manner that effectively balances the outputs currents delivered by the two power channels. Whether or not there is symmetry between the integrated circuit layouts of the two phases of the converter is immaterial.

As described briefly above, the present invention can be extended beyond the two-phase example of FIG. 2 to three or more phases. For example, FIGS. 3 and 4 diagrammatically illustrate the manner in which the auxiliary current sense resistor networks of the two-phase converter architecture of FIG. 2 may be modified to achieve circuit layout-independent current balancing for a three-phase DC-DC converter. In particular, FIG. 3 shows respective power stages 120, 220 and 320 of power channels 100, 200 and 300 of a three-phase converter, which are respectively driven by first, second and third channel driver ICs 110, 210 and 310 of a controller/driver IC diagrammatically illustrated in broken lines 500â€² in FIG. 4.

Like the two-phase DC-DC converters of FIGS. 1 and 2, each of the power stages 120, 220 and 320 of the three-phase converter of FIG. 3 contains an upper power semiconductor switch (e.g., MOSFET) and a lower power semiconductor switch (e.g., MOSFET) having the source-drain paths thereof coupled in series between an input voltage (Vin) supply terminal and a reference voltage (ground) terminal. The control or gate input of the upper MOSFET switch is coupled to a first output of an associated driver for that stage, while the control or gate input of the lower MOSFET switch is coupled to a second output of the driver for that stage. Common or phase nodes 125, 225 and 325 between the upper and lower MOSFET switches of the respective power stages, at which voltages V1P, V2P and V3P are provided, are coupled to respective output inductors (Lo) 126, 226 and 326, which supply respective phase/channel output voltages V1N, V2N and V3N to the converter's output node OUT.

As in the two-phase embodiment of FIG. 2, the V1P output of the first power stage 120 is coupled through a resistor (Rs) 127 to a primary sense current ISEN1 port or node 129, which is further coupled through a capacitor 128 to the output node OUT. Similarly, the V2P output of the second power stage 220 is coupled through a resistor (Rs) 227 to a primary sensed current ISEN2 port or node 229, which is further coupled through a capacitor 228 to the output node OUT, while the V3P output of the third power stage 320 is coupled through a resistor (Rs) 327 to a primary sense current ISEN3 port or node 329, which is further coupled through a capacitor 328 to the output node OUT. The first, second and third primary sense current ports 129, 229 and 329 are coupled to ISEN1, ISEN2 and ISEN3 input ports of the controller/driver IC 500â€² of FIG. 4. In addition, each of the power channels of the three-phase embodiment of FIGS. 3 and 4 further includes a pair of secondary sense current coupling resistors, respective ones of which are associated with the primary currents sensed in the other two phases, coupled between the output node of that power channel and the current sense input ports of the controller/driver IC 500â€² for the other two phases.

In particular, the first power channel 100 includes first and second secondary sense current coupling resistors 127â€² and 127â€³, first ends of which are connected to the V1N voltage output of the first power stage 120, while second ends thereof are coupled to the ISEN2 port and the ISEN3 input, respectively, of the controller 500â€², to which the primary sense current ISEN2 port/node 229 of the second power channel 200 and the primary sense current ISEN3 port/node 329 of the third power channel 300 are coupled. The value Rs of each of the auxiliary current sense resistors 127â€² and 127â€³ is the same as that (Rs) of current sense resistors 227 and 327.

Similarly, the second power channel 200 includes first and second secondary sense current coupling resistors 227â€² and 227â€³, first ends of which are connected to the V2N voltage output of the second power stage 220, while second ends thereof are coupled to the ISEN1 port and the ISEN3 input, respectively, of the controller 500â€², to which the primary sense current ISEN1 port/node 129 of the first power channel 100 and the primary sense current ISEN3 port/node 329 of the third power channel 300 are coupled. The value Rs of each of the auxiliary current sense resistors 227â€² and 227â€³ is the same as that (Rs) of current sense resistors 127 and 327.

Also, the third power channel 300 includes first and second secondary sense current coupling resistors 327â€² and 327â€³, first ends of which are connected to the V3N voltage output of the third power stage 320, while second ends thereof are coupled to the ISEN1 port and the ISEN2 input, respectively, of the controller 500â€², to which the primary sense current ISEN1 port/node 129 of the first power channel 100 and the primary sense current ISEN2 port/node 229 of the third power channel 300 are coupled. The value Rs of each of the auxiliary current sense resistors 327â€² and 327â€³ is the same as that (Rs) of current sense resistors 127 and 227.

As in the case of the dual-phase DC-DC converter architecture of FIG. 2, since each of the secondary sense current coupling resistors has the same value of resistance Rs as the primary sense current coupling resistors, the values of the combined sense currents that are fed back to the controller's three input ports ISEN1, ISEN2 and ISEN3 will be defined in accordance with an average of the respective voltages to which the sense current coupling resistors for each sensed current are coupled, which, in the present example of a three-channel converter, corresponds to one-third of the sum of the respective voltages. Namely ISEN1=0.33*(V1P+V2N+V3N); ISEN2=0.33*(V2P+V1N+V3N); and ISEN3=0.33*(V3P+V1N+V2N).

For controlling the respective power channels 100 and 200 of the three-phase converter of FIGS. 3 and 4, controller 500â€² includes first and second difference amplifiers 510 and 520 that are connected in the same manner as in the dual-phase architecture of FIG. 2. The first, non-inverting (+) input 511 of difference amplifier 510 is coupled to each of the resistors 127, 227â€² and 327â€² associated with the sensed current ISEN1, while the first, non-inverting (+) input 521 of difference amplifier 520 is coupled to each of the resistors 127â€², 227 and 327â€³ associated with the sensed current ISEN2. The second, inverting (âˆ’) inputs 512 and 522 of difference amplifiers 510 and 520, respectively, are coupled to the output I_AVGof a divide-by-three divider 517â€² of an averaging circuit 515â€². This average corresponds to one-third of the summation of the sensed currents ISEN1, ISEN2 and ISEN3 that are fed back to a summation circuit 516â€² from the three current sense resistors of each power stage, described above. The output 513 of difference amplifier 510 provides a first correction voltage ICOR1 representative of the difference between the first channel's sensed current ISEN1 and the average I_AVGof the three sensed currents (ISEN1, ISEN2 and ISEN3), while the output 523 of difference amplifier 520 provides a second correction voltage ICOR2 representative of the difference between the second channel's sensed current ISEN2 and the average I_AVGof the three sensed currents. To control the third power channel 300, controller 500â€² includes a third difference amplifiers 530 having a first, non-inverting (+) input 531 coupled to each of the resistors 127â€³, 227â€³ and 327 associated with the sensed current ISEN3, while the second, inverting (âˆ’) input 532 difference amplifier 530 is coupled to coupled to the output I_AVGof the divide-by-three divider 517â€² of averaging circuit 515â€². The output 533 of difference amplifier 530 provides a third correction voltage ICOR3 representative of the difference between the third channel's sensed current ISEN3 and the average I_AVGof the three sensed currents (ISEN1, ISEN2 and ISEN3).

As in the dual-phase architecture of FIG. 2, the first correction voltage ICOR1 is coupled to a first (âˆ’) input 541 of subtraction unit 540, while the second correction voltage ICOR2 is coupled to a first (âˆ’) input 561 of subtraction unit 560. The third correction voltage ICOR3 is coupled to a first (âˆ’) input 571 of a subtraction unit 570. The subtraction units 540, 560 and 570 have second (+) inputs 542, 562 and 572, respectively, that are coupled to receive the error voltage generated at the output 553 of error amplifier 550. The output 543 of subtraction unit 540 serves as the control input for PWM modulator 10 of the first power channel 100, the output 563 of subtraction unit 560 serves as the control input for PWM modulator 20 of the second power channel 200, and the output 573 of subtraction unit 570 serves as the control input for PWM modulator 30 of the third power channel 300.

Similar to the dual-phase architecture of FIG. 2, for the three-phase embodiment of FIGS. 3 and 4, it can be seen that (V1Pâˆ’V1N)=(V2Pâˆ’V2N)=(V3Pâˆ’V3N), so that the feedback connections from the additional pair of secondary sense current coupling 127â€² and 127â€³ in the first channel, the additional pair of secondary sense current coupling resistors 2271 and 227â€² in the second channel, and the additional pair of secondary sense current coupling resistors 327â€² and 327â€³ in the third channel effectively provide differential sensing for the controller 500, without the need for costly differential amplifiers. Such differential sensing enables the controller to balance the currents delivered by the three power channels, even though the circuit layouts of the three phases of the integrated circuit layout of the converter are not symmetric.

In addition to reducing cost and complexity by eliminating the need for differential amplifiers, the number of sense nodes (e.g., ISEN1, ISEN2, ISEN3, Vo) is also reduced in accordance with the invention, as compared with conventional differential schemes, which require a larger number of sense nodes (e.g., ISEN1P, ISEN1N, ISEN2P, ISEN2N, ISEN3P, ISEN3N). It may also be noted that the resistor networks may be implemented exterior to, or integrated within, the IC controller. In either implementation, there will be a number of pins saving benefit, in addition to a reduced complexity benefit, as far as the IC is concerned.

FIG. 5 diagrammatically illustrates an alternative implementation of the primary and auxiliary current sense resistor networks that are employed to couple output voltage nodes of the respective power stages of the power channels of the three-phase converter of FIGS. 3 and 4 to the controller therefor. In accordance with this alternative implementation, each power channel includes a multi-resistor, resistor-capacitor network, that is connected across the power stage's output inductor Lo. As shown in FIG. 5, the multi-resistor network for a respective ith power stage is comprised of a first resistor Rs, one end of which is connected to the common/phase node at which output voltage ViP for that ith stage is produced, and the other end of which is connected to a capacitor Cs. The capacitor Cs is further coupled to a first end of a second resistor Ro, a second end of which is connected to the output node ViN for that stage. The common node ISIP between the second resistor Rs and the capacitor Cs is coupled through a third, primary current sense resistor Rc to a primary current sense port ISENiâ€² for that ith power stage, while the common node Voâ€² between the capacitor Cs and the resistor Rc serves as the output voltage-monitoring input to the error amplifier. Fourth and fifth (current sense) resistors Rc are coupled between the output node ViN and respective auxiliary current sense ports ISENjâ€² and ISENkâ€². The letters i, j and k correspond to one of the first (1), second (2) and third (3) sensed output currents. The three current sense ports ISEN1â€², ISEN2â€² and ISEN3â€² for each power channel are coupled to associated inputs ISEN1â€², ISEN2â€² and ISEN3â€² of the controller, as in the implementation of FIGS. 3 and 4, so that, as in that implementation, the values of the sensed output currents fed back to the controller's three input ports ISEN1â€², ISEN2â€² and ISEN3â€² will be defined in accordance with the average of the currents sensed by the current sense resistors Rc for each sensed current, whereby ISEN1â€²=0.33*(V1P+V2N+V3N); ISEN2â€²=0.33*(V2P+V1N+V3N); and ISEN3â€² 0.33*(V3P+V1N+V2N).

FIG. 6 diagrammatically illustrates the manner in which the auxiliary current sense resistor networks of the multi-phase DC-DC converter architecture described above with reference to FIGS. 2-4 may achieve circuit layout-independent current balancing for the general case of an M-phase DC-DC converter. In particular, FIG. 6 shows respective power stages 120, 220, . . . , M20 of plurality M of power channels of an M-phase converter, which are respectively driven by first, second, . . . , Mth channel drivers of an associated M-phase controller/driver (not shown in FIG. 6, but effectively corresponding to that of FIGS. 2-4, and coupled to M2 current sense resistors of the M output stages, as will be described).

Like the multi-phase DC-DC converters of FIGS. 2-4, each of the power stages of the M-phase converter of FIG. 6 contains an upper power semiconductor switch (e.g., MOSFET) and a lower power semiconductor switch (e.g., MOSFET) having the source-drain paths thereof coupled in series between an input voltage (Vin) supply terminal and a reference voltage (ground) terminal. The control or gate input of the upper MOSFET switch is coupled to a first output of an associated driver for that stage, while the control or gate input of the lower MOSFET switch is coupled to a second output of the driver for that stage.

The common/phase nodes 125, 225, . . . , M25 between the upper and lower MOSFET switches of the respective power stages, at which voltages V1P, V2P, . . . , VMP are provided, are coupled to respective output inductors (Lo) 126, 226, M26, which supply respective phase/channel output voltages V1N, V2N, . . . , VMN to the converter's output node OUT. The V1P output of the first power stage 120 is coupled through a resistor (Rs) 127-1 to an ISEN1 port or node 129, which is further coupled through a capacitor 128 to the output node OUT. The V2P output of the second power stage 220 is coupled through a resistor (Rs) 227-1 to an ISEN2 port or node 229, which is further coupled through a capacitor 228 to the output node OUT, while the VMP output of the Mth power stage M20 is coupled through a resistor (Rs) M27-1 to an ISENM port or node M29, which is further coupled through a capacitor M28 to the voltage output node OUT. The first through Mth current sense ports 129, 229, M29 are coupled to ISEN1, ISEN2, . . . , ISENM inputs of the converter's controller/driver.

In addition, each power channel of the M-phase converter architecture of FIG. 6 further includes a plurality of Mâˆ’1 auxiliary current sense coupling resistors, coupled to sense secondary currents associated with the primary currents sensed in the other Mâˆ’1 phases. The (Mâˆ’1) auxiliary current sense resistors of a respective ith power channel are coupled between the output node of that ith power channel at which a respective output voltage ViN is provided, and the current sense input ports of the controller/driver for the other Mâˆ’1 phases. Thus, the M-phase architecture of FIG. 6 includes a total of M primary current sense resistors 127-1-M27-1, each having the value Rs and being respectively coupled to M phase nodes at which voltages V1P-VMP are provided, and an additional M*(Mâˆ’1) secondary current sense resistors 127-2-127-M, . . . , M27-1-M27-M, each having the same value Rs, and being coupled to M output nodes at which voltages V1N-VMN are provided.

Namely, the first power channel includes Mâˆ’1 auxiliary resistors 127-2-127-M, first ends of which are connected to the V1N voltage output of the first power stage 120, while second ends thereof are coupled to the ISEN2 through ISENM inputs, respectively, of the controller. Similarly, the second power channel includes M auxiliary current sense resistors 227-2-227-M, first ends of which are connected to the V2N voltage output of the second power stage 220, while second ends thereof are coupled to the ISEN1 input and to the ISEN3-ISENM inputs, respectively, of the controller. Also, the Mth power channel includes M auxiliary resistors M27-2-M27-M, first ends of which are connected to the VMN voltage output of the Mth power stage M20, while second ends thereof are coupled to the ISEN1-ISEN(Mâˆ’1) inputs, respectively, of the controller.

Again, since each of the secondary current sense resistors has the same value of resistance Rs as the primary current sense resistors, the values of the sensed output currents fed back to the controller's M input ports ISEN1-ISENM will be defined in accordance with an average of the respective voltages to which the current sense resistors for each sensed current are coupled. For the present example of an M-channel converter, this corresponds to one-Mth of the sum of the respective voltages. Namely ISEN1=(1/M)*(V1P+V2N+ . . . +VMN); ISEN2=(1/M)*(V2P+V1N+V3N+ . . . +VMN); and ISENM=(1/M)*(VMP+V1N++V(Mâˆ’1)N).

For controlling the respective power channels of the M-phase converter, the controller IC includes M difference amplifiers that are connected in the same manner as in the two-phase and three-phase embodiments of FIG. 2-4, except that the I_AVGreference for the M difference amplifiers is produced by the output of a divide-by-M divider within an averaging circuit, the front end of which sums the M primary sensed currents sensed by the M primary sensed current coupling resistors with the M*(Mâˆ’1) secondary sensed currents ISEN1-ISENM that are fed back from the M*(Mâˆ’1) auxiliary, secondary current sense resistors of each power stage, described above. The outputs of the M difference amplifiers provide M correction voltages ICOR1-ICORM, that are respectively representative of differences between the composite values of the M sensed currents ISEN1-ISENM and the average I_AVGof the composite values of the M sensed currents. Similar to the above embodiments, these M correction voltages ICOR1-ICORM are coupled to first inputs of respective ones of M subtraction units, second inputs of which are coupled to receive the error voltage generated at the output of the error amplifier. The outputs of these subtraction units serve as control inputs for respective PWM modulators of the M power channels. Similar to the two-phase and three-phase embodiments, described above, in the M-phase embodiment (V1Pâˆ’V1N)=(V2Pâˆ’V2N)=(VMPâˆ’VMN).

As will be appreciated from the foregoing description, the above-described asymmetry circuitry layout-based current imbalance problem encountered in a multi-phase DC-DC converter is effectively obviated in accordance with the multi-phase DC-DC converter architecture of the present invention, which uses reduced complexity implementation-based, resistor-coupling to feed back values of sensed currents at secondary current sense ports that couple the output nodes for each phase to differential measurement and control circuitry within the converter's supervisory controller. This enables the controller to perform current-balanced control of pulse widths of the switching waveforms produced by the PWM modulators for all channels, whether or not there is symmetry among the integrated circuit layouts of those channels.

While we have shown and described several embodiments in accordance with the present invention, it is to be understood that the same is not limited thereto but is susceptible to numerous changes and modifications as known to a person skilled in the art, and we therefore do not wish to be limited to the details shown and described herein, but intend to cover all such changes and modifications as are obvious to one of ordinary skill in the art.