BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a switching voltage regulator and, more particularly, to a switching voltage regulator with an improved range of input voltage.

2. Description of the Related Art

FIG. 1(a) is a circuit diagram showing a conventional switching voltage regulator 10a. The switching voltage regulator 10a converts an input voltage V_ininto an output voltage V_outfor being supplied to a load Ld. A high-side switch SH is coupled between the input voltage V_inand a switch node SN while a low-side switch SL is coupled between the switch node SN and a ground potential. As to the example of FIG. 1(a), the high-side switch SH is implemented by a PMOS transistor while the low-side switch SL is implemented by an NMOS transistor. An inductor L is coupled between the switch node SN and an output terminal O. An output capacitor C_ois coupled to the output terminal O for filtering the output voltage V_out.

The switching voltage regulator 10a has an oscillating signal generating circuit 11 and a switch control system 15 constituted by a latch 12, a PWM control circuit 13, and a drive circuit 14. The oscillating signal generating circuit 11 generates a pulse oscillating signal PL and a ramp oscillating signal RM, both of which are in synchronization with respect to each other. The rising edge of the pulse oscillating signal PL is corresponding to the peak of the ramp oscillating signal RM while the falling edge of the pulse oscillating signal PL is corresponding to the valley of the ramp oscillating signal RM. The pulse oscillating signal PL is applied to a set terminal S of the latch 12 while the ramp oscillating signal RM is applied to the PWM control circuit 13. When the rising edge of the pulse oscillating signal PL triggers the latch 12 through the set terminal S, the drive signal DR from the output terminal Q of the latch 12 changes into the HIGH level. Through the drive circuit 14, the HIGH level of the drive signal DR turns on the high-side switch SH and turns off the low-side switch SL, such that the switching voltage regulator 10a enters the so-called ON operating phase. During the ON operating phase, the inductor current I_Lgradually increases.

A voltage feedback signal FV is representative of the output voltage V_outwhile a current feedback signal FI is representative of the inductor current I_L. In response to the voltage feedback signal FV, the current feedback signal FI, and the ramp oscillating signal RM, the PWM control circuit 13 applies a control signal CS to a reset terminal R of the latch 12. Regardless of the current mode or the voltage mode adopted in the PWM control method, the drive signal DR from the output terminal Q of the latch 12 changes into the LOW level when the control signal CS triggers the latch 12 through the reset terminal R. Through the drive circuit 14, the LOW level of the drive signal DR turns off the high-side switch SH and turns on the low-side switch SL, such that the switching voltage regulator 10a enters the so-called OFF operating phase. During the OFF operating phase, the inductor current I_Lgradually decreases.

More specifically, the switching voltage regulator 10a shown in FIG. 1(a) belongs to the step-down type, i.e., converting a higher input voltage V_ininto a lower output voltage V_out. The step-down switching voltage regulator 10a has a duty cycle D_aas expressed in the following equation (1a): $\begin{matrix} D_{a} â‰¡ \frac{T_{ON}}{(T_{ON} + T_{OFF})} = \frac{V_{out}}{V_{in}} & (1 â ¢ a) \end{matrix}$
wherein T_ONis representative of the time of the ON operating phase each period while T_OFFis representative of the time of the OFF operating phase each period. The sum of T_ONand T_OFFequals to the period T_Sof the pulse oscillating signal PL (or the ramp oscillating signal RM).

As appreciated from equation (1a), T_ONbecomes longer when the input voltage V_inbecomes closer to the output voltage V_out. The increase of T_ONcauses T_OFFto decrease since the period T_Sof the pulse oscillating signal PL is a constant. However, when the high-side switch SH is turned off from on and the low-side switch SL is turned on from off, a finite physical time is necessary for the accumulation and depletion of the charges. Therefore, T_OFFmust be limited to being larger than a predetermined minimum T_{OFF, min}for allowing an appropriate switching operation to be possible. For example, when the minimum T_{OFF, min}is set as 15% of the switching period T_S, the duty cycle D_ahas an upper limit of 0.85. In the case where the input voltage V_inreduces to become lower than (V_out/0.85), the switching voltage regulator 10a fails to provide the regulated output voltage V_outsince T_OFFhas been shortened to reach its minimum T_{OFF, min}. Generally speaking, the conventional switching voltage regulator 10a is unable to provide the regulated output voltage V_outwhen the input voltage V_inis lower than [T_S/(T_S-T_{OFF, min})]*V_out.

FIG. 1(b) is a circuit diagram showing another conventional switching voltage regulator 10b. The switching voltage regulator 10b belongs to a step-up type, i.e., converting the lower input voltage V_ininto the higher output voltage V_out. In the step-up switching voltage regulator 10b, the high-side switch SH is coupled between the switch node and the output terminal O while the inductor L is coupled between the input voltage V_inand the switch node SN. Moreover, the ON operating phase is executed through turning off the high-side switch SH and turning on the low-side switch SL, causing the inductor current I_Lto increase. The OFF operating phase is executed through turning on the high-side switch SH and turning off the low-side switch SL, causing the inductor current I_Lto decrease. The step-up switching voltage regulator 10b has a duty cycle D_bas expressed in the following equation (1b): $\begin{matrix} D_{b} â‰¡ \frac{T_{ON}}{(T_{ON} + T_{OFF})} = \frac{(V_{out} - V_{in})}{V_{out}} & (1 â ¢ b) \end{matrix}$

As appreciated from equation (1b), T_ONbecomes shorter when the input voltage V_inbecomes closer to the output voltage V_out. However, when the high-side switch SH is turned on from off and the low-side switch SL is turned off from on, a finite physical time is necessary for the accumulation and depletion of the charges. Therefore, T_ONmust be limited to being larger than a predetermined minimum T_{ON, min}for allowing an appropriate switching operation to be possible. For example, when the minimum T_{ON, min}is set as 15% of the switching period T_S, the duty cycle D_bhas an upper limit of 0.85. In the case where the input voltage V_inrises to become higher than (0.85*V_out), the switching voltage regulator 10b fails to provide the regulated output voltage V_outsince T_ONhas been shortened to reach its minimum T_{ON, min}. Generally speaking, the conventional switching voltage regulator 10b is unable to provide the regulated output voltage V_outwhen the input voltage V_inis lower than [(T_S-T_{ON, min})/T_S]*V_out.

SUMMARY OF THE INVENTION

In view of the above-mentioned problems, an object of the present invention is to provide a switching voltage regulator with an improved range of input voltage.

According to one aspect of the present invention, a switching voltage regulator is provided for converting an input voltage into an output voltage. The switching voltage regulator has: a first switch; a second switch; an inductor, a switch control system, a duty cycle detecting circuit, an oscillating signal adjusting circuit, and an oscillating signal generating circuit. The first switch, the second switch, and the inductor are coupled together to a switch node. When the first switch is turned on and the second switch is turned off, an inductor current flowing through the inductor increases. When the first switch is turned off and the second switch is turned on, the inductor current decreases. The switch control system generates a drive signal to control the first switch and the second switch. The duty cycle detecting circuit detects a duty cycle of the drive signal. When the duty cycle is larger than a predetermined threshold, the duty cycle detecting circuit generates an over-threshold signal. When the duty cycle is smaller than the predetermined threshold, the duty cycle detecting circuit generates an under-threshold signal. In response to the over-threshold signal and the under-threshold signal, the oscillating signal adjusting circuit determines an adjusting current. The oscillating signal generating circuit generates and applies an oscillating signal to the switch control system. The oscillating signal has a period adjusted by the adjusting current.

BRIEF DESCRIPTION OF THE DRAWINGS

The above-mentioned and other objects, features, and advantages of the present invention will become apparent with reference to the following descriptions and accompanying drawings, wherein:

FIG. 1(a) is a circuit diagram showing a conventional switching voltage regulator;

FIG. 1(b) is a circuit diagram showing another conventional switching voltage regulator;

FIG. 2 is a circuit diagram showing a switching voltage regulator according to a first embodiment of the present invention;

FIG. 3 is a detailed circuit diagram showing an oscillating signal generating system of FIG. 2;

FIG. 4 is a waveform timing chart showing an operation of an oscillating signal generating system of FIG. 2;

FIG. 5 is a circuit diagram showing a switching voltage regulator according to a second embodiment of the present invention;

FIG. 6 is a detailed circuit diagram showing an oscillating signal generating system of FIG. 5; and

FIG. 7 is a waveform timing chart showing an operation of an oscillating signal generating system of FIG. 5.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The preferred embodiments according to the present invention will be described in detail with reference to the drawings.

FIG. 2 is a circuit diagram showing a switching voltage regulator 20 according to a first embodiment of the present invention. The switching voltage regulator 20 belongs to the step-down type, i.e., converting the higher input voltage V_ininto the lower output voltage V_out.

The switching voltage regulator 20 has a switch control system 15 and an oscillating signal generating system 24. The switch control system 15 is constituted by a latch 12, a PWM control circuit 13, and a drive circuit 14. The oscillating signal generating system 24 is constituted by a duty cycle detecting circuit 21, an oscillating signal adjusting circuit 22, and an oscillating signal generating circuit 23.

More specifically, the duty cycle detecting circuit 21 detects the duty cycle D_aof the drive signal DR. When the input voltage V_inbecomes closer to the output voltage V_out, the duty cycle D_aof the drive signal DR becomes larger. When the duty cycle D_aof the drive signal DR exceeds a predetermined threshold, the duty cycle detecting circuit 21 generates an over-threshold signal OT. In response to the over-threshold signal OT, the oscillating signal adjusting circuit 22 causes the oscillating signal generating circuit 23 to prolong the period T_Sof the pulse oscillating signal PL (and the ramp oscillating signal RM). As appreciated from equation (1a), a longer period T_Sallows a larger duty cycle D_ato be possible since the minimum T_{OFF, min}in is constant. Moreover, the lower limit [TS/(T_S-T_{OFF, min})]*V_outof the applicable range of the input voltage V_inis expanded closer to the output voltage V_outwhen the period T_Sbecomes longer. As a result, the switching voltage regulator 20 according to the present invention can be applied with a broader range of input voltage V_in.

On the other hand, for avoiding the period T_Sfrom being prolonged so much that the switching frequency becomes too low, the duty cycle detecting circuit 21 generates an under-threshold signal UT when the duty cycle D_aof the drive signal DR becomes lower than the predetermined threshold. In response to the under-threshold signal UT, the oscillating signal adjusting circuit 22 causes the oscillating signal generating circuit 23 to shorten the period T_Sof the pulse oscillating signal PL (and the ramp oscillating signal RM).

Hereinafter is described in detail an operation of the oscillating signal generating system 24 according to the present invention with reference to FIGS. 3 and 4. First of all, it is assumed that an NMOS transistor N1 of the oscillating signal generating circuit 23 is turned on such that the voltage at the oscillating node N_oscis reduced to the ground potential. Once the NMOS transistor N1 of the oscillating signal generating circuit 23 is turned off, an oscillating current source I_oscstarts charging an oscillating capacitor C_osc, causing the voltage at an oscillating node N_oscto gradually increase. A comparator 31 has a non-inverting input terminal for receiving the voltage at the oscillating node N_osc, and an inverting input terminal for receiving a reference voltage source V_ref. When the voltage at the oscillating node N_oscexceeds the reference voltage V_ref, the comparator 31 outputs a rising edge for triggering a one-shot circuit 32 to generate a first auxiliary signal DS1. Through a delay circuit 33 and then an inverter, the first auxiliary signal DS1 is transformed into a second auxiliary signal DS2. Therefore, the second auxiliary signal DS2 lags by a predetermined time dt and is out of phase with respect to the first auxiliary signal DS1. Subsequently through a NOR logic gate 34, the first and the second auxiliary signals DS1 and DS2 are coupled to from the pulse oscillating signal PL. Once the second auxiliary signal DS2 changes to the LOW level from the HIGH level, a NOR logic gate 35 outputs the HIGH level to turn on the NMOS transistor N1 such that the voltage at the oscillating node N_oscis rapidly reduced to the ground potential. Therefore, the voltage at the oscillating node N_oscis output for serving as the ramp oscillating signal RM.

The first and the second auxiliary signals DS1 and DS2 are applied to the duty cycle detecting circuit 21 for assisting the detection to the duty cycle D_aof the drive signal DR. The first auxiliary signal DS1 is used for setting a threshold. In the duty cycle detecting circuit 21, an NAND logic gate 36 has three input terminals for receiving the first auxiliary signal DS1, the second auxiliary signal DS2, and the drive signal DR, respectively. When the duty cycle D_aof the drive signal DR is smaller than the threshold set by the first auxiliary signal DS1, e.g., the first, the second, and the fifth periods PP1, PP2, and PP5 shown in FIG. 4, the NAND logic gate 36 outputs the LOW level. When the duty cycle D_aof the drive signal DR is larger than the threshold set by the first auxiliary signal DS1, e.g., the third and the fourth periods PP3 and PP4 shown in FIG. 4, the NAND logic gate 36 outputs a pulse for serving as the over-threshold signal OT. It should be noted that the width of the pulse of the over-threshold signal OT is determined in accordance with a difference between the duty cycle D_aof the drive signal DR and the threshold. The larger the difference between the duty cycle D_aof the drive signal DR and the threshold, the larger the width of the pulse of the over-threshold signal OT. For example in FIG. 4, the over-threshold signal OT in the third period PP3 has a larger width of pulse than the over-threshold signal OT in the fourth period PP4.

On the other hand, in the duty cycle detecting circuit 21, the NOR logic gate 37 has three input terminals for receiving the first auxiliary signal DS1, the second auxiliary signal DS2 after inverted, and the drive signal DR. When the duty cycle D_aof the drive signal DR is larger than the threshold set by the first auxiliary signal DS1, e.g., the third and the fourth periods PP3 and PP4 shown in FIG. 4, the NOR logic gate 37 outputs the LOW level. When the duty cycle D_aof the drive signal DR is smaller than the threshold set by the first auxiliary signal DS1, e.g., the first, the second, and the fifth periods PP1, PP2, and PP5 shown in FIG. 4, the NOR logic gate 37 outputs a pulse for serving as the under-threshold signal UT. It should be noted that the width of the pulse of the under-threshold signal UT is determined in accordance with the difference between the duty cycle D_aof the drive signal DR and the threshold. The larger the difference between the duty cycle D_aof the drive signal DR and the threshold, the larger the width of the pulse of the under-threshold signal UT. For example in FIG. 4, the under-threshold signal UT in the first period PP1 has a larger width of pulse than the under-threshold signal UT in the second period PP2.

The over-threshold signal OT is applied to the oscillating signal adjusting circuit 22 for turning on a PMOS transistor P1 such that a current source I₁starts charging an adjusting capacitor C_adj. Through a transistor N3, the potential difference across the adjusting capacitor C_adjis level-shifted to form an adjusting voltage V_adj. The adjusting voltage V_adjis applied across an adjusting resistor R_adjto generate an adjusting current I_adj. Assumed that PMOS transistors P2 and P3 together form a 1Ã—1 current mirror and NMOS transistors N4 and N5 together form another 1Ã—1 current mirror, the same adjusting current I_adjas described above is generated to flow through the drain and the source electrodes of the NMOS transistor N5. At the presence of the adjusting current I_adj, the current for charging the oscillating capacitor C_oscin the oscillating signal generating circuit 23 is decreased to become (I_osc-I_adj). As a result, the rising rate of the voltage at the oscillating node N_oscslows down so as to produce a longer period T_Sof the ramp oscillating signal RM (and the pulse oscillating signal PL). For example in FIG. 4, the third period PP3 generates the over-threshold signal OT, by which the fourth period PP4 is prolonged by dT₁in comparison with the former period, and the fourth period PP4 also generates the over-threshold signal OT, by which the fifth period PP5 is prolonged by dT₂in comparison with the former period. Because a longer period T_Sallows a larger duty cycle D_ato be possible, the input voltage V_inmay decrease closer to the output voltage V_out, such that the switching voltage regulator 20 according to the present invention may be applied with a broader range of input voltage.

When the over-threshold signal OT has a wider pulse, the PMOS transistor P1 of the oscillating signal adjusting circuit 22 is kept on for a longer time, causing the adjusting voltage V_adjto rise higher. As a result, a larger adjusting current I_adjis generated to flow through the drain and the source electrodes of the NMOS transistor N5, thereby producing a longer period T_Sof the ramp oscillating signal RM (and the pulse oscillating signal PL).

The under-threshold signal UT is applied to the oscillating signal adjusting circuit 22 for turning on an NMOS transistor N2 such that a current source 12 starts discharging the adjusting capacitor C_adj. As a result, the decrease of the potential difference across the adjusting capacitor C_adjcauses the adjusting voltage V_adjand the adjusting current I_adjto become lower. Because the current for charging the oscillating capacitor C_oscin the oscillating signal generating circuit 23 is (I_osc-I_adj), the lower adjusting current I_adjcauses the rising rate of the voltage at the oscillating node N_oscto become faster. For this reason, the period T_Sof the ramp oscillating signal RM (and the pulse oscillating signal PL) is shortened. For example in FIG. 4, the fifth period PP5 generates the under-threshold signal UT, by which the sixth period PP6 is shortened by dT₃in comparison with the former period. Therefore, when the input voltage V_inbecomes closer to the output voltage V_out, the switching voltage regulator 20 according to the present invention automatically adjusts, i.e., either prolongs or shortens, the period T_S.

It should be noted that when the difference between the input voltage V_inand the output voltage V_outbecomes significantly large, the duty cycle D_aof the drive signal DR is kept smaller than the threshold set by the first auxiliary signal DS1, e.g., the first and the second periods PP1 and PP2 shown in FIG. 4. In this case, the under-threshold signal UT is continuously applied to the oscillating signal adjusting circuit 22, causing the adjusting capacitor C_adjto be continuously discharged until no potential difference exists across the adjusting capacitor C_adj. As a result, the period T_Sof the ramp oscillating signal RM (and the pulse oscillating signal PL) stays at the predetermined minimum.

FIG. 5 is a circuit diagram showing a switching voltage regulator 50 according to a second embodiment. The second embodiment shown in FIG. 5 is different from the first embodiment shown in FIG. 2 in that the switching voltage regulator 50 according to the second embodiment belongs to the step-up type, i.e., converting a lower input voltage V_ininto a higher output voltage V_outfor being supplied to the load Ld. Therefore in the switching voltage regulator 50, the high-side switch SH is coupled between the switch node SN and the output terminal O, the low-side switch SL is coupled between the switch node SN and the ground potential, and the inductor is coupled between the input voltage V_inand the switch node SN.

The switching voltage regulator 50 is different from the conventional switching voltage regulator 10b shown in FIG. 1(b) in that the switching voltage regulator 50 employs an oscillating signal generating system 54 constituted by a duty cycle detecting circuit 51, an oscillating signal adjusting circuit 52, and an oscillating signal generating circuit 53. More specifically, the duty cycle detecting circuit 51 detects the duty cycle D_bof the drive signal DR. When the input voltage V_inbecomes closer to the output voltage V_out, the duty cycle D_bof the drive signal DR becomes smaller. When the duty cycle D_bof the drive signal DR becomes smaller than a predetermined threshold, the duty cycle detecting circuit 51 generates an under-threshold signal UT. In response to the under-threshold signal UT, the oscillating signal adjusting circuit 52 causes the oscillating signal generating circuit 53 to prolong the period T_Sof the ramp oscillating signal RM (and the pulse oscillating signal PL). As appreciated from equation (1b), a longer period T_Sallows a larger duty cycle D_bto be possible since the minimum T_{ON, min}is constant. Moreover, the upper limit [(T_S-T_{ON, min})/T_S]*V_outof the applicable range of the input voltage V_inis expanded closer to the output voltage V_outwhen the period T_Sbecomes longer. As a result, the switching voltage regulator 50 according to the present invention can be applied with a broader range of input voltage V_in.

On the other hand, for avoiding the period T_Sfrom being prolonged so much that the switching frequency becomes too low, the duty cycle detecting circuit 51 generates an over-threshold signal OT when the duty cycle D_bof the drive signal DR becomes larger than the predetermined threshold. In response to the over-threshold signal OT, the oscillating signal adjusting circuit 52 causes the oscillating signal generating circuit 53 to shorten the period T_Sof the ramp oscillating signal RM (and the pulse oscillating signal PL).

FIG. 6 is a detailed circuit diagram showing the oscillating signal generating system 54 of FIG. 5. As seen from the comparison between FIG. 3 and FIG. 6, the oscillating signal generating system 54 of the second embodiment is different from the oscillating signal generating system 24 of the first embodiment in that the duty cycle detecting circuit 51 of the oscillating signal generating system 54 employs an AND logic gate 56 to generate the under-threshold signal UT and an OR logic gate 57 to generate the over-threshold signal OT.

FIG. 7 is a waveform timing chart showing an operation of the oscillating signal generating system 54 of FIG. 5. During the first and the second periods PP1 and PP2, the duty cycle D_bof the drive signal DR is larger than a threshold set by the second auxiliary signal DS2, so the over-threshold signal OT is generated. Assumed that the period T_Sof the first period PP1 stays at the minimum, the second and the third periods PP2 and PP3 still stay at the minimum period. During the third period PP3, the duty cycle D_bof the drive signal DR is smaller than the threshold set by the second auxiliary signal DS2, so is generated the under-threshold signal UT, by which the period of the fourth period PP4 is prolonged by dT₁in comparison with the former period. During the fourth period PP4, the duty cycle D_bof the drive signal DR is still smaller than the threshold set by the second auxiliary signal DS2, so is generated the under-threshold signal UT, by which the period of the fifth period PP5 is prolonged by dT₂in comparison with the former period. During the fifth period PP5, the duty cycle D_bof the drive signal DR becomes larger than the threshold set by the second auxiliary signal DS2, so is generated the over-threshold signal OT, by which the period of the sixth period PP6 is shortened by dT₃in comparison with the former period. Therefore, when the input voltage V_inbecomes closer to the output voltage V_out, the switching voltage regulator 50 according to the present invention automatically adjusts, i.e., either prolongs or shortens, the period T_S.

While the invention has been described by way of examples and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications.